JPH0455585U - - Google Patents
Info
- Publication number
- JPH0455585U JPH0455585U JP9741390U JP9741390U JPH0455585U JP H0455585 U JPH0455585 U JP H0455585U JP 9741390 U JP9741390 U JP 9741390U JP 9741390 U JP9741390 U JP 9741390U JP H0455585 U JPH0455585 U JP H0455585U
- Authority
- JP
- Japan
- Prior art keywords
- pin
- contact point
- power return
- lead
- return line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 2
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図はこの考案によるＩＣ測定用ソケツトの
構成図、第２図は第１図の使用状態の回路図、第
３図は従来技術によるＩＣ測定用ソケツトの構成
図、第４図は第３図の使用状態の回路図である。
１……ピン、１Ａ……接触点、１Ｂ……接触点
、２……ピン、１Ｃ……接触点１Ａと接触点１Ｂ
間のインピーダンス、２Ａ……接触点、２Ｂ……
接触点、２Ｃ……接触点２Ａと接触点２Ｂ間のイ
ンピーダンス、３……ＩＣ、４Ａ……電源帰路用
リード、４Ｂ……信号用リード、５……ピン、５
Ａ……リード４Ａとの接触点、５Ｂ……電源帰路
７との接触点、６……ソケツト、７……電源帰路
、８……信号線、９……信号帰路。
Fig. 1 is a block diagram of the IC measurement socket according to this invention, Fig. 2 is a circuit diagram of the usage state of Fig. 1, Fig. 3 is a block diagram of the IC measurement socket according to the prior art, and Fig. 4 is the It is a circuit diagram of the state of use of the figure. 1...pin, 1A...contact point, 1B...contact point, 2...pin, 1C...contact point 1A and contact point 1B
Impedance between 2A... Contact point, 2B...
Contact point, 2C... Impedance between contact point 2A and contact point 2B, 3... IC, 4A... Power return lead, 4B... Signal lead, 5... Pin, 5
A... Contact point with lead 4A, 5B... Contact point with power return path 7, 6... Socket, 7... Power return path, 8... Signal line, 9... Signal return path.
Claims (1)
と第２のピン２を接触させ、第１のピン１を電源
帰路７に接続し、第２のピン２を信号線帰路９に
接続することを特徴とするＩＣ測定用ソケツト。 Connect the first pin 1 to the power return lead 4A of IC3.
and a second pin 2 are brought into contact with each other, the first pin 1 is connected to a power return line 7, and the second pin 2 is connected to a signal line return line 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9741390U JPH0455585U (en) | 1990-09-17 | 1990-09-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9741390U JPH0455585U (en) | 1990-09-17 | 1990-09-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0455585U true JPH0455585U (en) | 1992-05-13 |
Family
ID=31837761
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9741390U Pending JPH0455585U (en) | 1990-09-17 | 1990-09-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0455585U (en) |
-
1990
- 1990-09-17 JP JP9741390U patent/JPH0455585U/ja active Pending