JPH0455012B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a variable length code conversion method applied to the transmission and recording of digital signals. Conventional configuration and its problems In general, the following five characteristics are known as necessary for a channel code when magnetically recording a digital signal. (1): Minimum magnetization reversal interval Tmin Since the magnetic recording/reproducing system has the property of blocking high frequency components, a code in which magnetization reversal occurs frequently is not appropriate. Therefore, it is desirable that the Tmin is large. (2): Maximum magnetization reversal interval Tmax If no magnetization reversal continues for too long, it becomes difficult to extract clock information and self-clock function cannot be obtained.To avoid this, Tmax is set to a small value. This is desirable. (3): Detection window _TW This is a measure of the phase direction margin against time axis fluctuations such as jitter of the reproduced signal and peak shift due to waveform interference, and the larger the value, the better. (4): Minimum number of consecutive bits d This is the minimum number of consecutive bits regarding “0” and “1”, and is given by d=T _nio / _TW . (5): Maximum number of consecutive bits k This is the maximum value of the number of consecutive bits regarding “0” and “1”, and is given by k = T _nax / _TW . Hereinafter, the code subjected to the constraints (4) and (5) above will be referred to as a (d,k) code. By the way, in order to obtain the (d, k) code, M
It is necessary to convert a bit data word into a channel code word of N bits, _which is larger than M.
Since is M/NT (T is the 1-bit length of the data word), M/N must be as large as possible due to the constraint in (3) above. In the following, a circuit that converts an M-bit data word into an N-bit channel code word is called a modulation circuit, and a circuit that inversely converts an N-bit channel code word into an M-bit data word is called a demodulating circuit. It's called a circuit. Conventionally, various code conversion methods have been proposed from the above viewpoint, and 3PM, HDM-3, 2/3 conversion codes, etc. are known. According to the above definition, 3PM is T _nio = 1.5T, T _nax
=6T, T _W =0.5T, d=3, and k=12. HDM-3 has T _nio = 2T, T _nax = 8.33T, T _W =
The channel code is 0.33T, d=6, and k=25. The 2/3 conversion code is T _nio = 1.33T, T _nax = 5.33T, T _W
=0.67T, d=2, k=8. On the other hand, the theoretical upper limit of T _W for d and k is already known (DTTang and L,R,Bahl,
Information and Control, 17 , No.5, P.436,
(1970), the following values are obtained for each of the above three types of channel codes. T _W 0.545T (d=3, k=12, 3PM) T _W 0.361T (d=6, k=25, HDM-3) T _W 0.679T (d=2, k=8, 2/3 conversion) Therefore, there is a possibility that there is a channel code with even better performance than the above three types of channel codes. Generally, the most effective code conversion method to achieve the same d, k and T _W is the variable length code conversion method. This consists of a channel codeword N ₁ with a basic bit length N _nio and a bit length i times N _nio (1i
i _nax , i: integer) iN _nio bit channel code word N _i
, a data word M ₁ of basic bit length M _nio and a data word M i of iM nio bits whose bit length is i times M _{nio are} obtained _.
corresponds to a N _i -bit channel codeword. By doing so, T _W of the channel code word becomes T _W =M _i /N _i =iM _nio /iN _nio =M _nio /N _nio = constant. A fixed length that satisfies the same d, k, and T _W , i.e., a channel codeword length N _F with i _nax = 1, and a variable length, i.e., the maximum value of the channel codeword length i _nax N _nio of i _nax 2.
In general, the following formula holds true, and N _F i _nax /N _nio variable-length codes require a shorter channel code word length than fixed-length codes. However, there is still no variable-length code conversion method that can most efficiently and systematically obtain such (d,k)-limited variable-length codes. Purpose of the Invention The present invention relates to the number of consecutive bits of "0" or "1" at both the left and right ends of a channel codeword to be used, connection conditions between channel codewords, method of selecting channel codewords, and data words. Appropriate rules are established in relation to the correspondence with channel code words, and the detection window width T _W is constant.
In other words, the purpose is to provide a systematic variable-length code conversion method to obtain a (d, k) limited variable-length code where M _i /N _i = constant (i = 1, 2, ..., i _nax ). That is. Structure of the Invention In order to achieve the above object, the present invention sets the minimum number of bits of a data word to Mmin, the minimum number of bits of a code word to Nmin, and for an integer i of 2 or more, i.
In a variable length code conversion method for converting a data word of Mmin bits into a channel codeword of i/Nmin bits, d is an integer of 2 or more, k is an integer larger than the above d, and d1 is a positive number of the above d-1 or less. be an integer of
Among the 2· ^{i.Nmin channel codewords obtained by i·Nmin} bits, the number 1 of consecutive “1” bits at the starting end L is greater than or equal to the above d1 and less than the above k−d+1, and the number of consecutive “1” bits 1 at the starting end L is equal to or greater than the above k−d+1, and the terminal end R The number r of consecutive bits of “1” or “0” in the above k
−d+1 or less, and the number of consecutive “1” bits in the intermediate portion B sandwiched between the L and the R;
A channel code word in which the number of consecutive bits of “0” is greater than or equal to the above k and less than or equal to the above k, and the above i/Nmin
+2・(d−1)≦k and the above i・Nmin≦k−d
Only when +1 holds true, the channel codeword containing the channel codeword in which all i+Nmin bits are "1" is set as CCO, and "1" is changed to "0" for this CCO and all bits of CCO, and "0" is set. is replaced with "1", the CCO and the code word of the back pattern are made to correspond to the same input data word, and the number of consecutive bits of the same binary value is greater than or equal to the above d and less than or equal to the above k. CCO or
This configuration is characterized by selecting a CCO, thereby making it possible to effectively obtain (d, k) limited variable length channel codewords. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on the drawings. I will explain the first rule in detail. Figure 1a,
b indicates a channel codeword pattern of iN _nio bits, and channel codewords are selected based on the following criteria in order to satisfy the d and k restrictions. (): Let d ₁ be an integer between 1 and d−1, and “1”
For each channel code word of bit length starting with iN _nio (1ii _nax , i: integer),
Number l of consecutive bits of “1” on the left side L of the channel code word and “0” and “1” on the right side R
The number of consecutive bits r is given by the following formula (1) d ₁ lk-d+1, dd ₁ rk-d
+1 ... is in the range shown in (1), and in the middle part B of b = iN _nio -l - r bits, d bits or more k
The channel code word CC0 is composed of L, B, and R, in which successive "0" and "1" appear alternately after the bit, and all bits of this CC0 are changed from "0" to "1". ”, “1”
Back pattern 0 of CC0 with “0” replaced
and choose. However, b=0 for CC0 and 0
including those of (): Among the channel code words CC0 selected in (), the channel code word for which l is less than or equal to d-1
CW0 and its back pattern 0 are paired, and each pair is associated with a data word. (): Similarly, among CC0, the channel code word CW1 whose l is greater than or equal to d and its back pattern
Pair CW1 and associate data words with each pair. Next, we will show the connection rules for the channel codewords shown in () to () above, and clarify that the d and k restrictions are satisfied by the connection rules. However, l=
l ₁ , r=r ₁ , first channel code word W1, l=l ₂ ,
Let us consider the connection of the second channel code word W2 where r= _r2 . Note that in the following, the final bit of W1 is assumed to be LB. Connection rule When either CW0 or 0 must be used for W2, (1) When LB = "1", W2 = CW0; When LB = "0", W2 = 0. This is because when LB is “1”, W2=
Assuming CW0, the L part of 0 is "0" of d-1 bits or less, so "0" of d-1 bits or less occurs at the connection between W1 and W2, which violates the d restriction. In this case, W2=0 is not appropriate. Conversely, when W2 = CW0, the maximum number of consecutive "1" bits in the R part of W1 is k-d+1,
Since the maximum number of consecutive bits of "1" in the L part of CW0 is d-1, W1 and W2 of LB = "1" =
The maximum number of consecutive bits of "1" at the connection part of CW0 is k (=k-do1+d-1). Furthermore, the R part of W1 has at least dd ₁ bits of "1", and the minimum value of "1" in the L part of CW0 is d ₁
Therefore, at least d (=d-d ₁ +d ₁ ) bits of "1" exist at the connection between W1 and W2=CW0 where LB="1", and the d restriction is satisfied. What I have stated above is that when LB = “0”, W2 =
The case of setting CW0 can be shown in exactly the same way. Next, when either CW1 or 1 must be used for W2, (ii): When the number of consecutive "1" bits in the R part of W1 is d or more, W2 = 1 (iii): R of W1 When the number of consecutive "1" bits in the R part of W1 is d-1 or less, W2 = CW1 (iv): When the number of consecutive "0" bits in the R part of W1 is d or more, W2 = CW1 (v): W1 When the number of consecutive "0" bits in the R part of is less than or equal to d-1, W2=1. This is due to the following reason. First, regarding (ii), the number of consecutive "0" bits in the L part of W2=1 is greater than or equal to d and less than or equal to k-d+1. On the other hand, the R part of W1 has more than d bits k−d+
Since it is “1” of less than 1 bit, W1 and W2 =
Satisfies d and k restrictions at the connection part of CW1. Next, regarding (iii), "1" in the R part of W1 is d-
1 bit or less, W2 = “1” in the L part of CW1
Since is less than k-d+1 bits, it satisfies the k restriction. On the other hand, “1” in the R part of W1 is at least d
−d There is ₁ bit, and the L part of W2=CW1 is also at least
Since there is d ₁ bit, it also satisfies the d restriction. As mentioned above, due to the connection laws (ii) and (iii),
It can be seen that the d and k restrictions are satisfied. Furthermore, (iv) and (v)
Satisfying the d and k restrictions also by the connection law is,
It can be shown in the same way as cases (ii) and (iii), but
It is omitted here. The connection rules (i) to (v) above are such that when the number of consecutive bits of "0" or "1" in the R part of W1 is less than or equal to d-1, E = "0", and when it is greater than or equal to d, E = "1". ” is determined. For the CW0 and 0, F=“0”, and for the CW1 and 1, F=
If F is a value determined by whether or not the number of consecutive bits of "0" or "1" in the L part is less than or equal to d-1, then W2 is the reverse pattern for W1. Then, Y = “1”, and if it is not used as a back pattern, Y = “0”. The value Y is based on the connection law (i) ~
From Table 1, which summarizes (v) into a truth table using LB, E, and F, it can be seen that it is given by equation (2). Y=(+)・{+(○+)} ……(2) However, “+” is logical sum, “・” is logical value, “○+”
represents exclusive OR, and "-" represents negation. Note that all iN _nio bits are “1” or “0”.
Communication channel code word, following formula (3) iN _nio k−d+1 ……(3)

[Table] holds, and from the above connection rules (i) to (v) and Fig. 2, the following equation (4) iN _nio +2(d-1)k ...(4) holds only when Included in 0. For such a channel codeword, F=
It is clear that by setting "1" and E="1", equation (2) can be applied as is. Therefore, such channel codewords are the CC0 and 0
Even if it is included in , there is no change in the connection rules (i) to (v) above,
Also, this channel code word belongs to CW1 and CW0. It has been clarified that (d, k) codes can be obtained by the constraints and connection rules for channel codewords as described above, but in order to increase the number of channel codewords belonging to CC0 and 0 as much as possible, Select ₁ as the next value. Let d′ be the largest integer not exceeding d/2, then d ₁
is given by either equation (5) or (6). d ₁ = d' ... (5) d ₁ = d - d' ... (6) Note that when d is an even number, the results of equation (5) and equation (6) are equal. The reason for choosing d ₁ in equation (5) or equation (6) is as follows. The value of l within the range of equation (1) is (k−d+1−
d ₁ +1), and r is (k-d+1-d+
d ₁ +1). Therefore, the number of combinations of l and r is (k-d-d ₁ +2)(k-2d-d ₁ +2) =-2(d ₁ -d/2) ² +(k+d+2)(k-2d+2
) +d ² /2 (7), and the number of combinations is maximum when d ₁ =d/2. However, since d ₁ is a positive integer, when d is a number, it is maximum when the value is shown in equation (5) and equation (6). The number of channel code words CC0 and 0 is proportional to the number of combinations of l and r, so when the number of combinations of l and r is maximum, the number of channel code words CC0 and
The number of CC0 is also maximized. In the following, d ₁ is the value given by equation (5), but d
It goes without saying that similar results can be obtained even when is an odd number. When applying the connection rules shown in (i) to (v) above to a channel code word that is subject to the constraints described above, a channel code that satisfies the d and k restrictions can be obtained. Having clarified the following, the conditions for selecting a channel codeword for correct modulation and demodulation when the variable length code conversion method is applied to these channel codewords and connection conditions will be explained. When channel codewords with different bit lengths are used, in order to correctly demodulate to the original data word, in the bit string obtained by connecting channel codewords with different bit lengths, those channel codewords It is sufficient if the word boundaries can be correctly identified. In other words, when the minimum value of the channel codeword to be used is N _nio and the maximum value is N _nax (=i _nax・N _nio ), communication of N ₁ (=i ₁ N _nio , 1i ₁ i _nax ) bits. When channel codeword n ₁ and N ₂ (=i ₂ N _nio , 1i ₂ i _nax ) bit channel code word _{n 2 are} connected, X
(N ₁ <X<N _nax ) bit is the third channel code word n ₃
, the word boundary between n ₁ and n ₂ can be correctly determined. That is, as shown in Fig. 3, even if we sequentially examine N _nax bits, N _nax-1 bits, ..., X bits, ... N ₁ +N _nio bits from the beginning of n ₁ ,
None of them matched the channel codeword being used, and it turned out that N ₁ was sent after all.
Can correctly identify the word boundary between n ₁ and n ₂ . If the above can be said for all connections of channel code words used, all word boundaries can be correctly determined and correct demodulation can be performed. A channel codeword that satisfies the above requirements is determined as follows. Bit length is iN _nio (1ii _nax )
CC0 _i
If the number is T(i), generally the following relationship is satisfied: T(2i)>T(i) ² ...(8). For example, if i=1,
The communication channel code word CC0 ₂ with a length of _{2N nio bits} contains _the above (i) to
T obtained by the connection law uniquely defined by (v)
(1) Contains a channel code word other than ^{the two} 2N _nio bit channel code words, that is, a channel code word CC1 unique to 2N _nio bits. Therefore, the communication channel code word with a length of 2N _nio bits is the above-mentioned 2N _nio bit unique communication channel code word CC1 and its back pattern.
By using CC1, the bit string of 2N _nio bits obtained by connecting N _nio bit channel code words does not match. In the same way, a unique channel code word for iN _nio (3ii _nax ) bits can be obtained, and by using these channel code words CC1 and 1, word boundaries can be correctly identified in the bit string generated by modulation. can be determined. Next, the present invention will be explained in detail using a specific example. Below, the channel code word refers to a code word belonging to CC1 and CC1. Example 1 This example has d=5, k=18, N _nio =5, M _nio
=2, N _nax =30, i _nax =6, TW=0.4T, T _nio =
This is a variable length code conversion method that yields a channel code of 2T, T _nax = 7.2T. The number of channel code words that can be used in this embodiment is 130 as shown in Table 2 a, b, and c (excluding back patterns). As mentioned earlier, these channel code words have their own bit lengths, and each channel code word is
As long as the connection rules defined in (i) to (v) above are followed, the bit strings generated by the connection of other channel code words will not match.

【table】

【table】

【table】

[Table] This will be explained below using a specific example. The 5-bit communication channel code words No. 1 and No. 2 are expressed as (i) to
There are four types of bit strings as a result of connection according to the connection rule (v): “11000” + “00111” (No.1 + No.1) “11000” + “00000” (No.1 + No.2) “11111” + “11000” (No.2 + No.1) “11111” + “00000” ( No. 2 + No. 2) It can be seen that these four types of bit strings with a bit length of 10 are clearly different from the 10-bit channel code words No. 3 to No. 6 in Table 2. Similarly, No. 15 of the 15-bit communication channel code word
is “111000000000000” = “1110000000” + “00000”
(No. 15 = No. 5 + No. 2), the 10-bit channel code No. 5 is connected to the back pattern No. 2 of the 5-bit channel code word No. 2. However, according to the connection law,
In the case of connection between No. 5 and No. 2, “1110000000” + “11111” = “111000000011111”
(No. 5 + No. 2). Therefore, the channel code word for No. 15 is No.
It can be seen that this was not caused by the connection between No. 5 and No. 2. The same is true for all other channel codewords in Table 2. Table 2 also lists data words corresponding to each channel code word. As is clear from Table 2, the ratio of the number of bits in the data word to the number of bits in the channel code word is constant at 2:5, so the transmission speed of the channel code is constant, and T _W =0.4T. is also constant. The correspondence between data words and channel code words may be determined as follows. (a): Since T _W =0.4T, a 2-bit data word is associated with a 5-bit channel code word.
In this embodiment, "00" is associated with the No. 1 channel code word, and "01" is associated with the No. 2 channel code word. For example, if No. 1 = "11"
, "10" may correspond to No. 2. In short, two 5-bit channel codewords contain 4 bits.
It is sufficient to match any two of the two 2-bit data words. In the following, explanation will be given by taking the correspondence shown in Table 2 as an example. (b): There is no problem with the data words “00” and “01” because there are corresponding channel code words. However, since data words "10" and "11" do not have corresponding 5-bit channel code words, they are made to correspond to 10-bit channel code words, but as is, the data words and channel code words The bit length ratio is not 2:5. Therefore, 4-bit data words starting with "01" and "11" are made to correspond to 10-bit channel code words. Since there are four 10-bit channel code words, each of the four data words starting with "10" has a corresponding channel code word. (c): Similar to (b), a 15-bit channel code word is used to supplement the four 4-bit data words starting with "11". At this time, the data word is also 6
Become a bit. Such a data word is “11”
There are 16 items starting with . Since there are nine 15-bit channel code words, among the 6-bit data words starting with "11", corresponding channel code words exist for "110000" to "111000". (d): Similarly, the data words "11100100" to "11110011" are made to correspond to the 20-bit channel code words No. 16 to No. 31. (e): Correlate the data words “1111010000” to “1111110001” with the 25-bit communication channel code words No. 32 to No. 65. : There are 56 data words from “111111001000” to “111111111111”. On the other hand, since the number of 30-bit channel code words is 65, all of the above 12-bit data words correspond to 30-bit channel code words. As described in (a) to (f) above, the channel code word corresponds to every combination of data bit strings, and the modulation is uniquely performed. A block diagram of the modulation circuit of this embodiment is shown in FIG. The operation of the modulation circuit will be explained below with reference to FIG. Note that the clock for the data bit string is f _d (bits/s), and the clock for the channel codeword is f _r (=5/2f _d ) (bits/s). First, a bit string of the following equation (9) "01/(A) 111111111111/(B) 111000/(C) 0111100110/(D)" is assumed as a data bit string. It is assumed that there is no data bit string before and after equation (9), and that (A) in equation (9) is the start of the data bit string. Operation 0: Shift register 10 consisting of 12 bits
takes in the first 12 bits of equation (9), that is, a="011111111111". Operation 1: The 12 bits taken into the shift register 10 are taken into the latch circuit 12 consisting of 12 bits by the control pulse CP from the control pulse generation circuit 11. The contents of the latch circuit 12 at this time are also the same as a. The 12 bits taken into the latch circuit 12 are applied to the input terminal of the code conversion circuit 13. In the code conversion circuit 13, the communication channel code word CW corresponding to the applied data word and a value F indicating whether or not the number of consecutive "1"s in the L part of the CW are equal to or greater than d (if equal to or greater than d, F=" 1”,
If it is less than or equal to d-1, F = "0"), and a value E' indicating whether the number of consecutive bits of "0" or "1" in the R section is equal to or greater than d (if it is equal to or greater than d, E' = "1",
If it is less than or equal to d-1, E' = "0"), and the value I that represents how many times the number of bits of CW is N _nio = 5
(When N=5, I=“001”, when N=10, I=
“010”, when N=15 I=“011”, when N=20 I
="100", I="101" when N=25, I="110" when N=30) are sent as outputs. Table 3 shows an input/output correspondence table of the code conversion circuit 13. Note that "X" in Table 3 means an unrelated value. As is clear from Table 3,

[Table] The input/output characteristics of the code conversion circuit 13 are as follows:
iM _nio = 2i (1i6) bits in Table 2
When it is equal to any of the 2i bit data words, it is sufficient that modulation is performed only on that 2i bit. In this case, the input/output of the code conversion circuit 13 corresponds to the case No. 1 in Table 3, and modulation is performed only on the first "01" of a, and the 10 bits following "01" are modulated. It has nothing to do with the value. Therefore, the output of the code conversion circuit 13 contains the channel code word CW.
= “11111”, F = “1”, E′ = “1” and I =
“001” appears. Operation 2: The value of I obtained as a result of Operation 1 is immediately sent to the control pulse generation circuit 11. Based on the value of I, the control pulse generating circuit 11 detects that the shift register 10 has been shifted by 2×I bits, and generates a control pulse CP. In this case, since I="001", the first two bits of the shift register 10, that is, the underlined part of a=" 01 11111111111" is shifted out from the shift register 10, and then the control pulse CP is occurs. Operation 3: Control pulse generated in operation 2
Due to the CP, CW="11111" appearing at the output of the code conversion circuit 13 is taken into the parallel-serial converter 14 and sequentially sent out with the clock of _fr . On the other hand, the values of F and E' are taken into the inversion control circuit 15, and F is held in the last bit holding circuit 16 along with the value E of E' of the channel code word CW' sent out immediately before. Last bit of CW′
A signal Y is applied to the exclusive OR gate 17 to be used together with the LB and to control whether or not to send out the CW as a back pattern according to the connection rules (i) to (v). Note that Y=“1” if the back pattern is used, and Y=“0” otherwise, so Y is given by equation (2). In this case, since it is the first data word,
LB and E are set to an initial value of "0".
Therefore, by F="1",
From equation (2), Y=“1”, so CW=
“11111” is sent in the back pattern. Operation 4: In parallel with operation 3, the control pulse CP generated in operation 2 is applied to the latch circuit 12, and new 12 bits are taken into the latch circuit 12. In this case, as mentioned in operation 2, at this point, shift register 1
Since the content of 0 is the 12 bits following "01" in equation (9), that is, β = "111111111111", the content of the latch circuit 12 is also β. Then, operations 1 to 4 are repeated again, and the content of the latch circuit 12 becomes γ=“111000011110” following “01111111111111” in equation (9), and operations 1 to 4 are repeated for this value. For the data bit string in equation (9). FIG. 5 shows a time chart of the modulation circuit of FIG. 4.
Each symbol in Fig. 5 represents 0 to 4 of the above operation.
This is the same as the one used in the explanation. In addition, the broken line in FIG. 5 represents the same time. or,
“X” indicates an irrelevant value. Next, demodulation will be explained. As mentioned above, if word boundaries can be correctly determined in the bit string created by modulation, correct demodulation will be performed. Furthermore, the channel code words used in this embodiment are selected so as to enable accurate discrimination of word boundaries in bit strings generated by connections. Therefore, the block diagram of the demodulation circuit is as shown in FIG. The operation of the demodulation circuit will be explained below using FIG. 6. First, the following equation (10) corresponding to the data bit string of equation (9) is assumed as a channel code word. “00000/(A)′ 11111000000000000000011111000
0/(B)′ “000111111111111/(C)′ 1111000001111111000
0/(D)′”…(10) Also, assume that (A)′ in equation (10) is the start of the channel code word. Operation 0: The shift register 30 consisting of 30 bits is as shown in equation (10). The first 30 bits, that is, a′ = “000001111100000000000000001111” are taken in. As a method for detecting the beginning of the channel code word, a known technique such as using a mark pattern is adopted. Operation 1: Transfer to the shift register 30. The 30 bits taken in are taken into a latch circuit 32 consisting of 30 bits by the control pulse CP from the control pulse generation circuit 31.The contents of the latch circuit 32 are also the same as a' above.Latch circuit 32 was incorporated into
The 30 bits are applied to the input terminal of the sign inversion circuit 33. The sign inversion circuit 33 converts the data word DW corresponding to the added 30 bits into
The value I that represents how many times the number of bits M of DW is M _nio = 2 (I = “001” when M = 2, I = “001” when M = 4)
= "010", when M = 6 I = "011", when M = 8 I = "100", when M = 10 I = "101", when M = 12 I = "110") Send as output. Table 4 shows a part of the input/output correspondence table of the code inversion circuit 33. Note that the horizontal line in the input column of Table 4 indicates that the value of that portion is unrelated. However, the numbers shown in the remarks column are the numbers attached to the communication channel code words in Table 2, and the input of the code inverse conversion circuit 33 in FIG. 6, for example,
Even if a 30-bit string starting with “11111” is sent, the first 30 bits
If the channel code word with the number shown in the remarks column of Table 4 exists in the 10-bit or more part, the data word “01” corresponding to the channel code word “11111”
is not output. As an example, the communication channel code word of No. 9 in Table 4 is equal to No. 121 of Table 2, and this is written in the remarks column of No. 1 of Table 4, so No. 9 of Table 4 is the same as No. 121 of Table 2. Even if the first 5 bits of No. 9 are equal to “11111” of No. 1, the output data word in this case is not “01” but “111111111111”.
becomes. Conversely, the following bit string obtained by connecting No. 1 and No. 9 in Table 4 “11111/No. 1 00000111111111111111100000111
1/No. 9'' from the beginning 5i (i = 2, 3, 4, 5, 6) bits are not equal to any of the channel code words shown in the remarks column of Table 4 No. 1. Therefore, , the data word “01” corresponding to the channel code word “11111” is the output. By using the input/output correspondence table as above, the word boundaries of the channel code word can be correctly determined. In this case, , the input and output of the code inversion circuit 33 corresponds to the case of the back pattern of No. 1 in Table 4, and the data words DW="01" and I="001" are output from the code inversion circuit 33. Operation 2: The value of I obtained as a result of operation 1 is immediately sent to the control pulse generation circuit 31.The control pulse generation circuit 31

[Table] Based on the value, the shift register 30
Detects bit shift and generates control pulse CP. In this case, since I="001", the first 5 bits of the shift register 30, that is, the
The control pulse CP is generated after the first five bits "00000" of a' are shifted out. Operation 3: Control pulse generated in operation 2
Due to the CP, DW="01" appearing at the output of the sign inversion circuit 33 is taken into the parallel-serial converter 34 and sequentially sent out. Operation 4: In parallel with operation 3, the control pulse CP generated in operation 2 is also applied to the latch circuit 31, and new 30 bits are taken in. As described in operation 2, the contents of the shift register 30 become β'=“111110000000000000000111110000”, and the contents of the latch circuit 31 also become β'. Then, repeat steps 1 to 4 again.
Get “111111111111” as the data word. Further, operations 1 to 4 are repeated when the content of the latch circuit 31 is γ'=“000111111111111111100000111111” to obtain “111000” as the data word. In other words, the data word for equation (10) is “01 111111111111 111000”, which corresponds to the data bit strings (A) and (B) of equation (9) that were assumed when explaining the operation of the modulation circuit.
and (C), which means that correct demodulation has been performed. The configuration and operation of the modulation/demodulation circuit described above are not limited to this embodiment, but can be applied to all channel codes obtained by the variable length code conversion method of the present invention. As mentioned above, d=5, k=18, T _W
= 0.4T, T _nio = 2T, T _nax = 7.2T, and compared to the conventional HDM-3 which also satisfies T _nio = 2T, T _W is 21
The variable-length code conversion method of this embodiment, which can widen % and reduce T _nax by 15%, has a simple modulation/demodulation circuit configuration, making it suitable for practical applications such as digital image transmission and recording. The effect is huge. Example 2 This example has d=6, k=16, N _nio =6, M _nio
This is a variable tone code conversion method that can obtain a channel code of =2, N _nax =24, i _nax =4, TW = T/3, T _nio = 2T, and T _nax =16T/35.33T. The number of channel code words that can be used in this embodiment is 49 as shown in Table 5 (excluding back patterns). Table 5 also lists examples of data words corresponding to each channel code word. The suitability of these channel code words as variable tone channel code words was confirmed in the same manner as in Example 1, and the correspondence between data words and communication code words was also the same as in Example 1. obtained in the same way. The channel code obtained by the variable tone code conversion method of this embodiment is, compared to the conventional HDM-3,
T _W , T _nio are equivalent, k is 9 less, so T _nax
is 36% smaller.

【table】

[Table] As described above, the code conversion method of this embodiment provides a channel code with T _nax that is 36% smaller than that of the conventional HDM-3, and its practical effects are very large. Example 3 This example has d=3, k=12, N _nio =15, M _nio
This is a variable-length code conversion method that can obtain channel codes of =8, N _nax =30, i _nax =2, T _W =8/15T 0.533T, T _nio =1.6T, and T _nax =6.4T. The number of channel codewords that can be used in this example is
There are 180 with N _nio = 15 bits and 19502 with a bit length of 30 bits. Additionally, the 180 15-bit channel codewords correspond to the 8-bit data words “00000000” to “10110011” in the range below, and the 30-bit channel codewords correspond to 19456 in the range below. Match data words. Therefore, the 30-bit channel code “1011010000000000” to “11111111
11111111" words, there are 19502-19456=46 channel code words. Compared to the conventional 3PM, the variable length channel code by the variable key code conversion method has the same d and k, and T It has the feature that _W becomes wider by about 6.7%. Example 4 This example has d=2, k=7, N _nio =3, M _nio
= 2, N _nax = 15, i _nax = 5, T _W = 2/3T0.67T, T _nio = 4T/31.33T, T _nax = 14/3T4.67T is obtained by variable key code conversion. It's a method.
The number of channel code words that can be used in this embodiment is 20 as shown in Table 6 (excluding back patterns). Table 6 also lists examples of data words corresponding to each channel code word. The suitability of these channel code words as variable-length channel code words was confirmed in the same manner as in Example 1, and the correspondence between data words and channel code words was also the same as in Example 1. can be obtained in the same way. In the case of this embodiment, there are 9-, 12-, and 15-bit unique communication channel code words other than those in Table 6.
There are six as shown in Table 7. However, these channel code words cannot be mixed with the channel code words in Table 5. This is clear from the following example.

【table】

【table】

[Table] When the channel code words in Tables 6 and 7 are used together, channel code words of 12 bits or more are unnecessary, and data words are used in the No. 1 channel code word in Table 7, for example. “111111” can be matched. However, in this case, if you connect the channel code word in Table 6 No. 3 and the channel code word in Table 7 No. 1, you will get "111000000111"/No. 7 as shown below. The channel code word No. 7 appears, and according to the demodulation algorithm, this becomes a demodulation error. The reason for the above is that "111111" or "000000", which is not included in the 6-bit unique channel codeword, can appear in both the L and R parts of the 9-bit channel codeword. be. In such a case, it is necessary to use a channel code word in which 6 consecutive bits of "1" or "0" appear only in either the L part or the R part. In Table 6, 6 consecutive bits of “1” or “0” are R
A channel code word that appears only in the first part is used. I want to

[Table] Therefore, the same effect as shown in Table 6 can be obtained even with a channel code word in which 6 consecutive bits of "0" or "1" are limited only to the L part as shown in Table 8. As mentioned above, iN _nio bits of consecutive "1" or "0" are not included in the channel code word unique to the iN _nio bit length, but are included in the channel code word unique to the (i+1)N _nio bit length. As is clear from the above, what appears in both the L part and the R part is the formula
This is a case where (3) holds true and equation (4) does not hold true. That is, if iN _nio is within the range of formula (11),
The constraint condition for the L and R parts of a channel codeword of (i+1)N _nio bits or more is either Equation (12) or Equation (13) instead of Equation (3). k−2d+2<iN _nio −d+1 …(11) d ₁ liN _nio −1, d−d ₁ rk−d+
1 ...(12) or d ₁ lk-d+1, d-d ₁ riN _nio −
1...(13) In the case of this example, k-2d+2=5, k-d+
1 = 6, N _nio = 3, satisfying equation (11) with i = 2,
Consistent with the specific description above. Compared to the conventional 2/3 conversion code, the channel code obtained by the variable length code conversion method of this embodiment obtained in this way has d and T _W equal, and k can be reduced by 1, and 2 It is more suitable for high-density recording and high-speed transmission than the /3 conversion code, and its practical effects are great. Effects of the Invention As described above, the variable key code conversion method of the present invention places constraints on the number of consecutive "0"s and "1"s at both the left and right ends of a channel codeword, and appropriately selects channel codewords with different bit lengths. For example, as shown in Examples 1 to 4, T _W is 21% wider and T _nax is 15% smaller (5,
18) code, T _nax is 36% smaller (6,16) code,
A (3,12) code with T _W 6.7% wider than the conventional 3PM and a (2,7) code with k smaller by 1 than the conventional 2/3 conversion code can be obtained with a relatively simple circuit configuration. It has great practical effects in applications such as digital image transmission, magnetic recording, and digital audio recording.

[Brief explanation of drawings]

Figures 1a and b are diagrams showing the pattern of the channel codeword of iN _nio bits, Figure 2 is a diagram showing the conditions for the existence of a channel codeword with all "1"s, and Figure 3
The figure is a diagram explaining the determination of word boundaries of channel code words.
FIG. 4 is a first embodiment of the variable key code conversion method of the present invention.
FIG. 5 is a time chart of the modulation circuit in the first embodiment, and FIG. 6 is a block diagram of the demodulation circuit in the first embodiment. 10, 30... Shift register, 11, 31... Control pulse generation circuit, 12, 32... Latch circuit, 13... Code conversion circuit, 14, 34... Parallel-serial converter, 15... Inversion control circuit, 1
6... Final bit holding circuit, 17... Exclusive OR gate, 33... Sign inversion circuit.

Claims (1)

[Claims] 1. Let the minimum number of bits of a data word be Mmin, and the minimum number of bits of a code word be Nmin, and for an integer i of 2 or more, a data word of i·Mmin bits is a channel code of i·Nmin bits. In the variable-length code conversion method for converting into words, d is an integer of 2 or more, k is an integer larger than d, and d1 is a positive integer less than or equal to d-1, and 2· ⁱ obtained by i·Nmin bits. ^.Nm
Among the ⁱⁿ channel codewords, the number of consecutive bits of "1" at the start end L is greater than or equal to the above k-d.
+1 or less, and the number r of consecutive bits of "1" or "0" at the terminal part R is greater than or equal to said d-d1 and less than said k-d+1, and in the middle part B sandwiched between said L and said R. Both the number of consecutive bits of “1” and the number of consecutive bits of “0” are
The communication channel code word which is above k or less, and the i.
Nmin+2・(d−1)≦k and the above i・Nmin≦
Only when k−d+1 holds true, the channel codeword containing the channel codeword in which all i+Nmin bits are “1” is set as CCO, and for this CCO and all bits of CCO, “1” is changed to “0”, and “ 0” to “1”
Using the code word of the back pattern replaced with
A variable-length code conversion method, characterized in that the CCO and correspond to the same input data word, and the CCO or the CCO whose number of consecutive bits of the same binary value is greater than or equal to the d and less than or equal to the k is selected. 2 For the channel code word CCO and, a value F representing whether l is less than or equal to d-1, a value E representing whether r is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1, and a value F representing whether or not l is less than or equal to d-1. Selecting whether or not to make the second channel code word W2 the back pattern using the last bit LB of the first channel code word W1 when connecting two channel code words W1 and W2. A variable length code conversion method according to claim 1, characterized in that: 3 When l is ld-1, F="0", when ld, F="1", and when r is rd-1, E=
“0”, when rd, E = “1”, if W2 is a back pattern, Y = “1”, otherwise Y = “0”, and “+” is logically summed. , “・”
Claim No. 1, characterized in that when ``○+'' is logical product, ``○+'' is exclusive OR, and ``-'' is negated, Y=(LB+F){+(LB○+E)}. 2. The variable length code conversion method according to item 2. 4 Belonging to the communication channel code word CCO and
It is characterized by using channel code words CC1 and 1 obtained by deleting all channel code words of iNmin bits that are generated by connecting channel code words shorter than iNmin bits among channel code words of iNmin bits. A variable length code conversion method according to claim 3. 5. The variable length code conversion method according to claim 4, wherein 5d is 3 or more. 6. The variable length code conversion method according to claim 4 or claim 5, wherein d ₁ =d', where d' is the largest integer not exceeding d/2. 7. The variable length code conversion method according to claim 4 or 5, characterized in that when d is an odd number, d ₁ is d and d', and d ₁ = d - d'. . 8 d=5, k=18, Mmin=2, Nmin=5,
8. The variable length code conversion method according to claim 6 or 7, wherein imax=6. 9 d=6, k=16, Mmin=2, Nmin=6,
5. The variable length code conversion method according to claim 4, wherein imax=4. 10 d=3, k=12, Mmin=8, Nmin=15,
6. The variable length code conversion method according to claim 4 or 5, wherein imax=2. 11 i Nmin is k-2(d-1)<i Nmin
In the case of a value in the range k-d+1,
Among channel code words CC1 and 1, (i+1)
For channel codewords with Nmin bits or more, the above l and r are d ₁ lk-d+1 and d-d ₁ r
i Nmin-1 or d ₁ lNmin-1 and d-d ₁ rk-d+
6. The variable length code conversion method according to claim 4 or 5, characterized in that a channel code word in one of the ranges expressed by the two equations 1 is used. 12. The variable length code conversion method according to claim 11, wherein d ₁ is equal to d'. 13 When d is an odd number, the above d ₁ is equal to d
12. The variable length code conversion method according to claim 11, wherein the difference in d' is d ₁ =d - d'. 14 d=2, k=7, Mmin=2, Nmin=3,
13. The variable length code conversion method according to claim 12, wherein imax=5.