JPH0454069A - Shading correction circuit - Google Patents

Abstract

PURPOSE:To attain shading processing independently of a data form by selecting a data read from a data storage means in response to the data form based on a control means. CONSTITUTION:A data form signal 6 is inputted to a control means 1 in advance to select a white reference data RAM 2a and a white level reference data 4a is written to an address designated by an address of the signal 6. A black level reference data 4b is written similarly in a black reference data RAM 2b. A line signal 5 is selected as a reset signal 14 of an address counter 12 in the case of a point sequential data and the address is initialized for each line. In the case of a line sequential data, a 3-line signal 13 is selected and the address is initialized for each of 3-line. In the case of an area sequential data, the operation is similar to the case with the point sequential data. When a picture data is inputted, the control means 1 outputs an address 9 in response to the data form and the picture data is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shading correction circuit used in image devices such as image scanners, printers, and copying machines, and particularly to a shading correction circuit that handles color images.

[Conventional technology]

Conventionally, in image processing devices that handle two-dimensional color image data, image scanners often use line-sequential data, and printers and copiers often use field-sequential data. red), G
For example, input data separated into three primary colors (green) and B (blue) is shown in Figure 5 for point sequential data, Figure 6 for line sequential data, and Figure 7 for field sequential data. The data arrangement is as shown in , and in the main scanning direction, every 2WJ element is used for dot sequential data, all pixels are the same color data for line sequential data and field sequential data, and in the sub-scanning direction, dot sequential data and field sequential data are In data, all lines have the same color data, and in line sequential data, every two lines have the same color data.

On the other hand, in imaging equipment, sonification correction circuits are often used to correct variations in illuminance of light sources and variations in sensitivity of image sensors, color filters, lenses, etc.; The data arrangement differs depending on the format, and therefore a specific shading correction circuit is configured according to each data format.

[Problem to be solved by the invention]

In the conventional technology as described above, the shading correction circuit lacks versatility, and it is difficult to connect it to other devices with different data formats. For example, shading correction circuits used in image scanners that often use line-sequential data formats cannot be used in printers and copiers that often use frame-sequential data, so shading correction circuits that can handle frame-sequential data are available. I had to.

Therefore, it is an object of the present invention to provide a shading correction circuit that can handle a plurality of data formats.

[Means to solve the problem]

In order to solve the above problems, the present invention stores white reference data and black reference data that correspond to pixels and are used in calculations in a shading correction circuit that performs soning correction processing on color image data. a data storage means; a control means for controlling an address value specifying the data storage means according to a data format; and a control means for controlling an address value specifying the data storage means according to the data format; It is characterized by comprising a shading processing section that performs shading processing on input pixel data and outputs the resultant data.

[Effect]

According to the above configuration, data to be read from the data storage means is selected based on the data format based on the control means, and shading processing can be performed regardless of the data format.

〔Example〕

FIG. 1 is a block diagram of an embodiment of a shading correction circuit according to the present invention.

The control means 1 is for eliminating the adverse effect on calculations due to differences in data arrangement between data formats, such as using data of a different color when calculating data of the same color. It is composed of a counter, etc., and is synchronized with the input data with a data format signal 6 indicating whether the format of the input image data is dot sequential data, vA sequential data, or field sequential data, and a line signal 5 indicating the effective range of the data. By inputting the clock 8, the generation method of the address 9 is changed according to the data arrangement of each color and outputted to the white reference data RAM 2a and the black reference data RAM 2b.

The control means 1 will be explained based on FIG. 2. It has a line counter 10 for counting line signals for three lines, eight inputs, and a B input, and it selects one of the signals based on the signal input to the select terminal. It consists of a selector 11 that outputs an output, and an address counter 12 that counts addresses in synchronization with a clock, and a line signal 5 is input to the counter input of the line counter 10, the input of the selector 11, and the enable terminal E of the address counter 12, respectively. The Q output 13 of the line counter 40 is input to the B input of the selector 11, and the data format signal 6 is input to the select terminal S. The Y output 14 of the selector 11 is connected to the reset terminal R of the address counter 12, and the clock 8 is input to the clock terminal. With these configurations, the data format signal 6 is used to select which of the line signal 5 and the 3-line signal 13, in which one line is composed of line signals for three lines, is used as the reset signal 14 of the address counter 42, and the white reference data RAM 2a and the black Standard data R
Generate address 9 of AM2b.

In the case of dot sequential data and field sequential data, the address 9 uses the line signal 5 as the reset signal 14 of the address counter 12, and as shown in FIG. It is reset every time. 3 for M sequential data
The line signal 13 is used as the reset signal 14 of the address counter 12, and the period when the line signal is asserted as shown in FIG.
It is incremented in synchronization with the clock input, and is reset every time the 3rd line signal is negated. In Figure 2, the address counter is a counter, and the line counter 10
can be composed of a counter and a gate.

In this example, the output from the address counter is used as is as the address of the data storage means, but the white reference data RAM2a, ! ! If the A reference data RAM 2b is composed of a plurality of table data or a plurality of storage elements, it is also possible to select the table data or storage element using the upper bits of the address 9.

The white reference data RAM 2a and the black reference data RAM 2b correspond to data storage means, have a capacity of at least one line (number of pixels for one line x number of colors x bit length of pixels), and are RAMs for storing correction data.

The shading correction section 3 is a circuit for performing predetermined calculations for performing shading correction, and can be constructed from a known subtraction circuit and division circuit. The calculation formula for shading correction is shown below.

In the above equation, C is a normalization constant, which is 256 if the data length is 8 pints. Again...

is input data + I) out is output data, D+= is white reference data, and Dm is black reference data.

Next, the operation shown in FIG. 1 will be explained.

First, the white reference data 4a is stored in the white reference data RAM 2a,
In order to write the black reference data 4b to the black reference data RAM 2b, the data format signal 6 is input to the control means 1 in advance, the white reference data RAM 2a is selected, and the white reference data is written to the address specified by the address. Write 4a. The black reference data 4b is similarly written to the black reference data RAM 2a. At this time, the control means 1 changes the address generation method depending on the data format. For zero point sequential data, the control means 1 selects the line signal 5 as the reset signal 14 of the address counter 12, As shown in FIG. 3, addresses are initialized for each line.

For line sequential data, the 3-line signal 13 is selected, and as shown in FIG. 4, zero-plane sequential data in which addresses are initialized every three lines operates in the same way as dot sequential data.

The correction data is stored as described above, and when the image data is input, the control means 1 outputs the address 9 according to the data format, and corresponds to each pixel from the white reference data RAM 5 and the black reference data RAM 6. The corrected correction data is read out, and correction calculations are performed on the image data. In this case, the method of generating address 9 is the same as when writing correction data to RAM.

〔Effect of the invention〕

As explained above, the present invention enables arithmetic processing for each data format, significantly improves the versatility of an image processing device, and facilitates connection with other devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of the configuration of the control means 1, and FIG. 3 is a timing chart of the embodiment of the present invention during point sequential data processing.
FIG. 4 is a timing chart during line sequential data processing according to the embodiment of the present invention, FIG. 5 is an explanatory diagram showing a data array of point sequential data, and FIG. 6 is an explanatory diagram showing a data array of line sequential data. , FIG. 7 is an explanatory diagram showing the data arrangement of the frame sequential data. 1 ・ ・ 2 a, 3 ・ ・ 4 a ・ 4 b ・ 10 ・ 11 ・ 12 ・ Sequential circuit Shading correction section White reference data RAM Black reference data RAM Line counter selector Address counter Applicant Seiko Representative of Denshi Kogyo Co., Ltd. Patent attorney Keiyuki Hayashi □ Principal foot examiner RmOGmo Bmo Rm+ Qnn+ &n+
Rmz Grn2 Brr+2-Fig. --GonGo
o Go GI2 G+3 ----- G+n32
0 G2T G22 (723---G2nRrr+
n Rmo Rm+ Rm2 Rm3 Gmo Gm+ Gm2Gm3 mn Boo Bo+ BOZ &+3 ----- B
anB+□ BIT B12 8+3 -----
B1n820 B21 B22 B23 -----
BznBmo Bm+ Bm2Bm3 8m n Diagram

Claims (1)

[Claims] In a shading correction circuit that performs shading correction processing on color image data, data storage means for storing white reference data and black reference data corresponding to pixels and used in calculations, and the data storage means are designated according to the data format. It consists of a control means for controlling an address value, and a shading processing section that performs shading processing on input pixel data and outputs it using the data in the data storage means stored under the address value specified by the control means. A shading correction circuit characterized by: