JPH0453317A - Reference signal generator capable of fine adjustment - Google Patents

Abstract

PURPOSE:To obtain an output signal with high accuracy even when an inexpensive crystal oscillator is used as a reference signal source by controlling the output frequency of a synthesizer signal source capable of fine adjustment with a reference signal applied externally. CONSTITUTION:The output of a PLL circuit 21B being a component of a synthesizer signal source 21 is frequency-divided, its relevant output is mixed to a crystal oscillator (TCXO) 21A being a reference signal source to form the synthesizer signal source 21 whose fine adjustment is attained by an external digital signal. A variable frequency divider 21C in the synthesizer signal source 21 is controlled by a reference signal fed externally (sender side). Thus, even when a comparatively inexpensive reference signal source (crystal reference signal source) is employed, the accuracy of the oscillating frequency is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for detecting
The present invention relates to a finely correctable reference signal generator useful in finely adjusting a synthesizer signal source.

[Summary of the Invention] The reference signal generator of the present invention mixes the frequency of a synthesizer signal source formed by a PLL circuit using a crystal oscillator as a reference signal source and a reference signal frequency supplied from the outside, It is equipped with a counter that counts the difference signal between two frequencies.

The output frequency of the synthesizer signal source can be corrected in extremely small steps by varying the frequency division ratio of the variable frequency divider constituting the synthesizer signal source based on the output of this counter.

[Prior art J] In some mobile communication systems using satellites, the frequency is variable in extremely small steps in order to selectively receive information from several thousand channels modulated on the carrier frequency of the SHF band. In addition, there is a need for a reference signal source whose frequency can be calibrated using a reference signal and whose frequency can be finely corrected.

Figure 3 shows an overview of the transceiver of a ground station that uses such satellite communication (Inmarsat), with antenna 1
The radio waves input from the SHF are transmitted via transponder 2.
Amplified by amplifier 3, for example, the received radio wave is 1530MH2
The signal of ~1545 Mn2 is output to the first mixer 4 at a first intermediate frequency of 95.55 Ml1. be drowned. The signal is then supplied to the second mixer 6 via the first IF amplifier 5, and the second mixer 6 further outputs the second intermediate frequency 33.
．． It is converted to 75KH.

This second intermediate frequency signal passes through an IF amplifier 7, and a demodulator 8 detects transmission data.

A carrier wave for transmission is synthesized by a first PLL circuit 9 and a second PLL circuit 10. That is, 96.21 MII□ to 117.16 output from the first PLL circuit 9
The frequency signal of M12 is modulated by the modulator 11, supplied to the third mixer 12, and output from the second PLL circuit 10. For example, it is mixed with a 1529.34MH□ signal.

Then, the mixed output is 1625.55Ml2~1
The transmission frequency signals of 640 and 55Ml2 are output from the output amplifier 13.
The signal is supplied to the transponder 2 via the antenna 1, and transmitted from the antenna 1 to the communication satellite.

Also, this mixed output is 1625.55MH, ~1
The signal of 640, 55MH is sent to the first mixer 4 described above.
to form a first intermediate frequency and a second PLL.
The output frequency of circuit 10 is fed to a second mixer 6 to form a second intermediate frequency.

In the case of Inmarsat communication, for example, if the number of transmission and reception channels is 3000 and the band of each channel is 5KH2, the center frequency of the first PLL circuit 9 is 5KH2 to select each channel. It is necessary to change the frequency by at least 15 MHz in steps.

Therefore, the first PLL circuit 10 and the second PLL circuit 9 are provided with fairly accurate reference signals S, +10. (1
5Ml2) is supplied from the reference signal generator 20.

In addition, the first PLL circuit 9 has an output frequency of at least 5
A variable frequency divider is provided so that it can be changed at the step of KH2, and the frequency division ratio is controlled by a transmission/reception control section 14 that controls the entire transmitter/receiver.

[Problems to be Solved by the Invention] By the way, the above-described first and second PLL circuits 9. When the reference signal SR supplied to the IO is formed using a normal crystal oscillator, the reference signal SR supplied to the IO is
It is preferable to set it to H2 or less, but if the reference signal SR is lO
When it is MHz, the second PLL circuit IO is a multiplier [
In order to operate stably, the accuracy of the reference signal SR must be approximately
It is required to be less than ±lppm (1ppm=1o-t+).

However, it is extremely difficult to construct a reference signal source that maintains the above-mentioned accuracy in any surrounding environment, and a reference signal source that can maintain the above-mentioned accuracy is expensive and large. Therefore, there was a problem in that the cost of mobile radio equipment increased.

Means for Solving Problem E] In order to solve this problem, the present invention provides a synthesizer signal source in which fine correction is performed by an external signal, and a reference signal supplied from the outside (satellite calibration transmission frequency). ), and a variable component forming the synthesizer signal source, comprising a multiplier for detecting a difference signal of This constitutes a reference signal generator that is capable of fine correction and is equipped with means for controlling a frequency generator.

[Operation] By dividing the output of the PLL circuit that forms the synthesizer signal source and mixing it with a signal corresponding to the reference signal source, a synthesizer signal source that can be finely adjusted by a digital external signal is formed. Since the variable frequency divider in the synthesizer signal source is controlled by the reference signal supplied from the outside (transmission side), even if a relatively inexpensive reference signal source (crystal reference signal source) is used, the generated frequency The degree of accumulation can be increased.

[Embodiment] FIG. 1 shows a block diagram of a finely correctable reference signal source according to an embodiment of the present invention, in which 21 is a temperature compensated crystal oscillator (TCXO) 21A; PLL circuit 21B using 21A as a reference signal source,
Frequency divider 21. A synthesizer signal source composed of C1 and a mixer 22D; 22 is a multiplier composed of L L circuits, etc.; 23 is an external reference signal Srr manually inputted from the outside; 28 is a frequency divider that divides the output of the crystal oscillator 21A, and 24 is the frequency mixer that uses the output of the frequency divider 28 as a counting timing. 23 is a counter that counts the output frequency; 25 is an error detector; 26 is a microcomputer;
This controls the variable frequency divider of the I-circuit 21B.

Note that 27 indicates a memory read out by the microcomputer, and this memory 27 is configured so that output frequency fluctuation data of the synthesizer signal source can be stored in time series.

FIG. 2 is a block diagram showing a specific example of the PLL circuit 21B, in which 31 is a first fixed frequency divider, 32 is a phase comparator, and 33 is a first fixed frequency divider.
34 is a loop filter, 35 is a voltage variable oscillator (VCO), and 35 is a variable frequency divider whose frequency division ratio is made variable by a control signal supplied from the outside.

The configuration of this PLL circuit can be used as a frequency multiplier by setting the division ratios of the fixed frequency divider 31 and the variable frequency divider 36, and can be adopted as the multiplier 22 in FIG. It is something.

Next, the operation of the finely correctable reference signal source shown in FIG. 1 will be explained using numerical examples.

The oscillation frequency of the crystal oscillator 21A is set to IOMH, and the second
As shown in the figure, the frequency division ratio of the fixed frequency divider 31 of the PLL circuit 21B is 2000, and the frequency division ratio of the variable frequency divider 36 is 2000.
When set to 00,000, the oscillation frequency of the VCO 35 is set to approximately IGHz.

And this oscillation frequency f. is the frequency divider 2IC, 1/2
When the frequency is divided by 5000, a signal of approximately 400KH2 is output, and when this 400KH2 signal and the output frequency of the crystal oscillator are added by the mixer 2LD, a lo, 4MH2 signal is output.

This signal is frequency-multiplied by, for example, 1500 times via a multiplier 22, and is then adjusted to 1530 MHz, which is the reception frequency shown in FIG.
When mixed with the reference frequency S , , transmitted from the satellite, the difference frequency (1500
XlO,2) Mn2-1530MH,=O, and the count value of the counter 24 becomes O.

Therefore, in this case, the crystal oscillator 21A is controlled to a predetermined oscillation frequency in synchronization with the external reference signal Srr.

By the way, since the oscillation frequency accuracy of the normal crystal oscillator (TCXO) 21A is about ±1 ppm (10-6), when the fine correction circuit is not added, the TCXO
The oscillation frequency fluctuates by a maximum of 1 OHZ.

However, since the finely correctable synthesizer signal source of the present invention is configured so that the fluctuation of 10H2 is detected by the counter 24, it can be corrected by the error data input from the error detector 25 to the microcomputer. .

That is, the PLL circuit 21B of the synthesizer signal source
When the frequency division ratio of the variable frequency divider 36 built in is increased or decreased by 1, the output frequency of the synthesizer signal source 21 becomes l(1
The signal source changes in steps of 4MH2±0.25H2 and can be made into an extremely small and finely correctable signal source.

In order to use the embodiment of FIG. 1 as the reference signal generator 20 of FIG. 3, the oscillation frequency of the crystal oscillator 21A and the division ratio of each frequency divider must be slightly different from the values explained above. However, according to the method of the present invention, fine correction can be made in steps of about 0.25 Hz, making it possible to reliably receive narrowband channels.

It is preferable to set the output frequency of the multiplier 23 to be near the second intermediate frequency.

Further, in the satellite communication system, the reference signal S fr supplied from the outside may be based on the radio wave transmitted from the satellite station, which is received immediately before transmission from the mobile station.

[Effects of the Invention] As explained above, in the finely adjustable synthesizer signal source of the present invention, the output frequency of the finely adjustable synthesizer signal source is controlled by a reference signal supplied from the outside. This makes it possible to obtain an extremely accurate output signal even if an inexpensive crystal oscillator is used as a reference signal source.In particular, it is possible to stabilize the signal source of a transmitter/receiver using satellite communication and reduce costs. It has the advantage of being possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a finely correctable synthesizer signal source of the present invention, and FIG. 2 is a block diagram showing an example of a PLL circuit forming the synthesizer signal source of the present invention.
FIG. 3 is a block diagram showing an example of a satellite communication device in which the synthesizer signal source of the present invention can be used. In the figure, 21 is a synthesizer signal source, 21A is a crystal oscillator, 21B is a PLL circuit, 2IC is a frequency divider, 22 is a multiplier, 23 is a multiplier, and 24 is a counter. An example of the SR 8-5 aircraft (Fig. 1)

Claims (4)

[Claims] (1) A synthesizer signal source capable of fine correction, a multiplier for mixing the synthesizer signal source with an external reference signal supplied from the outside, and an output of the multiplier forming the synthesizer signal source capable of fine correction. It is characterized by comprising a counting means for counting based on the output of a reference oscillator, and a control means for controlling a variable frequency divider forming the synthesizer signal source so that the count value of the counting means becomes a specified value. Reference signal generator that allows fine correction. (2) The finely correctable reference signal generator according to claim (1), wherein the output of the synthesizer signal source supplied to the multiplier is multiplied by a predetermined multiple. (3) The synthesizer signal source includes a first fixed frequency divider that frequency divides the output of the reference oscillator, a voltage controlled oscillator, and a second variable frequency divider that frequency divides the output of the voltage controlled oscillator; 1
comparing the outputs of the fixed frequency divider and the second variable frequency divider;
The PLL circuit includes a phase comparator that controls the voltage controlled oscillator based on the phase difference.
The microcomputer according to claim 1 is configured to output a signal obtained by frequency-dividing the output of the L circuit and a signal corresponding to the reference signal source. Compensable reference signal generator. (4) The output of the counting means is stored in a memory means in time series, and the variable frequency divider of the synthesizer signal source is controlled by the data read from the memory means. A finely correctable reference signal generator according to claim (1).