JPH0453130B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radio selective calling receiver known under the name "pager". More particularly, it relates to a radio selective calling receiver including display means for displaying messages and the like.

A wireless selective call receiver is a reception-only radio device carried by a user that receives and identifies a radio signal transmitted from a base station, and the radio signal includes a selective call signal (PID) of its own station. This device notifies the user that a call has been made by emitting a ringing sound.

[Conventional technology]

In recent years, wireless selective calling receivers have become more compact and multi-functional.In particular, in terms of multi-functionality, services that add message information to selective calling signals are being considered, instead of the conventional notification ringing service that uses only selective calling signals. It is being In this service for adding message information, after receiving a selective call signal and a message information signal, a notification sound is sent out to notify that the signal has been received, and at the same time, the display device is driven to display the contents of the message information. .

In conventional call-only services, subscribers pay a monthly usage fee to the service company, and if the subscriber does not pay the usage fee, the base station takes action by deleting the subscriber number from the subscriber registration. was.

[Problem that the invention seeks to solve]

However, in recent years, with services that add message information, the same message information may be used by multiple subscribers, so if one subscriber does not pay the usage fee, the base station It is not possible to stop all corresponding message information services on the side. Therefore, it is necessary to develop some kind of measure that can deal with only specific subscribers who attempt to receive illegal services without paying usage fees.

The present invention solves this problem, and aims to provide a device that can individually stop the operation of subscribers who do not pay usage fees.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems, and to provide a device that integrates a read-only memory (P-ROM) for information reception with an address read-only memory (P-ROM) and a timer, and updates billing each time the timer ends. It is in.

[Means for solving problems]

The present invention is configured such that each subscriber device has a built-in timer that measures a certain period of time after payment of a usage fee, and when the timer ends, the device stops functioning.

That is, a number setting means in which the selective calling number of the self is set in a storage circuit, a means for identifying the selective calling number set in the means from the received signal, and a device demodulated from the received signal in accordance with the identification output of this means. In the wireless selective calling receiver with display, the number setting means has a built-in timer, and after the time set in the timer has elapsed, the number setting means The present invention is characterized by comprising means for inhibiting read operations from the memory circuit.

It is desirable that the timer settings be programmable.

[Effect]

According to the present invention, a message signal subsequent to the self-selective call signal is received and a call alarm is activated, and a call display is performed by displaying the message signal, and the call display function using the display device In a multi-functional display radio selective calling receiver having additional functions other than
After using the radio selective call receiver with display for a certain period of time, the number setting unit (P-ROM) loses its function. As a result, the reception function of the radio selective calling receiver is stopped. The wireless selective calling receiver with display has a built-in timer in the number setting section, and until the timer times out, the wireless selective calling receiver with display performs a normal receiving function. Therefore, the subscriber enters the timer built-in number from the service company into the timer built-in number setting section by writing an individual selective calling number and a number corresponding to the message information service required by each individual (hereinafter abbreviated as message calling number). By purchasing the number setting unit separately and incorporating it into a radio selective calling receiver with display, the call display service can be received until the timer times out. However, when the timer times out, the subscriber cannot receive the call display service, and if the subscriber wants to continue the call display service again, the subscriber must reconfigure or purchase the timer built-in number setting unit from a new service company. By adopting this service system, it is possible to deal with the problem of certain subscribers not paying usage fees.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of a received signal configuration for explaining the operation.

The radio signal received by antenna 1 in Fig. 1 is
The radio section 2 amplifies and demodulates the signal. The signal demodulated by the waveform shaping circuit 3 is converted into a digital signal and supplied to the decoder 4. The decoder 4 detects the frame synchronization signal F, and in order to receive the subsequent calling signal, the decoder 4 detects the frame synchronization signal F, and in order to receive the subsequently sent calling signal, the decoder 4 uses a P-ROM in which its own calling number is written in advance.
5 and the digital signal from the waveform shaping circuit 3, and if a match is confirmed, a detection signal is sent to the message processing section 6 to prepare for subsequent message data processing. Then, the message processing section 6
waits for the end of the message signal, notifies the decoder 4 of this fact, and drives the speaker 8 via the amplification section 7 to generate a sound. Furthermore, the message processing section 6 drives the liquid crystal display section 9 to display message information on the liquid crystal display section 9. A reset switch 10 is also provided, and by manually operating it, change information and status signals are sent to the message processing unit 6 via the decoder 4.
Stops the sound, stops and starts the LCD display, etc. A crystal oscillator 11 is a clock generating oscillator that operates the decoder 4.

To explain the signal frame in Fig. 2, Fig. 2 a
The symbol F is a frame synchronization signal, N is a selective call signal, and 1 is a message signal. Figure b and c show BCH31 and 21 for selective call signal and message signal.
Using a signal with parity bit EP added to the code,
Selective call signals (logic ``0'') and message signals (logic ``1'') are distinguished from each other by the value of the identification bit A plurality of signals can be arranged as required depending on the length of the message.

FIG. 3 is a block diagram of the decoder 4. The waveform shaping circuit 3 sends the signal that can be read by the decoder 4 to the signal detection circuit 21 and the matching circuit 22. The signal detection circuit 21 performs frame synchronization, and in response to the detection of the synchronization signal, P-
The ROM read/decode circuit 23 sends a read pulse to the P-ROM 5, reads out the selective call number previously written in the P-ROM 5, and compares it bit by bit with the received signal in the matching circuit 22.

FIG. 4 is a block diagram of the P-ROM 5. The signal C1 from the timer 30 uses logic 1 or D to distinguish between timer operation (logic "1") and timer out (logic "0"), and the read pulses A1~ from the P-ROM read decoding circuit 23.
A8 and the signal C1 from the timer 31 are sent to the memory via the AND gate circuit 32. Since the signal C1 from the timer 30 is at the logic "1" level during the timer operation, the A1 to A8 signals and X1 to
The X8 signal becomes the same signal. However, in the timeout state, the signal C1 becomes a logic "0" level, and therefore the X1 to X8 signals become a "0" level and are inhibited. Therefore, even if the P-ROM read/decode circuit 23 sends a read pulse to the P-ROM 5, the selective call number pre-written in the memory 33 cannot be read out.

FIG. 5 shows a specific example of the timer 30.
The astable multivibrator circuit 40 is a basic circuit that utilizes the 180° phase difference between the input and output of inverters 47 and 48 and the time constant of CR. For pulse synchronization, resistor (R) 43, capacitor (C) 44
In the case of , there is a relationship of approximately T=2.2RC, and if it is desired to increase the input pulse period from Z1, the values of R and C can be increased. (Here, the resistance (RS) 42 is
RS≧10R), the counter circuit 41 is the inverter 4
Consists of 6,49 flip-flops, Q ₁ ~ _{Q o}
The period until timeout can be set by connecting the terminal. That is, if it is desired to lengthen the period of timer operation, the number of flip-flop stages may be increased or the period of the unstable multivibrator may be increased. Here, the crystal oscillation circuit with high frequency stability of the oscillator is connected to the unstable multivibrator circuit 4.
It is obvious that it can be replaced with 0, and a crystal oscillation circuit can be easily realized using conventional technology.

FIG. 6 is a block diagram of the message processing section 6. As shown in FIG. Reference numeral 50 is a control circuit composed of a one-chip CPU, 51 is a liquid crystal driver, and 52 is a random access memory (RAM). Further, detailed block diagrams of the control circuit 50, the liquid crystal driver 51, and the random access memory 52 are shown in FIG. 7, FIG. 8, and FIG. 9, respectively.

In FIG. 7, symbols 60 to 62 are input ports;
63 is an interrupt port, 64 is a serial interface, 65 to 71 are output ports,
80 is a data bus, 90 is a program counter that specifies the contents of an address, 100 is a program memory that reads the contents of the address specified by the counter 90, and 110 is used to perform various operations such as arithmetic operations and logical operations. Arithmetic circuit, code 120
is an instruction decoder that decodes information from the program memory 100 and supplies control signals corresponding to the instructions to each section. Reference numeral 130 denotes a random access memory 140, which is used for transmitting and receiving data between each port 60 to 71.
ACC, reference numeral 140, is a random access memory used for storing various data, program counting in subroutine interrupts, and saving program status, and reference numeral 150 is a system clock generation circuit that determines the execution instruction cycle time.

FIG. 8 shows the configuration of the liquid crystal driver. In FIG. 8, reference numeral 210 is a column driver that controls the columns of the liquid crystal, 220 is a row driver that controls the rows of the liquid crystal display, 230 is a voltage control controller that controls the voltage supplied to the liquid crystal display, and 240 is a voltage control controller that controls the voltage supplied to the liquid crystal display. This is a controller that controls the drive timing of the liquid crystal display section. Reference numeral 250 is character generation circuit 2
90 output or serial interface 29
260 is a system clock controller, and 270 is a serial interface 295 that reads and decodes input commands and controls each part according to the contents of the commands. The command decoder 280 is the serial interface 29
This is a data pointer that specifies an address for writing data from the serial interface 295 or reading data from the serial interface 295. Reference numeral 290 represents a character generation circuit that generates a 7×5 dot matrix pattern in response to input data, and reference numeral 295 represents a serial interface that serially transfers data to and from the control circuit 50.

FIG. 9 shows the configuration of the random access memory. In this figure, the reference numeral 310 is a serial interface that serially transfers data to and from the control circuit 50, the reference numeral 320 is an address counter, and the reference numeral 330 specifies the address of a memory cell 340 by analyzing the data of the address counter 320. An X-Y decoder is used to write or read data in the memory, 340 is a memory array, and 350 is a control circuit.

FIG. 10 is a configuration diagram of the signal detection circuit 21.
When a desired pattern is input to the signal detection circuit 21, the output of the AND gate 540 becomes a logic "1".
level is obtained. As a result, data from the P-ROM 5 and the 11th
While making a comparison using the circuit shown in the figure, the 11th
In the circuit shown in the figure, the R terminal is cleared every 30 bits, but if a signal detection is output due to 29 or more matches before it is cleared, one chip is sent via the interrupt port 63 as shown in FIG. When the CPU 50 is activated, a clock corresponding to the transmission speed is supplied from the input port 61. The signal D read in through the input port 62 in synchronization with the clock is written into the random access memory 140 through the data bus 80 and ACC 130. Then, each time 31 bits are input, an arithmetic operation is performed in the arithmetic circuit 110 to decode the received signal.

As a result, each BCH code 31 correctly decoded,
Since the information bits out of 21 are stored in the external random access memory 52 as message information, the external random access memory 52 is set to the operation mode by setting the signal () to logic "0" level, and the address to be written is determined. The corresponding address information is transferred via the serial interface 64 as a signal (S). At this time, the system clock is sent as a signal (), and at the same time, the signal (A/) is set to logic "1" level to indicate an address. And at this time, the 9th
In the figure, the random access memory 52 determines that the signal input to the terminal "SI" is an address signal according to each input control signal (, A/, R/), and the address counter 320, X-Y decoder 330 The address of the memory cell 340 to be written to is specified via the .

Next, the control circuit 50 sends out the message data to be written using the signal (SO) of the serial interface 64, and also sends out a code (A/
D) is set to logic "0" level, and the signal (R/) is set to logic "0" level to indicate writing.

As a result, the random access memory 52 uses the data input through the terminal "SI" in response to the input control signal as message data to send it to the memory cell 33 designated earlier via the X-Y decoder 330.
Write to 0. In the above process, the message signals are sequentially decoded, but if a predetermined pattern indicating the end of the message signal is decoded, or if two consecutive words of the message signal cannot be received, the signal at the output port 65 (ME ) to inform the decoder 4 that the message has ended. At this time, decoder 4 stops supplying the clock to control circuit 50. Also, at the same time as stopping the decoding process, a signal (AC) is sent via the output port 66.
controls the sound generation circuit 24 of the decoder 4, and causes the speaker 8 to sound using the amplifier (buffer amplifier) 7. By the way, at the same time as the reception of the message signal is completed, the decoded message data is displayed in the next process.

That is, the first address information of the corresponding message data is supplied to the external random access memory 52 from the terminal "SO" in FIG.
D” to logic “1” level, then terminal “A/
D" is set to the logic "0" level, and the corresponding data is sequentially written in 1-byte units from the above-mentioned first address.
Memory cell 340 via Y decoder 330
The data is read from the terminal SO and supplied to the control circuit 50 via the serial interface 310. In this way, external random access memory 5
In FIG. 7, the data read from the terminal 2 is set to the terminal ``SO'' with the terminal ``'' at the logic ``1'' level, the terminal ``CS'' at the logic ``0'' level, and the terminal ``C/'' at the logic ``0'' level. The signal is then supplied to the LCD driver 51 shown in FIG. As a result, the information converted from serial to parallel by the serial interface circuit 295 is decoded by the command decoder 270 when the terminal "C/" is at the logic "1" level, and an internal control signal is generated.

Here, if the command is a write command, the data pointer 280 is accessed to set the write address, and when the terminal "C/" becomes a logic "0" level, the data input via the serial interface 295 is accessed to the character. The generation circuit 290 converts it into a 7×5 dot matrix pattern, writes it to the decoder memory 250, and displays it on the liquid crystal display section 9 via the row driver 220 using the outputs of the column driver 210 and liquid crystal display timing controller 240. .

The operation of the receiver will be explained with reference to the time chart in FIG. Now, assume that this receiver is always powered on, as shown in FIG. 12b, and receives a signal as shown in FIG. 3a. When the frame synchronization signal F in the signal from the waveform shaping circuit 3 (FIG. 1) is supplied to the signal detection circuit 21 configured as shown in FIG. 540 outputs the signal shown in FIG. 12c, and P
- Send to ROM reading circuit 23. The P-ROM read circuit 23 sends out read pulses shown in FIGS. 12D to 12K.

Here, Fig. 12D is the #12 terminal of Fig. 13A, No. 12E is the #13 terminal, Fig. 12F is the #14 terminal, and Fig. 13G is the #15 terminal.
Terminal, H16 terminal, #17 terminal for I, #18 for J
Terminals and K are synchronous pulses supplied to each terminal of #19 terminal. Figure 13A shows the correspondence between the terminal numbers of the integrated circuit and the positions of each memory bit.
Shown below.

Here, if the own selective call number (binary number) and check bit are written in A1 to A23 in FIG. 13A, the P-ROM
The first signal is sent from the readout circuit 23 to #12 of the P-ROM5.
When the read pulse shown in FIG. 2D is input, the waveform shown in FIG.
9, data of A17 is output to #5, and data of A25 is output to #6. Similarly, when the read pulses D to K in FIG. 12 are sequentially input to the input terminals #12 to #19, at D in FIG. 12, at B in FIG. 13,
The waveforms at each point in time at E, F, G, H, I, J, and K are output from output terminals #3 to
Since it is output to #6, for example, if we focus on the output terminal #3, data from A1 to A8 will be output in order. The data output from output terminals #3 to #6 is sent to the P-ROM decoding circuit 23. An example of the P-ROM decoding circuit 23 is shown in FIG. This P-ROM decoding circuit is a matching circuit 22.
This circuit reads out the output data from the P-ROM 5 bit by bit so that the received information from the waveform shaping circuit and the output data from the P-ROM 5 can be compared bit by bit. In FIG. 14, the outputs L, M, N, and O of the control timer 706 are indicated by time charts (L) to (0) in FIG. 12.

An example of the matching circuit 22 is shown in FIG. This circuit uses a counter 600 to count the output of EXNOR, which is compared in units of 1 bit. As a result, the counter 600 counts a number corresponding to the number of erroneous bits, so it is checked whether the counted value is less than the desired value in units of 23 bits of the code length of the selective call code, and in this example, errors up to 2 bits are detected. If the count value is 2 or less, it is assumed that the own device has been called and a detection signal is sent to the message processing unit 6.

As explained above, when the timer 30 in the P-ROM 5 times out, the receiving function of the receiver becomes disabled, so it is necessary to reset the timer 30 in order to restart the receiver. Fifth
The signal line _c2 of the timer 30 in the figure is this reset signal line, and the signal line of the P-ROM 5 shown in FIG.
A terminal is arranged as _C2 on the surface of the package of P-ROM5. This terminal should not be easily discovered by the general user (e.g., placed under a nameplate made of insulating material), and the timer 30 should be initialized at the service center when restarted or when the user borrows the terminal. Set.

〔Effect of the invention〕

According to the present invention, it is possible to set the period of use of a receiver with high precision, and billing updates, which were previously impossible, can be realized, and the practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a wireless selective calling receiver according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of the structure of a received signal. FIG. 3 is a block diagram of the decoder 4. Fourth
The figure is a block configuration diagram of P-ROM5. FIG. 5 is a block diagram of the timer 30. FIG. 6 is a block diagram of the message processing section 6. FIG. 7 is a block diagram of the control circuit (1-chip CPU) 50. FIG. 8 is a block diagram of the liquid crystal display driver 51. 9th
The figure is a block diagram of random access memory 52.
FIG. 10 is a block diagram of the signal detection circuit 21.
FIG. 11 is a block diagram of the matching circuit 22. 1st
Figure 2 is an operation time chart. Figure 13A is P-
The figure which shows the content of ROM5, and B shows the output waveform of P-ROM5. Figure 14 shows P-ROM decoding circuit 2
3 block configuration diagram. 1...Antenna, 2...Radio section, 3...Waveform shaping circuit, 4...Decoder, 5...P-ROM, 6
...message processing unit, 7...amplifier, 8...speaker, 9...liquid crystal display section, 10...switch,
11...Crystal, 21...Signal detection circuit, 2
2... Match circuit, 23... P-ROM reading decoding circuit, 30... Timer, 31... Count timer circuit, 32... AND gate circuit, 33...
...Memory, 40...Unstable multivibrator circuit, 41...Binary counter, 42, 43...
...Resistor, 44...Capacitor, 45...Battery, 46, 47, 48...Not gate, 50...
...Control circuit (1 chip CPU), 51...Liquid crystal driver, 52...Random access memory, 60~
62...Input port, 63...Interrupt port,
64...Serial interface, 65-71...
...Output port, 80...Bus, 90...Program counter, 100...Program memory, 1
10... Arithmetic circuit, 120... Instruction decoder, 130... ACC, 140... Random access memory, 150... System clock generation circuit, 210... Column driver, 220
... Row driver, 230 ... Liquid crystal voltage control controller, 240 ... Liquid crystal timing controller, 250 ... Data memory, 260 ... System clock controller, 270 ... Command decoder, 280 ... Data pointer, 290 ...
...Character generation circuit, 295...Serial interface, 310...Serial interface, 320...Address counter, 330...X
-Y decoder, 340...Memory cell, 350
...Control circuit, 500...Shift register, 51
0 to 530... Inverter, 540... AND gate, 600... Counter, 610... Exclusive NOR circuit, 701 to 704... AND gate, 705... OR gate, 706... Control timer.

Claims (1)

[Scope of Claims] 1. A number setting means in which a self-selective call number is set in a storage circuit; a means for identifying the selective call number set in the means from a received signal; In a wireless selective calling receiver with a display, which is equipped with a means for optically displaying a message signal demodulated from a received signal, the number setting means has a built-in timer, and after the time set in the timer has elapsed. A radio selective call receiver with a display, characterized in that the number setting means includes means for inhibiting a reading operation from the storage circuit. 2. The radio selective call receiver with display according to claim 1, wherein the timer setting is programmable.