JPH0453092A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To test it in a short period of time whether a severe reference is satisfied or not by making changeable a resistance value between one of two power sources and a memory cell based on an external input signal. CONSTITUTION:In the case of normal use, a test signal T is made H. At such a time, a resistance component is formed by the ON resistance of a transistor TrT2 and since the ON resistance is at a certain level to be ignored, however, no adverse influence is generated in the operation of the memory cell in the case of normal use. On the other hand, when inspecting the forwarding of an SRAM, the test signal T is turned to be L and a simple function test is executed. The test is executed for inspecting whether a threshold voltage is made abnormal at one part of an internal TR or not, and the characteristic of the abnormal memory cell is further made adverse by the resistance component to be formed between the memory cell and a ground level in the case of normal use. Then, by suitably setting the ON resistance of the TrT1 large, the characteristic can be made adverse to the level not to present an FF function. Thus, the defect of the memory cell loosing the FF function can be detected by the simple function test.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a memory cell in which H and L levels are applied from first and second power sources, respectively, and H and L levels are stored by a predetermined writing means. The present invention relates to a semiconductor memory device having:

[Conventional technology]

FIG. 3 is an explanatory diagram showing the overall layout configuration of a conventional SRAM (static random access memory). As shown in the figure, each memory cell in a memory cell array region 1 in which memory cells (not shown) are arranged in a matrix is connected to a source line 2 via a contact (indicated by * in the figure). The source line 2 is usually formed of metal wiring, and is connected to a ground potential setting pad 3 from which a ground level potential (L level) can be changed.

FIG. 4A is a circuit diagram showing the structure of the SRAM memory cell shown in FIG. 3. As shown in the figure, a high resistance load type memory cell]0 is formed between the bit line pair BLI and BL2. Memory cell] 0 is NMO5) transistor Q
2. Q3. Q5. It consists of Q6 and resistors R1 and R2, and transistor Q3 and transistor Q6 are cross-connected. That is, the gate of transistor Q3 and the drain of transistor Q6 are connected, and the transistor Q
The drain of transistor Q3 and the gate of transistor Q6 are connected, and the source of transistor Q3 and the source of transistor Q6 are grounded via source line 2.

Further, the drain of the transistor Q3 is connected to the power supply V ee (H level) via the resistor R1, and is also connected to the bit line BL1 via the transistor Q2, and the drain of the transistor Q6 is connected to the power supply V ee (H level) via the resistor R2. V. 0 and is also connected to bit line BL2 via transistor Q5. transistor Q
The gates of bit lines BLI and BL2 are both connected to the word line WL. One ends of bit lines BLI and BL2 are connected to the power supply vCo through NMO5 transistors Q i and Q4, and the gates of transistors Q1 and Q2 are connected to the power supply vCo. It is connected to the. Bit line pair B L 1. .

During writing, a predetermined potential difference is set between BL2 by a writing means (not shown) based on write data.

In such a configuration, when the word line WL is at L level, both transistors Q2 and Q5 are turned off.
Since the influence of bit line pair BLI and BL2 is completely eliminated,
The memory cell 10 is connected to a flip-flop formed by cross-connecting an inverter made up of a transistor Q3 and a resistor R1, and an inverter made up of a transistor Q6 and a resistor R2.
The stored data (potentials of nodes N1., N2) latches the previous state and becomes extremely stable.

On the other hand, when word line WL is at H level, transistor Q
Since bit line pair BL1.2 and Q5 are both turned on, bit line pair BL1.
．． ．． The data stored in the memory cell 10 changes based on the change in the potential of BL2. At this time, memory cell 10 is connected to memory cell transistor Q1. ．． ．． An EE (enhancement-enhancement) type inverter (hereinafter abbreviated as inverter E1) consisting of a load connected in series with Q2 and a transistor Q3, and a transistor Q4. A flip-flop is formed by cross-connecting a load formed by the series connection of Q5 and an EE type inverter (hereinafter abbreviated as inverter I2) formed of a transistor Q6.

FIG. 4B is an equivalent circuit diagram of the inverter 11.

In the figure, Q12 equivalently represents the transistor Q1+02, IN is an input signal, and OUT is an output signal. Note that although the inverter and the inverter I2 have the same configuration, the input/output relationship is opposite to that of the inverter 11, so for the inverter I2, the input signal becomes OUT and the output signal becomes IN.

The MJC diagram is a graph showing the characteristics of the memory cell 10, that is, the input/output characteristics of the inverters 11 and 12.
is the input/output characteristic of the inverter 11, Ll is the inverter 12
The input/output characteristics of each are shown. The shaded area in FIG. 4C is called the eye of the memory cell, and its size indicates the stability of the memory cell 10. In other words, if the size of the memory cell is small, there is a high possibility that the data stored in memory cell 0 (the potentials of nodes N1 and N2) will be reversed by a slight vibration of the input signal IN (output signal 0UT), and the stability is low. If the size of the memory cell is large, even if the input signal IN (output signal 0UT) oscillates to some extent, the data stored in memory cell 0 (the potentials of nodes N1 and N2) will not be reversed, resulting in high stability.

FIG. 4D is a circuit diagram showing an undesirable memory cell configuration of an SRAM. As shown in the figure, memory cell 1
The source of transistor Q3 and the source of transistor Q6 at 0' are grounded via resistor R3. Note that the other configurations are the same as the example shown in FIG. 4A, so explanations will be omitted.

In such a configuration, when the word line WL is at L level, the stored data latches the previous state and becomes extremely stable, similar to the memory cell 10 shown in FIGS. 4A to 4C.

When word line WL is at H level, transistors Q2 and Q
Since bit line pair BL1.5 are both turned on, the bit line pair BL1. ．． The data stored in the memory cell 10' changes based on the change in the potential of BL2. At this time, the memory cell 10' includes an E-E type inverter (hereinafter abbreviated as inverter II') consisting of a load formed by a series connection of transistors Ql and Q2 and a transistor Q3, and transistors Q4. , Q5 are connected in series, and an EE type inverter (hereinafter abbreviated as inverter 12') consisting of a transistor Q6 is cross-connected to form a flip-flop.

FIG. 4E is an isotonic circuit diagram of inverter Ill'.

As shown in the figure, unlike the inverter 11, a resistor R3 is inserted between the transistor Q3 and the ground level, so the driving ability of the transistor Q3 is equivalently reduced, as shown in Fig. 4F. , the output signal OUT of the inverter 11' (the input signal IN of the inverter 12')
L level is not low enough, Ll', L2 in Figure 4F
Since the input/output characteristics shown by ' are obtained, the mesh of the memory cell becomes smaller and the stability of the memory cell 10' becomes worse.

For the above reasons, conventional SRAMs are configured to include as little resistance as possible between the memory cell and the ground level when connecting the memory cell and the ground level.

[Invention or problem to be solved]

Since an SRAM with such a configuration is desired to have highly accurate stability, even an SRAM that has a small defect in its memory cells and is defective only in a very specific function must be rejected during shipping inspection.

For example, memory cell 1 in the SRAM shown in FIG. 4A
], if some of the transistors constituting memory cell 0 have abnormal threshold voltages, bias will occur in memory cell 11 as shown in FIG. 2A, and the bit line ( When the potential of BLi, BL2) is lowered, the possibility that the data stored in the memory cell 0 will be reversed increases. The above noise occurs in rare cases, for example, when specific address signals change at the same time, or when a signal change in the chip select signal and a signal change in the address signal occur at a certain time interval. However, since it is difficult to predict in advance, it is not possible to intentionally generate noise.

Therefore, even if an SRAM is defective only in a very specific function, in order to reject it during shipping inspection, all memory cells must be tested under all possible conditions F, which takes time. There was a problem with it being too much.

This invention was made to solve the above-mentioned problems, and it is an object of the present invention to obtain a semiconductor memory device having an internal function capable of confirming whether or not it satisfies strict standards in a short period of time. With the goal.

[Means to solve the problem]

The semiconductor memory device according to the present invention has a memory cell to which H and L levels are applied from first and second power supplies, respectively, and in which the H and L levels are stored by a predetermined writing means, A switching means is provided between at least one of the first and second power supplies and the memory cell, and is capable of changing the resistance value between them by switching the on-resistance based on an external input signal. It is equipped with

[Effect]

The switching means in this invention is provided between at least one of the first and second power supplies and the memory cell, and the resistance value between them is changed by switching the on-resistance based on an external input signal. Since it can be changed, the resistance value can be set to a level that adversely affects the operation of the memory cell, if necessary.

〔Example〕

FIG. 1 is an explanatory diagram showing the overall layout configuration of an SRAM that is an embodiment of the present invention. As shown in the figure,
Each memory cell in a memory cell array region 1 in which memory cells (not shown) are arranged in a matrix is connected to a source line 2 via a contact (indicated by * in the figure). The source line 2 is usually formed of metal wiring, and is connected to the ground potential setting pad 3 via an NMOS transistor T1, and to the pad 3 via an NMOS transistor T2.

The transistor T1 has a small channel width and a relatively large on-resistance, and the transistor T2 has a sufficiently large channel width so that its on-resistance can be almost ignored. A test signal T and an inverted test signal T are applied to the gates of transistors T2 and T1, respectively. Test signal T is SRAM
Ch1. This is a signal given from outside the board. Note that the structure of the memory cell is equivalent to that shown in the conventional example of FIG. 4A.

In such a configuration, when the test signal T (inverted test signal T) is set to L (H), the transistor T1 is turned on and the transistor T2 is turned off. As a result, a resistance component due to the on-resistance of the transistor T1 is formed between the memory cell and the ground level, and substantially the fourth D
The configuration is the same as that of the memory cell 10' shown in the figure. On the other hand, when the test signal T (inverted test signal T) is set to H (L), the transistor T is turned off and the transistor T2 is turned on. As a result, between the memory cell and ground level,
A resistance component is formed due to the on-resistance of the transistor T2, but since this on-resistance is at a negligible level, the structure is substantially the same as that of the memory cell 10 shown in FIG. 4A.

Therefore, during normal use, the test signal T is set to H.

At this time, as mentioned above, a resistance component is formed due to the on-resistance of the transistor T2, but since this on-resistance is at a negligible level, it does not adversely affect the operation of the memory cell during normal use. Never.

On the other hand, when performing a shipping inspection of SR and AM, the test signal T is set to L and a simple function test is performed.

At this time, some of the internal transistors have abnormal threshold voltages, and during normal use with the test signal T set to H, the characteristics of the abnormal memory cell are as shown in Figure 2A. This is further exacerbated by the resistance component (on-resistance of transistor T1) formed between levels. If the on-resistance of the transistor T1 is set appropriately large, it can be deteriorated to a level where the flip-flop function cannot be performed, as shown in FIG. 2B. A simple function test can reliably detect defects in memory cells that have lost their flip-flop function.

On the other hand, the characteristics of a normal memory cell whose characteristics are shown in FIG. 4C during normal operation are also deteriorated by the resistance component formed between the memory cell and the ground level, but the transistor T
Unless the on-resistance value of 1 is set to an abnormally large value, the flip-flop function will not be lost;
Since the memory cells remain at the defective level where the eyes of the memory cell become smaller as shown in Figure F, it is impossible to detect defective memory cells at this level with a simple function test, and a normal memory cell is determined to be abnormal. There's nothing wrong with that.

In this way, the resistance value of the resistance component formed between the memory cell and the ground level is changed between normal use and shipping inspection.
By setting the resistance to almost zero during normal use and setting it to a predetermined resistance value during shipping inspection, the test signal T
Since the product can be rejected by a simple shipping inspection with the value set to L, the inspection time is significantly shortened compared to the conventional method.

In this embodiment, the memory cell is formed by an N-channel transistor, and the resistance value between the ground potential level and the memory cell is changed. However, if the memory cell is formed by a P-channel transistor, the power supply In some cases, it may be more effective to change the resistance value between the cc and the memory cell, so in some cases, switching means such as a transistor may be used to control the power supply. A configuration in which the resistance value between C and the memory cell is changed is also conceivable.

Note that in this embodiment, SRAM was taken as an example, but DRA
Even for other semiconductor memory devices such as M, H and L levels are applied from the first and second power supplies, respectively, and written by a predetermined writing means! (7), the characteristics of the memory cell are deteriorated by changing the resistance value between the memory cell and at least one of the first and second power supplies. This invention can be applied to all semiconductor memory devices.

〔Effect of the invention〕

As explained above, according to the present invention, based on the external input signal, the internal switching means
is provided between at least one of the power supplies and the memory cell, and the resistance value between them can be changed by not switching the on-resistance.
If necessary, the resistance value can be set to a level that may adversely affect the operation of the memory cell.

Therefore, even if a memory cell cannot normally be detected as defective, by applying an external input signal it is possible to deteriorate the memory cell to a level where it can be detected with a simple function test, so it is difficult to This has the effect of allowing tests to be conducted in a short time to determine whether or not the standards are met.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing the overall structure of an SRAM according to an embodiment of the present invention, FIG. 2A is a graph showing the characteristics of a defective memory cell during normal use, and FIG. 2B is a graph showing the characteristics of a defective memory cell during testing. 3 is an explanatory diagram showing the overall structure of a conventional SRAM, FIG. 4A is a circuit diagram showing the structure of a memory cell of a conventional SRAM, FIG. 4B is an equivalent circuit diagram showing a part of it, and FIG. The figures are a graph showing the characteristics of the memory cell shown in Fig. 4A, Fig. 4D is a circuit diagram showing the configuration of an undesirable memory cell in a conventional SRAM, Fig. 4E is an equivalent circuit diagram showing a part of it, and Fig. 4F The figure is a graph showing the characteristics of the memory cell shown in Figure 41). In the figure, 1 is a memory cell array region, 2 is a source line, 3 is a ground potential setting pad, and Ti and T2 are NMOS transistors. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A semiconductor memory device having a memory cell to which H and L levels are applied from first and second power supplies, respectively, and in which the H and L levels are stored by a predetermined writing means, A switching means is provided between at least one of the two power supplies and the memory cell, and is capable of changing the resistance value between them by switching the on-resistance based on an external input signal. A semiconductor memory device characterized by: