JPH0451315A - Data transfer system - Google Patents

Abstract

PURPOSE:To reduce the waiting for rotation to a half and to speed up the data transfer by saving data for showing a generation area and an exception factor, when the exception factor is generated in the course of data transfer, transferring the data of the remaining area, and thereafter, executing an exception processing. CONSTITUTION:In the case an error is generated as an exception factor in the course of this data transfer, a generation place storage processing 410 stores an address of an area to which the data transfer is executed at present, and data for showing the error cause or the kind in a storage part. Subsequently, by an area address decision processing 110, the decision is executed again. In the next defect area decision processing 112, in the case it is decided that a target area is a defective area, an alternate address storage processing 113 holds an address of an alternate area prepared in advance instead of the defective area. Next, in an exception processing end decision processing 411, whether an exception factor is generated in the course of area data transfer or not is decided by the generation place storage processing 410, and an exception processing 12 is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method in a file input/output device.

[Conventional technology]

Conventionally, in file input/output devices, exception handling has been performed sequentially. This exception processing is divided into processing for replacing a defective area with a replacement area and error recovery processing. Among these, the process of replacing defective areas with alternative areas is
It is described in the publication No. 6-162166.

FIGS. 2 and 3 below show the case of data transfer between a host and a magnetic disk device regarding conventional processing including replacement processing of a defective area to an alternative area.

This will be explained based on FIGS. 4 and 5. FIG. 2 is a block diagram of a conventional data transfer process 10 including a process of replacing a defective area with a replacement area. This configuration will be explained below. 10 is a data transfer process including a conventional replacement process of a defective area to a replacement area; 11 is an initial process of dividing the area to which data is transferred into groups of adjacent areas;
12 is a data transfer end determination process, and 13 is an alternative area process.

14 is a subroutine for performing address switching processing, and 15 is a subroutine for performing data transfer processing for continuous area groups.

Below, the configuration of area group data transfer processing 15 will be explained in the third section.
This will be explained using figures. FIG. 3 is a block diagram of the area group data transfer process 15, in which 110 is an area address comparison process to determine whether it is the target area, 111 is a rotation wait process to skip the area to be accessed, and 112 is the currently accessed area. J13 is a process for determining whether an area is a defective area; J13 is an alternative address storage process for storing the address of an area to be replaced with the defective area;
114 is data transfer processing between the data section of the currently accessed area and the host; 115 is processing for determining the end of data transfer for consecutive areas; and 116 is updating to the address of the next consecutive area from the currently accessed area. This is area address update processing.

Hereinafter, individual processes of the conventional data transfer process 10 will be explained with reference to FIG. Furthermore, the data structure of one area in a magnetic disk device that transfers data between hosts is divided into an ID section, which is an address indicating the location of the area, and a data section. The ID section is represented by a cylinder address, head address, and sector address. Here, among areas that are successively accessed from a certain area, a seek wait time occurs when data is transferred between areas with different cylinder addresses, and a head switching time occurs when data is transferred between areas with different heads.

Therefore, after starting the data transfer process 10, the areas to which data is transferred are divided into groups of adjacent areas in the initial process 11. Specifically, in the initial processing 11, tracks, which are a collection of sectors with the same cylinder address and the same head address, are grouped, and the area for data transfer is divided into track units.

Next, in a data transfer end determination process 12, it is determined whether the data transfer has ended.

Determine whether data transfer still remains. If the process does not end here, address switching processing 14 is performed. This address switching process 14 updates the cylinder address and head address of the l/rack to which data will be transferred next by seek or head switching.

Hereinafter, each process of the area data transfer process 15 will be explained with reference to FIG. In the data transfer process 15, first, in an area address determination process 110, it is determined whether the currently accessed area is the target area by comparing addresses.

Here, if this area is not the target area, the currently accessed area is skipped in rotation waiting processing 111 and rotation waiting is performed until the next adjacent area. When accessing the next area, area address determination processing 1
10, the determination is made again. Here, in area address determination processing 110, when the currently accessed area matches the address of the target area, defective area determination processing 112 is then performed. Defect area determination processing 112 determines whether the target area is a defective area or not.

Next, if this area is normal, area data transfer processing 114 is performed. This area data transfer process 1
14 performs data transfer between the data section in this area and the host. After the data transfer of the target area is completed, a process 115 for determining the end of data transfer of the area group to be continuously accessed is performed. If it does not end here, the next area address update process 116 updates the address to the next data transfer address in the adjacent area.

Next, the determination is made again by area address comparison processing 110. Since this area is adjacent, it matches the address of the target area without waiting for rotation. If the target area is determined to be a defective area in the next defective area determination process 112, then an alternative address storage process 113 is performed. Substitute address storage processing 113 holds the address of a substitute area prepared in advance in place of the defective area. Next, without performing area data transfer processing 114,
Area group data transfer end determination processing 115 is performed.

If the process ends here, the process returns to the data transfer end determination process 12 of the data transfer process 10 in FIG.

Referring again to FIG. 2, the data transfer end determination process 12 and subsequent steps will be explained. If the data transfer is completed here, then alternative area processing 13 is performed. The alternative area processing 13 is
In the alternative address storage process 113 in FIG. 3, data transfer is performed at the address of an alternative area prepared in advance in place of the defective area. When this alternative area processing 13 is completed, the data transfer 10 is completed.

If the alternative area exists on another track, address switching becomes necessary, and each time this process requires seek waiting time and head switching time. In this way, data transfer including replacement processing to a defective area replacement area is made faster by reducing the time required for address switching processing to this replacement area. In order to reduce the time required for address switching processing, data is transferred from the defective area after the remaining data from the normal area is transferred, and the number of address switching is optimized by not sequentially switching between the replacement area and the normal area. ing.

However, this data transfer method does not take into account recovery processing for errors such as a CRC error in the ID section, an ECC error in the data section, and a sync pattern mismatch.

FIG. 4 shows recovery processing when an error occurs during data transfer in the conventional data transfer method. The area data transfer process 114 in FIG. 4 is a subroutine in the area group data transfer process 15 in FIG.

Area data transfer processing 114 includes area data transfer 21
If an error occurs during execution of process 0, error determination processing is performed. For this reason, error recovery processing 211
It was necessary to process each error sequentially.

Hereinafter, an error recovery operation when an error occurs during data transfer in the conventional data transfer including replacement processing of a defective area to a replacement area will be explained with reference to FIGS. 5 and 6. First, FIG. 5 is a track format diagram for explaining the operation of the conventional data transfer method. 310
is the track currently being accessed, and the order of sector numbers O11, 2, 3, 4, 5, 6, etc. up to n is opposite to the rotation direction of the track, in ascending order. to access. Here, the operation will be described assuming that six sectors with sector numbers O to 5 are transferred and an error occurs in sector number 1 and sector number 4.

FIG. 6 is a flowchart of the data transfer operation of the data transfer process 10 in FIG. The following description will be made based on the flow of operations shown in FIG. First, data in the area of sector number O is transferred as a normal access. Next, if an error occurs while accessing sector number 1 or during data transfer, data transfer from the next sector is stopped. Here, in order to start the error recovery process for sector number 1, sector number 1 will be restored on the next track access.
Wait until the rotation is accessed. In this error recovery process, for example, when a read process is performed on a magnetic disk device, the magnetic head is finely adjusted, the data on the error occurrence area is read again, and the data is transferred. When writing is performed, data is written again in the area where the error occurred.

Sector number 1- is accessed and error recovery processing is performed, but if the error cannot be cleared, it is necessary to perform error recovery processing again. This error recovery process is executed until the error is resolved, and is performed once every - number of track accesses. Here, the number of error recovery processes for sector 1 is R1.
times. After the error is canceled in the first error recovery process R and data is transferred up to sector number 3, an error occurs in sector number 4. The error recovery process for sector number 4 is assumed to be R4 times. Processing is performed in the same order as for the error in sector number 1. Finally, data is transferred for sector number 5, and data transfer for sector numbers O to 5 is completed.

This data transfer means that R1+R4+1 tracks have been accessed, and RI + R4 rotation wait times, which is the same as the total number of error recovery processes for each error that occurred during data transfer and sector number 1 and sector number 4, are added. be done.

[Problem to be solved by the invention]

The above conventional technology does not take into consideration the case where an error occurs during multi-area transfer, and since error recovery is performed sequentially for each error, the problem is that it is necessary to wait for the number of error recovery times for all errors. was there.

An object of the present invention is to reduce rotational wait times when an exception occurs during data transfer of multiple areas.

[Means to solve problems]

In order to solve the above object, the present invention provides a file input/output device such as a magnetic disk device, when transferring data in multiple areas on a storage medium, when an exception factor occurs during data transfer, the occurrence area and the exception Data showing the factors,
Sequentially save and execute exception handling after transferring the remaining area data.

[Effect]

By having means for sequentially storing data indicating the type of exception cause or the state and occurrence location after the exception cause occurs, it becomes possible to start exception handling at any time.

By activating exception handling after data transfer in consecutive area groups is completed, data transfer in other adjacent areas is not affected.

Additionally, by sequentially performing exception handling for multiple exception causes, one track's worth of rotational waiting time was previously required for one error recovery process for one error; You can perform one error recovery process for each of multiple errors.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1, 2, 5, and 7. In the embodiment, the data transfer method of the present invention is used in a data transfer processing device between a host and a magnetic disk. FIG. 2 shows a conventional data transfer process 10 in a data transfer processing device between a host and a magnetic disk.

FIG. 1 shows the area data transfer process during the data transfer process lo in FIG.

Hereinafter, referring to FIG. 1, area data transfer processing 15 using the data transfer method of the present invention will be explained. 41
0 is an exception cause and occurrence location storage process, 411 is an exception processing end determination process, and 412 is an exception process.

In the data transfer process 15, first, in an area address determination process 110, whether or not the currently accessed area is the target area is determined by comparing addresses.

If this area is not the target area, the currently accessed area is skipped and the rotation wait is performed until the next adjacent area in a rotation waiting process 111.

Here, if this area is a normal area, then area data transfer 210 is performed. This area data transfer 21
0 transfers data between the data section in this area and the host. Next, data transfer error determination processing 212 is performed. Up to this point, the process is the same as conventional data transfer, but if an error occurs as an exception during this data transfer,
Exception cause and occurrence location storage processing 410 is performed.

Exception Cause and Occurrence Location Storage Processing 4 ], O stores in the storage unit the address of the area to which data is currently being transferred and data indicating the error cause or type. At this time, data that has been stored since the previous error occurred and that has not undergone exception processing is added while being protected. After storing the data, the process proceeds to area group data transfer end determination processing 115. Further, in the area data transfer 210, if there is no error after the data transfer of the target area is completed, a process 115 for determining the end of data transfer of the area group to be continuously accessed is performed.

If it does not end here, the next area address update process 1
16, the next address for data transfer is updated in the adjacent area.

Next, the area address determination process 110 is performed to determine the address again. Since this area is adjacent, it matches the address of the target area without waiting for rotation. If the target area is determined to be a defective area in the next defective area determination process 112, then an alternative address storage process 113 is performed.

Substitute address storage processing 113 holds the address of a substitute area prepared in advance in place of the defective area. Next, area group data transfer end determination processing 115 is performed without performing area data transfer processing 114. If the end is reached here, next, in exception processing end determination processing 411, whether or not an exception factor occurred during area data transfer is stored in the storage unit stored in exception cause and occurrence location storage processing 410. Determine whether there is or not.

If there is an exception factor here, exception handling 412 is performed.

Exception processing 412 reads the exception cause and occurrence location from the storage unit and executes exception processing such as error recovery processing.

When the exception handling is completed, the cause and location of the exception for which the exception handling has been completed are cleared from the storage section.

Next, in the processing end determination process 411 again, it is determined whether or not an exception factor has occurred during area data transfer by checking the exception cause and whether or not there is an exception cause in the storage section stored in the occurrence location storage process 410. judge. If there is no exceptional cause here, the area group data transfer process 15 is ended.

After the area group data transfer process 15 is completed, the process returns to the data transfer end determination 12 of the data transfer process 10 in FIG.

The operation of the embodiment when an error occurs will be described in detail below with reference to FIGS. 5 and 7. As in the conventional example, in Fig. 5,
The operation will be described assuming that six sectors from sector numbers O to 5 are transferred and that an error occurs in sector numbers 1 and 4.

First, data in the area of sector number O is transferred as a normal access. Next, even if an error occurs while accessing [sector number] or during data transfer, data transfer from the next sector is not stopped. After data is transferred up to sector number 3, an error occurs in sector number 4.

Similar to sector number 1, data transfer from the next sector is not stopped even if an error occurs. Next, the data of sector number 5 is transferred and the normal access is completed.

Finally, the error recovery process for sector number 1 is started, but in order to access sector number 1, a rotation wait is performed.

Further, after accessing sector number 1 and performing error recovery processing, and polling from sector number 2 to sector number 3, error recovery processing for sector number 4 is started.

After completing the error recovery process for sector number 4, if the errors in sector number 1 and sector number 4 have not been cleared, the error recovery process for sector number 1 and sector number 4 is performed again. Here, the error in sector 1 is cleared by R1 error recovery processes. Furthermore, the error in sector 4 is cleared by R4 error recovery processes.

When this error recovery relationship is R1<R4,
First, in the first error recovery process R, the error in sector number 1 is cleared and data is transferred from sector number 1.

After polling from sector number 2 to sector number 3, error recovery processing for sector number 4 is started. After completing the error recovery process for sector number 4, if the error in sector number 4 has not been cleared, the error recovery process for sector number 4 is performed again.

As a result, the error in sector number 4 is cleared in the first time of error recovery processing R, data is transferred from sector number 4, and data transfer of sector numbers O to 5 is completed. In this data transfer, the waiting time for R4 rotations is increased, which is the same as the largest number of recovery times among errors that occurred during data transfer. In this embodiment, exception processing such as error recovery processing can be executed while waiting for the maximum number of track accesses during the exception processing.

A second embodiment of the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is a block diagram of the first embodiment in which part of the processing is implemented in hardware.

In the figure, 609 is a host interface bus 61
a host interface controller controlling 0, 6
11 is a file control device, 612 is a file control device 1
a cache memory 61 that caches data under the control of the address bus 13 and data bus 61-4 of No. 1 and also stores host interface transfer data 615;
6 is a CPU that controls the host interface controller 609 and the file control circuit 612 via the IO control bus 617; 618 is a file thread input/output device that controls the interface signal 619 and inputs and outputs data 620;
630 is an FCC that performs ECC error detection and FCC correction.
circuit, 631 is a CRC circuit that performs CRC error detection;
32 is a 5YNC circuit that detects a sync pattern, 633
63 is an interface signal control circuit that controls the interface signal 619 of the file input/output device 615;
4 is I that verifies the ID and outputs a match signal 635.
D-verify circuit, 636, data transfer control circuit, 63
7 is an interrupt signal that becomes active when data transfer ends;
638 is a status bus indicating an exception factor, 639 is a status register that stores signal 638, and 640 is an interrupt signal that becomes active when an exception factor occurs.

FIG. 9 is a program flow for controlling the file control circuit 611 from the CPU 616 regarding data transfer between the file input/output device 619 and the cache memory 612. 650 is the flow of the data transfer start processing routine
651 is the flow of exception factor interrupt processing routine 652
is the flow of the data transfer end interrupt processing routine.

The following will explain based on FIG. 9. The CPU 616 uses the data transfer start processing routine 650 to set the ID of the transfer start area, the number of transfer areas, and the cache memory data transfer position in the file control device 611, thereby setting the ID in the ID verify circuit 634.

Next, when the CPU 616 commands the file control circuit 611 to start transfer, the ID verify circuit 634 sends an interface signal 61 from the file input/output device 618 to the interface signal 61 controlled by the interface signal control circuit 633.
9, the comparison between the ID part of the data signal 620 to be read and the ID is started.

If the IDs match here, a match signal 635 is output to the data transfer control circuit 636.

In the data transfer control circuit 636, when the coincidence signal 635 is input manually, the data section of this area and the cache memory 61
Transfer data between the two. Further, after the data transfer of this area is completed, the number of transfer areas is decremented and the ID of the ID verify circuit 634 is updated. From this, the verify circuit 634 compares the IDs again, and if the IDs match, a match signal 635 is sent to the data transfer control circuit 63.
Output to 6.

Next, the data transfer control circuit 636 transfers data between the data portion of this area and the cache memory 612 when the match signal 635 is input. Also, after data transfer in this area is completed, the number of transfer areas is decremented and the ID
The ID of the verify circuit 634 is updated.

Also, a CRC circuit 6 that performs CRC calculation during data transfer.
32, when a CRC mismatch occurs in the ID section,
A flag is set on the status bus 638 and written to the status register 639. Similarly, when a flag mismatch occurs in the ID verify circuit 634 that verifies the ID section, a flag is set on the status bus 638 and written in the status register 639. Similarly, when a sync pattern mismatch occurs in the 5YNC circuit 632 that detects the sync pattern, a flag is set on the status bus 638 and written in the status register 639. Similarly, in the ECC circuit 630 that performs FCC calculation, F of the data section is
When a CC mismatch occurs, a flag is set on the status bus 638 and written to the status register 639. When such an exception factor occurs and a flag indicating the exception factor is written to the status register 639, the status register 639 activates the exception factor interrupt signal 640 that is output to the CPU 616.

When the exception cause interrupt signal 640 becomes active, the CP
U6], 6 interrupts the process currently being executed and starts execution of the exception factor interrupt processing routine 651. C
The PU 616 reads the data from the status register 639 and stores it in the storage unit. Then, the stored status register 639 is cleared.

Next, read the ID of the ID verify circuit 634,
Memorize the same. After storing the ID, the interrupt processing ends. Here, the file control device 611 executes the data transfer process described last time even if an exception factor occurs.

When the number of transfer areas becomes O, the data transfer control circuit 636
activates the data transfer end interrupt signal 637 output to the CPU 616. Data transfer end signal 637
When the CPU 616 becomes active, the CPU 616 interrupts the process currently being executed and starts executing the data transfer end interrupt processing routine 652. The CPU 616 reads the data from the register/private area in which the data of the status register 639 is stored, and sequentially reads and executes the exception handling routines 1 to n. After all data transfer routines have been executed, the interrupt processing ends. This completes the data transfer between the cache memory 612 and the file output device 618.

A third embodiment of the present invention will be described with reference to FIGS. 10 and 11. FIG. 10 is a flowchart 1 of this embodiment. 750 is an address generation circuit, and 751 is a status and ID transfer period signal.

The following will explain based on FIG. 9. The CPU 616 uses the data transfer start processing routine 650 to provide the file control device 611 with the ID of the transfer start area, the number of transfer areas,
By setting the cache memory data transfer position, the ID verification circuit 634
do.

Next, when the CPU 616 commands the file control circuit 611 to start transfer, the verify circuit 634 sends the interface signal 61 from the file input/output device 618 to the interface signal 61 controlled by the interface signal control circuit 633.
9, the comparison with the ID part of the data signal 620 to be read is started.

If the IDs match here, a match signal 635 is output to the data transfer control circuit 636.

In the data transfer control circuit 636, when the match signal 635 is input, the data section of this area and the cache memory 61
Transfer data between the two. Further, after the data transfer of this area is completed, the number of transfer areas is decremented and the ID of the ID verify circuit 634 is updated. The ID verify circuit 634 compares the IDs again, and if the IDs match, outputs a match signal 635 to the data transfer control circuit 636.

Next, in the data transfer control circuit 636, the match signal 635
When input, data is transferred between the data section of this area and the cache memory 612.

Further, after the data transfer of this area is completed, the number of transfer areas is decremented and the ID of the ID verify circuit 634 is updated.

Also, a CRC circuit 6 that performs CRC calculation during data transfer.
32, when a CRC mismatch occurs in the ID section, a flag is set on the status bus 638, and the status register 63 is
Write in 9. Similarly, when a flag mismatch occurs in the ID verify circuit 634 that verifies the ID section, a flag is set on the status bus 638 and written in the status register 639. Similarly, when a sync pattern mismatch occurs in the 5YNC circuit 632 that detects the sync pattern, a flag is set on the status bus 638 and written in the status register 639. Similarly, ECC
When an FCC mismatch occurs in the data section in the ECC circuit 630 that performs calculations, a flag is set on the status bus 638 and written in the status register 39.

The operation when an error occurs will be explained with reference to FIG. 76
0 is the data format of the area where the error occurred.

As a means of remembering the type of error and the location where it occurred,
When an exception factor occurs, the address generation circuit 711 reads and clears the status register 639 using the status register control signal 710. The address generation circuit 711 stores the exception cause and the ID of the ID verify circuit 634 at the time when the exception cause occurs in the cache memory.

Of these, FIG. 11 shows the operation when an ECC error occurs during data transfer. Data transfer control circuit 636
After transferring data in the data section in this area, ECC
If an error occurs in the section, the status and ID transfer period signal 712 is generated in the gap section up to the next area.
Activate.

During this period, data is stored in the cache memory by transferring the exception cause and the ID where the exception cause has occurred to the cache memory to the address 613 generated by the address generation circuit 711. Similarly, if a CRC error in the ID section, a flag error in the ID section, or a sync pattern mismatch in the data section occurs, it is stored.

At this time, the data transfer control circuit 636 does not stop, and when the number of transfer areas becomes O, the data transfer control circuit 636
Data transfer end interrupt signal 6 output to CPU 6], 6
Activate 37. When the data transfer end signal 637 becomes active, the CPU 616 interrupts the process currently being executed and starts executing the data transfer end interrupt processing routine 652. The CPU 616 reads data from the storage unit that stores the data of the status register 639, and sequentially reads and executes exception handling routines 1 to n. After all data transfer routines have been executed, the interrupt processing ends. This completes the data transfer between the cache memory 612 and the file thread input/output device 618.

According to this embodiment, the exception handling interrupt handling routine 651
Since the CPU 616 does not process an interrupt even if an exception occurs, the load on the CPU 616 is reduced. Furthermore, since the cache memory is used as a storage location for exception factors, the circuit scale of the file control circuit is reduced.

〔Effect of the invention〕

According to the present invention, when an exceptional factor occurs during data transfer of a plurality of areas, the rotation waiting time can be halved, resulting in the effect of speeding up data transfer.

[Brief explanation of drawings]

Fig. 1 is a flowchart of a transfer method according to an embodiment of the present invention, and Fig. 2 is a flowchart of a conventional transfer method.
FIG. 4 is a flowchart of conventional area data transfer, FIG. 4 is an explanatory diagram of the operation when an error occurs in FIG. 3, and FIG. 5 is a data transfer format diagram explaining the operation when an error occurs.
FIG. 6 is a flowchart 1 of the operation in FIG. 2, FIG. 7 is a flowchart 1 of the operation in FIG. 1, FIG. 8 is a block diagram of the second embodiment of the present invention, and FIG. FIG. 10 is a block diagram of the third embodiment of the present invention, and FIG. 11 is an explanatory diagram of the operation of the second embodiment of the present invention. ]5... Area group data transfer processing, 110...
・Area address comparison processing, 111...Rotation wait processing, 112...Defective area processing, 113...Alternative address storage processing, 115...Area group data transfer end determination processing, 116...Address update processing , 21
0...Area data transfer, 211...Error recovery processing, 212...Error determination processing, 410...Exception cause and occurrence location storage processing, 411...Exception processing end determination processing, 411... Exception handling, 609... Host interface controller, 611... File control circuit, 612... Cache memo 1 bar 616
...CPU, 618...File input/output circuit, 63
4... ID verify circuit, 635... Match signal,
636...Data transfer control circuit, 639...Status register. ＋ Figure collection Efu Masupu E F-RμL FIG.

Claims (1)

[Scope of Claims] 1. In a file input device, when data in multiple areas on a storage medium is transferred, data indicating an exception cause that occurred during data transfer and data indicating the position of occurrence of the exception cause are sequentially transferred. A data transfer method characterized by storing data in the remaining area and executing exception processing after transferring the data.