JPH0451097A - Frame buffer - Google Patents

Abstract

PURPOSE:To speed up mathematical arithmetic writing to an image memory by providing plural mathematical and logical arithmetic mechanisms and an input and output means for a carry in a frame buffer controller and propagating the carry between frame buffer controllers. CONSTITUTION:Multi-bit data read out of the image memory are inputted, bit by bit, to another mathematical and logical arithmetic mechanisms ALU101-1 to ALU101-n in a frame buffer controller (FBC) 100, and write data are also inputted, bit by bit, to the ALUs 101-1 to 101-n. The ALUs 101-1 to 101-n perform preset mathematical arithmetic by using those two data and a carry inputted from ALUs in another FBC and outputs the carry to ALUs in another FBC. When the propagation of the carry between the FBCs 100 is completed, the arithmetic result is written in the image memory 300, and consequently the mathematical arithmetic writing to the image memory 300 is performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame buffer in a graphic ink display system such as a graphic display.

[Conventional technology]

A frame buffer in a conventional graph ink display system will be described below with reference to the drawings.

In conventional frame buffers, the image memory is divided into planes in order to speed up multi-window processing, especially BitBLT (Bit Block Transfer), and a frame buffer controller (hereinafter referred to as FBC) is used for each plane. is under control. Third
The figure shows an example of a conventional frame buffer, in which the image memory is divided into 300-1 plane #1 to 300-m plane #m, each with 1001 to 10 planes.
0-m FBCs are connected and independently controlled. In this configuration, one pixel is defined in the depth direction of the plane, and has m-bit color and exploration information. Furthermore, data is transferred between the FBC and each plane in units of n bits. In the case of image copying in the aforementioned 13it BLT, since each plane can be operated independently and in parallel, a maximum of n pixels (nXm bits) can be transferred in one memory cycle, so high-speed operation is possible.

[Invention tries to solve it! In the illuminating CRT display technology, there is a problem of displaying straight staircases (also called jaggies) due to resolution constraints, which is avoided by line smoothing technology. The line smoothing technique is described in Japanese Patent Application No. 1-229851 filed earlier by the present applicant.

In the line smoothing technique, when writing to a frame buffer, arithmetic operations are required on a pixel-by-pixel basis between data that has already been written and data to be newly written.

The problems of the prior art will be illustrated below with reference to the drawings. In FIG. 3, each FBC from 100-1 to 100-m cannot operate data pixel by pixel. Therefore, in order to perform pixel-by-pixel arithmetic operations, the image data is read out from the image memory of 30 (1-1 to 300-m) through the FBC to the outside of the frame buffer, and then the ALU provided outside the frame buffer is read out. It is necessary to perform arithmetic operations with the data to be written and write the results back to the image memory via the FBC, which takes time.Furthermore, since the direction of data flow changes, the vibration line operation This method has the disadvantage of not being able to increase speed, and has the problem of not being able to provide high-speed display.

[Means to solve the problem]

In order to solve the above problem, the present invention includes a plurality of ALUs (arithmetic and logical units) in the FBC, a means for inputting carries to the ALtJ from an ALU in another FBC, and A frame buffer is configured that includes means for outputting carries to an ALU and allows carries to be propagated between frame buffer controllers.

[Effect]

Multiple bits of data read from the image memory are 1
Each bit is input into a separate ALU. Write data is also input to the ALU bit by bit.

The ALU uses these two data and the carry input from the ALU in the other FBC to perform a preset arithmetic operation and outputs the carry to the ALU in the other FBC. When the carry propagation between each FBC ends, the calculation result is written to the image memory. These series of operations are the read/write steps of the DRAM used for image memory.
This can be done in one memory cycle by using the modify write function.

〔Example〕

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows a graphic display system configured according to an embodiment of the present invention, 1a is a frame buffer of the embodiment of the present invention, and FIG.
It is a diagram showing internal blocks of BC.

In FIG. 1, 200 is a focus map controller (
BMC) develops the graphic information into pixels and provides the FBC with information to write into the image memory. Also,
The BMC provides a transfer source address and a transfer destination address during 3itBLT.

The image memory of 1b is divided into planes 300-1 to 300-m, with one 100-m plane in each plane.
1 to 100-m FBCs are provided.

When performing arithmetic addition on a pixel-by-pixel basis to the image memory, ■ In Figure 2, with the line smoothing technique described above, in which the data to be written is written to the 102 write data processor (WDP), this data is This is the volatility value that you want to add. The WDP writes the data of the corresponding bit from 101-1 to 101 in the next image memory write cycle depending on which focus position of the pixel the plane to which the FBC corresponds corresponds.
−n ALU.

■The word address on the image memory of the pixel to be written is sent to the memory controller (MC) 103 via the address bus 601, and the information about which bit position of the memory word is to be written is sent to the n-bit/7-bit data bus 602.
to each ALU.

(2) The MC generates an address for the image memory from the given address, reads n-bit data from the image memory, and supplies each bit separately to each ALU.

■ Each ALU calculates the data to be written to the image memory according to the arithmetic function using the three data given from ■ to ■ and the carry input from the ALU in the other FBC, and at the same time calculates the data to be written to the image memory using the digit error as a carry. F
Output to BC. The arithmetic function is defined as follows, and is set from the above-mentioned BMC.

D= 1MxFALU (d, s, c
) Ten! IMXRALU (d, s, c) here, at, D
is the data output from the ALU to the image memory, IM is the data given to the ALU as mask information, and IIM is the logical negation (N) of IM.

T), S is the data written in the image memory, C is the input carry, FALU and RALU are the data written in the image memory, and FALU and RALU are the data written in the image memory.
, s, c, and in addition writing in this embodiment, FALU (d, s, c)
-d+s+cRALU (d, s, c) =
s, but combinations of addition, subtraction, and logical operations are possible.

(2) Each plane performs the operations from (1) to (2) in parallel, the carry propagates through the FBC of each plane, and the data to be written to the image memory is determined after a propagation delay time.

(2) The MC waits for the data in (2) to be finalized and then writes the outputs of each ALU into the image memory.

■Additional writing to pixels can be realized by a series of operations. This write is performed once in one memory cycle.
A pipeline operation is possible because pixels are performed and this operation causes data to flow in a positional direction from the point of view of the BMC, which is the write source.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a frame buffer that allows arithmetic operations to be written to an image memory at high speed.

By configuring a graphic display system using the frame buffer of the present invention, it is possible to provide a high-speed, easy-to-view graphic display.

[Brief explanation of the drawing]

1 and 2 are diagrams for explaining the present invention in detail. FIG. 1 is a block diagram of a graphic display system using an embodiment, and FIG. 2 shows a part of the embodiment in detail. FIG. FIG. 3 is a diagram for explaining the prior art, and is a block diagram of a frame buffer of the prior art. 1a: Frame buffer of the embodiment of the present invention 1b: Image memory 100i-too-rns frame buffer controller (FBC") 200: Bitmap controller (BMC) 300-
Image memory 400 divided into 1 to 300-m planes: DA converter 500: CR7 display device 600: Frame buffer write bus 101-1 to 1
01-n: ALU 102 Write data processor (WDP) 103: Mesori controller (MC> 601 Near address bus 602: Data bus Too: ALU and above

Claims (1)

[Claims] A frame buffer used in a graphic display system, which has multiple planes and is controlled by one frame buffer controller attached to each plane in order to speed up parallel operation. A plurality of ALUs within the frame buffer controller.
(arithmetic and logic unit), means for inputting carries into that ALU from the ALU of other frame buffer controllers, and an ALU of other frame buffer controllers;
By providing a means for outputting carries to the LU and propagating carries between each frame buffer controller, each plane can operate independently and in parallel while processing data already existing in the image memory and data input from the outside. A frame buffer that performs arithmetic operations on a pixel-by-pixel basis between pixels and writes the results to image memory.