JPH04503432A - CCD dark current reduction method and device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] COD dark current reduction method and device Technical field The present invention provides a method and apparatus for reducing dark current in a CCD (charge coupled device). Regarding.

Background technology A true two-phase CCD is a device in which two physical gates are arranged for each pixel. Each gate has two transfer and storage regions formed in the silicon below it. have a person. In this device, there are two types of voltage phase lines Φ1 and Φ2. charge The theory of coupling applies to frame transmission and interline transmission CCD image sensing elements. It is applied. FIG. 1 shows an example of a frame transfer surface type image sensor 10.

Figure 1 shows a schematic cross-sectional view of a true two-phase CCD. No. 4,613,402 (Losee and Lavine) (the same patent). This true two-phase CCD has a casing below each phase gate. It has both a storage area and a transfer area. In Figure 1a, the phase gate is or a second polycrystalline silicon (POLY-5i) and transferred The areas and storage areas are areas (1) and (2) for Φ1 and for Φ2, respectively. Labeled by (3) and (4). Here, we will discuss the n-type channel element. will be considered. In this type of device, the majority carriers are holes and the minority carriers are holes. becomes an electron. In this invention, voltage is applied evenly to the p-buried channel element. will be done. In the illustrated n-channel CCD, the buried channel is connected into the p-type substrate. constructed by Ni mid-doping or by forming a p-well in an n-type substrate. Ru. The transfer/storage buried channel area is each an n-type or better n-buried channel area. Each is distinguished by channel doping. U.S. Patent No. 4,613,402 discloses a true two-phase CCD device.

static electricity through the phase gate electrode, the buried channel and the substrate of the image vixel. The potential bands are shown in FIG. The buried channel has a positive gate voltage with reverse bias. A pressure Vg is applied, thereby creating a depletion plane. In this state, Although omitted, the Fermi level (EP) is the center of the band gap at the oxide-silicon boundary. appears in In a buried channel CCD, dark current arises from three types of sources: 1) Impurities at the 5t-3t02 boundary with lattice destruction or depletion: (2) Generation of depletion regions due to impurities or mid-gap defects; and ( 3) Diffusion of minority carriers from the substrate into buried channels. In all three cases A spurious charge is generated in the buried channel, which is collected as a signal in the buried channel. surface The dark current generation mechanism in both the depletion region and the depletion region is shown in Figure 2. Follow a similar process. First, at the location (defect), electrons (negative charges) It is released into the conductive band in the channel, and holes (positive charges) are released into the valence band. this In both cases, the electrons are captured by the buried channel as a dark signal. and, If the spatial region where holes are released into the valence band becomes depleted of majority carriers, The holes move away from their point of origin, causing depletion of majority carriers in the region. Ru. Holes generated within the depletion region move to the substrate. The holes generated on the surface are Move laterally towards the channel stop region and refill the surface with majority carriers. put in a state of poverty. Therefore, the state of the generation region is the same as before the emission of electrons and holes, Defects in the surface and depletion regions continue to generate electron-hole pairs, which become dark current sources.

This generation process occurs only when excessive electrons or holes are generated at the defect location. Stop. Recent manufacturing technology has introduced surface condition generation methods in buried channel COD. A method has been adopted in which the bulk current is supplied to the extent that the dark current source exceeds the dark current source. It is being This reduces the depletion region and bulk current to the surface state generation mechanism. This makes it possible to reduce the drawback of the buried channel being the main dark current source in the CCD.

The present invention aims to reduce the surface state component of this dark current.

Disclosure of invention In order to achieve the above object, the present invention provides a distance between the peak and This is a method to reduce the dark current that occurs in the buried channel CCD where the cells are identified. Therefore, it is necessary to arrange all the electrodes simultaneously during the accumulation mode operation of such a CCD. It is characterized by including a step.

In the present invention, dark current is suppressed very effectively. This suppressing effect is due to the -C During the entire time required to actually transfer the charge from the CD to the next CCD, the storage This is obtained by holding all phase gates in product mode operation. accumulation To operate the mode, most carriers are connected to a silicon 5i02 interface. voltage must be applied so that it is attracted to the ground. Large for n-channel devices A portion of carriers are holes, and in p-channel devices, most carriers are electrons. be. Therefore, the appropriate voltage in storage mode is negative for p-type buried channel devices and positive for p-type buried channel devices. Two true topological structures ideally fits this mode of operation.

In the present invention, the channel potential below the barrier region and the storage region is be selected appropriately so as not to mix in nearby pixel signals when operating in must be

The present invention can be used in frame transfer CCD imagers during integration and readout operations. Can be used. Additionally, the transfer CCD imager is installed during readout of optically generated signals. It can also be applied for tarlining.

The advantage of the accumulation mode driving the frame transfer CCD is that the integration and readout rain periods It is possible to drastically reduce the dark current flowing into the interior and the dark fixed pattern noise that appears during integration. It is in. Reducing dark current directly increases dynamic range and dark signal shock. This means reducing noise.

Another advantage of the present invention is that it does not introduce motion loss within a frame transfer image sensor. However, it is possible to perform interlacing operations during both integration and readout. Ru. This produces a half-stage normal transfer action of − according to − within each field. This ensures pixel alignment and reduces the number of pixels during the subsequent accumulation period. This avoids confusion in the files.

Brief description of the drawing Figure 1 is a plan view of a true two-phase domain image sensor; Figure 1a is the second position in Figure 1. A diagram showing an image pixel by a-a vertical cross section of a phase CCD element; Figure 2 shows the electrostatic charge of the image vixel in Figure 1a, which shows the mechanism of dark current generation. Between positions; Figures 3ae and 3b show surface depletion mode and accumulation mode during operation. Between electrostatic bands similar to Figure 2; Figures 4a and 4b show the gate voltage versus charge for the gate of Figure 1a, respectively. A graph showing the relationship between channel potential and gate voltage versus dark current; The three gate electrodes of the phase CCD and the accumulation mode of these gate operations A diagram showing the potential wells under these gates as they change from the end of the transmission period; Figure 6 shows the gate voltage in the vertical cross section of regions (a), (c) and (d) in Figure 5. Maximum electrostatic potential (volts) for and gate voltage in region (d) in Figure 5 It is a diagram showing potential capacity electrons/μm2 with respect to.

mode of implementation of the invention For illustrative purposes, reference is made to the frame transfer CCD image sensor 10 shown in FIG. I will explain as I go along. In this device, charge transfer channels 12 run vertically. There is. Each channel is separated from each other by a channel stop 14.

Channel stop 14 confines the charge collected in the transfer channel and Prevent leaks to channels. Each transfer channel 12 includes a plurality of sensing elements or image pixel (or vertical shift register in interline transfer CCD) stage). Since this element is a two-phase element, each pixel Each cell is identified by a gate placed at a close distance. gate electrode is made of a transparent conductive material such as polysilicon. Each electrode of each sensing element When an electrode is formed under the electrode, a potential well or depletion region is formed below it. love Charge, which is a function of scene brightness, is collected in the potential well. Buried channel CC In D, each electrode is placed on an insulator such as S L 02. The insulator is heavily attached to the board. It is placed side by side. The substrate is doped to achieve the desired polarity, e.g. an n-type channel. For onm channel elements, which can be formed to have p-type, the basic The surface area near the insulator in the plate has an n-type polarity opposite to that of the bulk substrate. Also , a potential wire is created in the substrate at a distance from the insulator when a predetermined potential is applied to the electrode. The concentration is such that a pore is formed.

The image sensor 10 has voltage phase lines Φ1 and Φ2 and a buried channel. It is equipped with a frame transfer true two-phase CCD. Each pixel constitutes a two-dimensional array. This array is for illustrative purposes only, and is 740 columns by 485 rows. is shown as a composition of pixels. Each transparent electrode has a two-phase voltage Connected to one line or one phase of the lock signal source. Exposure to incident light takes place After the voltage signals on the phase lines are sequentially applied to the image sensing array in a well-known manner, is applied to. This results in the formation in the pixel, as shown as block H. The image-like electric pattern is moved toward the output register by 10− at a time. It goes down.

High frequency clock pulses drive the polysilicon gate electrode and Each row of the image sensor is read out at a rate determined by the controller. Output level The register H is schematically shown as a block. The reason is that the optional transfer game A conventional two-phase CCD placed between the gate 16 and the horizontal channel stop 18 This is because it is supplied by a shift register. Transfer gate 16 is a vertical register can be configured as one of the following phase clocks. These electrodes are conventionally It is driven by a signal on voltage line Φ1-Φ2.

The transfer gate electrode 16 is driven by the first transfer signal T1 and outputs the low photocharge. Transfer it to Jister H.

After the photocharge low is transferred to output register H, transfer gate 30 is closed.

Due to this closure, a potential barrier is formed below this transfer electrode. At this time, the output level The resistor is driven in a two-phase fashion, so that the photocharge is transferred to the output diode 32 one vixen at a time. clocked by the clock. Output diode 32 converts the photocharge into voltage.

Before proceeding further with the explanation, the mechanism of action in the accumulation mode will be described below.

The dark current caused by the surface generation position can be reduced by applying a voltage to the gate electrode to generate a large amount below the electrode. By accumulating partial carriers, it can be dramatically reduced. This is an accumulation of effects. It's called a mode. Terms such as accumulation, depletion, and inversion refer to metal-oxide semiconductor (MOS) ’) Accepted technical terms in device physics, each with a large number of carriers. This means the presence of carriers, the absence of carriers, and the presence of minority carriers, respectively. this The mechanism that produces this effect will be explained. Holes or majority carriers are 5 Further dark current generation is caused by accumulation in the i-8IO2 interface. suppressed. This effect is caused by an electric current in the opposite direction rather than a hole emission from a defective site. A reaction that generates a hole pair, that is, a hole-electron hole pair (explained earlier) captured by a defect site. This can be explained by what happens. 5i-8i02 below any CCD phase gate The accumulation state of holes in the interface is determined by the voltage Vg applied to the gate. control. As is well known in the physics of MO3 elements, the hole density in the valence band is , is determined by separating the Fermi level EF from the valence band Ev. Ho The separation is approximately 174 below the bandgap, i.e. between Ev and Ec. It increases dramatically when separated. This separation is controlled by the gate voltage . In Figure 3a, this separation is essentially the entire bandgap, which makes the gap The semiconductor directly below the substrate insulator is depleted of holes (majority carriers).

Figure 3b shows a state in which the negative gate voltage is applied much higher than in Figure 3a. shows. As a result, holes are transferred to the 5t-8in2 interface below the gate electrode. is attracted to. When a larger negative gate voltage vG is applied, the hole layer becomes a buried channel. serves to protect the channel from gate voltage effects. In this way, holes accumulate at the gate. The dark current value decreases. The channel potential Vc is The difference between the Mi level EF and the Quasi Fermi level of the empty buried channel Equivalent to. The value of Vc is controlled by gate voltage VG. This control effect is The gate voltage becomes sufficiently negative that holes accumulate on the silicon surface below the gate insulator. It will be carried out until the end. When this state is reached, stop Ha at point VGh (Vc). Ru. These are shown in Figures 4a and 4b. This transition effect is caused by a narrow gate voltage. occurs over a wide range). Fig. 4a shows the dark current reduction effect, and Fig. 4b shows the dark current reduction effect. This shows the state of channel potential saturation when holes are accumulated on the surface.

FIG. 5 shows the operation of the CCD shown in FIG. 1 in the accumulation mode. At the top of the figure, 1 and 1/2 pixels of a positive two-phase CCD shift register are schematically represented. . − pixels contain two gates. Areas (a), (C) for each gate.

(b), Cd) is the transfer and storage area of the buried channel of the gate. 1st a See also figure. The important points shown in this figure are transfer area (a) and and (b) are less doped (n) than the accumulation regions (b) and (d). -1). Methods other than varying the doping amount can also improve storage below the phase gate. and a transfer area can be formed. An example of a suitable method is to gate One example is to vary the thickness of the insulator. For example, the gate insulator thickness in the storage region Make the size larger than that of the transfer area. Lines 1-7 are CCD shift registers As the phase 1 gate is clocked for accumulation in the interstage transfer below Indicates the channel potential (actual n>) and signal charge (shading) in the delay time sequence. It is something that Accumulation mode action during charge integration is similar to accumulation during interstage transfer. I will touch on this after discussing its effects.

(A) Inter-pixel transfer line]: This is the normal inter-stage transmission downstream of the CCD shift register. The voltage and signal charge form at the terminal end of . Voltage applied to phase line Φ2 is low, while the voltage applied to Φ2 is high. The signal charge is connected to the gate connected to Φ1. is held in a storage well below the The surface component (element) of the dark current is connected to Φ2 is suppressed below the gate. Also, the dark current below the gate connected to Φ1 is , this is suppressed by accumulation driving.

Line 2-4: First, phase line Φ1 is set to low 5, ie, toward accumulation.

At this time, all signals 1irR exist below the gate connected to Φ1.

When a certain voltage is applied to one of the phase lines, a transfer area accumulates and this This is the condition for line 4. At this point, the channel potential in the transfer region is saturate. As a result, as the Φ1 voltage further decreases, the gate voltage connected to Φ1 increases. This prevents the channel potential below the transmission region from decreasing further.

Line 5: As this transfer region accumulates, the Φ1 gate voltage decreases further and this reduces the channel potential of the storage region. As a result, destruction of the containment well begins. As a result, the charge handling capacity of the Φ1 gate decreases. Excess signal is phase 1 and leak either backward or forward depending on the relative channel potential of the two. This example In this case, since the channel potential is less than Φ1, excess charge leaks backward. In diagram is shown in shading below Φ2.

Line 6: The gate connected to Φ1 is thus fully accumulated and the signal is and between the pixel gates connected to Φ2. Both gates of each pixel are At the same time, it goes into storage mode. This is shown as the shaded area. Dark current generation The element is suppressed. The channel potential is selected so that the charge capacity does not decrease drastically. There must be. That is, the accumulated charge capacity under the negative phase is line 2 As shown in , the charge capacity under normal non-accumulation bias conditions should not be less than about 172. No. The reason is that the signal under accumulated conditions is distributed between both vixel gates. This is because it will be done.

Line 7: When inter-stage charge transfer takes place, the Φ1 voltage increases and the entire signal returns to Φ It is held below the gate connected to 1. Normal clock sequence applies Then, the charge is transferred from the − stage to the next stage, but the signal is shown on line 1. remains below the Φ1 gate. This signal, however, is The data is transferred for one entire CCD stage. The cycle of lines 1-6 is repeated and this This causes both gates to accumulate simultaneously again. As a result, the dark current of the interstage transfer is suppressed.

The above processing is performed while reading a frame transfer type or interline transfer type CCD. It will be held on. This process is done by changing the vertical CCD position while reading the horizontal output register. Applies to phase gates. The minimum dark current reduction rate is the total phase gate accumulated Depends on the number of minutes of frame readout time. Furthermore, the dark current reduction rate is due to the CCD shift During the time when the gate was not accumulated during the interstage transfer along the register It would be larger if the majority carriers were not ejected from the intermediate gap state.

(B) Integration As a frame transfer architecture, the dark current is It can also be suppressed during the time the light is optically exposed. This is line 6 in Figure 5. This is achieved by biasing the gate as shown. The pixels are shown in Figure 5. It is sufficient that the information is specified so that the information between each pixel is mixed. You won't have to worry about it. In Figure 5, the image pixel is the left gate connected to Φ2. is identified by the central gate connected to the gate and Φ1. The reason is below - This is because the excess charge in the pixel leaks away and therefore remains within the same pixel. . Pixel identification can be done, for example, if the color filter pattern has different colors in the same column. This is important when applied to generate. Storage during readout period As in the case of the product, the accumulation in the transfer region for Φ1 also applies to the accumulation during the integration period. The product channel potential must be more positive than the storage channel potential for the Φ2 gate. Must be.

Full accumulation mode operation at room temperature in true two-phase frame transfer CCD imager It was observed that the dark current was reduced by 50 times.

Figure 6 shows the electrostatic potential and charge capacity of the transfer region and storage region for the Φ1 gate. This is what I did. These curves were calculated from the dimensional electrostatic model of - It is something. The charge capacity is determined to be sufficient to fill the storage area, and Therefore, the electrostatic potential reaches within about 1/2 of the transfer region channel potential. storage area The doping profile in (d) has an electrostatic potential of 7.75 volts at Vg-Q, and 2° It is chosen to have a stored electrostatic potential (Oga Vg) of 3 volts. The transfer area (C) is , an electrostatic potential of 3.75 volts and a storage channel potential of 1.75 volts at Vg-Q. have. The charge capacity is also shown as the same size, approximately 10,000 electrons/μm2 at Vg-0. It is. As the gate decreases and the potential well breaks down, the charge capacity decreases and the During storage and transfer gate storage, the charge capacity reaches approximately 5700 electrons/μm2. this In the state, the excess charge is distributed between the Φ2 gate and 10000 electrons/μm 2, two regions of 5700 electrons/μm2 when both phases are accumulated and dark current is reduced. It will be stored by. Therefore, the saturation or maximum charge capacity of the CCD is It is understood that it is not reduced by accumulation mode action. Electrostatic area of Φ2 transfer region The area is also shown in FIG. Necessary for the vixel identification mentioned in relation to Figure 5. It is configured to be approximately 1/2 more negative than Φ1. The experimentally measured chi The channel potential is consistent with the channel potential curve in Figure 6, which was measured experimentally. The charge capacity does not decrease during the accumulation mode and can be estimated by the calculation shown in Figure 6. The current charge capacity is consistent with the given charge capacity.

The invention has been described with reference to a true two-phase CCD as a particularly preferred embodiment. However, various improvements and changes can be made without departing from the spirit and scope of the invention. One thing is clear. For example, it is also applicable to pseudo two-phase elements.

In such a device, each vixel has four electrons, but the phase lines are Φ1 and There are only two pieces of Φ2. The first 2-vixel electrode is at Φ1, and the second 2-electrode is at Φ1. Φ2, respectively. - in each pair is the storage area, and the other - is the transfer area. area. The channel potential values of the storage area and transfer area in each pair are as described above. is selected for true two-phase use, and the vixels are properly identified.

FIG, Ia FIG.6 international search report international search report

Claims (10)

[Claims] 1. In a buried channel CCD where pixels are identified by two adjacent electrodes In this method, all electrodes are simultaneously activated in the storage mode of the CCD. The method is characterized in that it includes a step of placing the device in the mode. 2. The method according to claim 1, The buried channel has a first pixel gate on the phase line Φ1 and a second pixel gate on the phase line Φ1. Two consecutive pixel gates each consisting of a cell gate connected to a phase line Φ2 two-phase buried channels repeated as the gates of each pixel are placed in the accumulation mode. It is characterized by: 3. The method according to claim 2, Each buried channel gate has a transfer region and a storage region formed in sequence below each gate. has a territory, The channel potential difference between each transfer region is such that a given pixel signal is The characteristic is that the value is selected such that it will not be mixed with the signal contained in the do. 4. The method according to claim 3, The buried channel CCD has a p-type substrate and an n-type buried channel. Features. 5. 5. The method according to claim 4, wherein the CCD is an image sensor; The gate electrodes are transparent and pixelated when they are held during the accumulation mode of action. Characterized by the intergating of charges within the potential well below each gate electrode of the cell. shall be. 6. 5. The method of claim 4, wherein the charge is transferred from one pixel to another pixel. It is characterized by being transferred to 7. 7. The method according to claim 3, wherein the transfer area is a storage area ( doped (n−) than n−), thereby giving a pixel The pixel signal is characterized in that it is not mixed with signals contained in neighboring pixels. 8. 8. The method according to claim 7, wherein the CCD is an image sensor; The gate electrodes are transparent and pixelated when they are held during the accumulation mode of action. The feature is that the charges in the potential well are intergated below each gate electrode of the well. Ru. 9. 8. The method of claim 7, wherein the charge is transferred from one pixel to another. It is characterized by being transferred to. 10.2 In a true two-phase CCD in which gate pixels are repeated consecutively, Subsequently, a transfer doped region is formed under the gate and stored under the gate. Contains an n-type buried channel with a doped region formed below the gate of each pixel. , the transfer region (n--) is more lightly doped than the storage region (n-); The pixel signal given by is configured so that it is not mixed with signals in neighboring pixels. It is characterized by the fact that it is made of