JPH04500572A - Circuit device for addition or subtraction of operands coded in BCD code or dual code - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Addition or subtraction of operands coded with BCD need or dual code The present invention uses a dual adder to convert BCD code or A circuit device for adding or subtracting X numbers encoded with dual codes. related.

Traditionally, addition or addition of operands coded with dual or BCD codes There are yL different circuit devices for subtraction. At that time, with dual code When adding or subtracting the operands of A second circuit is required, but a BCD cover is required! ji′X number, use “9’s complement” The circuit for generating the number was the key point.

Dual addition "Road Technology" 4th edition, Sbringer Publishing, Berlin-Heidelberg-Nini Kok. , 1978, p. 475, 476), and D.A.L.:,! i It is also known to add or subtract B, C, and D using . But that In order to The R2 desal summerizer is required to correct the results of the first dual be. This is necessary when a carry resides within Decay 1'. the spot 6 must be added to the result of the first decoal addition XH, but this The BCD number of may include a pseudo-tetrad. In this case, in addition, the pseudotetra-1゛ The result of the first dual adder Xr, where the number 6 has to be added for removal The correction of is performed by the second chemole adder, which adds 7BCD numbers xC ) Circuitry for! The overall cost of is relatively large, and the circuit is relatively slow and #Jj( ? do.

The object of the present invention is to provide a circuit device of the type mentioned at the beginning, which has a four bit number of operands. Dual addition and subtraction of double-width data using a single dual adder is also possible with BCD. The purpose is to pre-process so that Kaka8 and subtraction can also be performed.

This problem is solved by the features of claim 1.

An input stage connected before the deal adder allows for dual addition or subtraction. If necessary, the formula 6 is added to one of the 1jix numbers. This is B.C. This is true when D-addition is performed and both wave numbers are positive or negative. operand If only one of the numbers is a force injection, this operand is negated. On the other hand, the input stage Treat the dual number so that it only changes when it is a liquid temperature summer number force jet .

In this case it is denied.

The output stage optionally corrects the sum output from the deal summerizer.

This is necessary when no carry occurs at BCD addition zero. in this case, The number 6 must be subtracted from the result of the deair summerizer.

Configured in this way with a correspondingly configured input stage and a correspondingly configured output stage The proposed circuit arrangement does not require a second dual adder, preprocessing the operands and Correcting the result of the dair adder is simply a circuit using multipliers and logic gates. This can be done by This allows for a clear layout of the circuit, and this The advantage is that such a circuit device can be used as a cell in a CAD system. have

The invention will be further explained by means of embodiments shown in the drawings.

Figure 1 is a block circuit diagram of the circuit device, Figure 2 is a circuit diagram of one of the input stages, Figure 3 is a circuit diagram of the output stage, Figure 4 is a circuit diagram of an implementation example of the multiplier circuit used, and Figure 5 is the EXOR circuit used. FIG. 3 is a circuit diagram of an example implementation of the circuit.

FIG. 1 shows a block diagram of the circuit arrangement. In this circuit device, A dual adder DA is used which performs arithmetic logical operations. The dual adder is This is well known and does not require further explanation here.

Addition of positive dual numbers A and B is performed by such dual addition XH. When operands A and B do not need to be preprocessed before addition, whereas operands If one of the arithmetic A and B is negative, this operand is negated and the dual adder supplied to

The situation is different when the liquid temperature Ru. In this case, the operand is D5. must be preprocessed before addition by the alkalinizer. This is done by the input stages EGI and EC2. Input stage EGI converts the operand A into the preprocessed operand X, and the input stage EG2 converts the operand Convert B to preprocessed operand Y. Dua during BCD addition and subtraction The result S of the adder DA, the sum result, must be corrected in many cases1. This is the output stage AGS that performs corrections in relation to carry C during BCD logic operations. This is done by This correction is applied when performing logical operations on operands in dual codes. is not necessary and in this case the result S of the dual adder DA is unaffected by the output stage A. It is passed through the GS and connected to the output end.

First, the function of the input stage EG will be explained, and then the function of the output stage AGS will be explained.

Table 1 Table 1 shows how a single dual adder can perform the desired logical operation. Therefore, it is shown how operands A and B should be preprocessed. first The column shows the desired logical operation of the operands A and B, and the second column shows the desired logical operation of operands A and B. D logic shows how liquid temperature x number B must be pretreated when summer 0 occurs. The third column shows how the operand A is preprocessed during the BCD logical operation. The fourth column indicates whether the The influence of the operand B is shown, and the fifth column shows the operand in the dual logic operation. The influence of A is shown.

In the case of dual logic operations, these are not affected for positive operands A and B. If not, and one of the liquid temperature X numbers is negative, then this operand is negated. I know it will happen.

BCD logical operation When summer 0 occurs, the number 6 is added to one of the two-wave operation numbers during BCD addition. . This is operand B in the case of Table 1. On the other hand, the other operand A is a shadow. Not heard.

Two cases must be distinguished when BCDK is true, the first case liquid temperature) [numbers A and B are negative. In that case, one of the operands, for example, liquid temperature is negated, and the number 6 is added to another operand 1ji) E number, such as operand B, and This sum is then negated. If only one of the operands has a minus sign , this operand is negated, whereas the other liquid temperature X number is unaffected. Thus, in the exemplary embodiment, the operand B is mainly affected, and this is carried out by the input stage EG2. be exposed. Of course, the other operand A could be affected accordingly.

When the BCD logic denominator 0 is used, the operands preprocessed in this way are If a dual logical operation is performed by A, in many cases it is The sum S output from the It will be done. (Correction of Is must be done when the sum S is less than 10 , which is indicated by a carry of the most significant bit position of the sum S, which is then logical It is O. Vj is determined by subtracting Equation 6 from the sum S. This is out This is done in the power stage AGS. whereas the sum S is greater than 10 or or when a dual logic operation is performed, the dual adder D The result of A does not need to be changed and is not affected by the output terminal of the output stage AGS. Output as R.

In the example, the preprocessing of operand A to f-operand X, which is changed from I, is as follows: Since only one negation is performed when there is a minus sign, it is not a problem, but The implementation of input stage EG2 is more complex. 1 here! The case of sowing must be distinguished Various cases arise from Table 1 and Table 2 below.

Table 2 Fl, F2 yOyl y2 y3 1, ObObl b2 b3 1 1 bo bl b2 b child In various cases I! is supplied to the input stage EC2! ability (distinguished by g numbers F1 and F2) be done. The ea function signal F1 indicates whether the number 6 should be added, and the i function signal F2 indicates whether the number 6 should be added. Indicates whether the operand should be negated or not, thus! ! 4 fields in the second column of 1 Table 2 shows how the individual bits of the operand Y are preprocessed. A function that indicates whether a position is caused by a logical operation on the bit position of the $subsum number B. If body number F1 is logical 0, number 6 must be added to operand B. Plus 8! If the function signal F2 is logic 0, the result need not be inverted, otherwise If so, reversal is necessary. These two cases are shown in the first two rows of Table 2. There is. If the function signal F1 is logic I, it is not necessary to add the number 6 to the operand B. , now simply the operand B is negated or not negated in relation to the function signal F2. or

The corresponding results for the preprocessed operand Y are shown in rows 3 and 4 of Table 2. Ru.

A circuit implementing this function is shown in FIG. As shown in Figure 2, this The circuit is exclusively a multiplexer! 1.4 L, lX and logical elements, e.g. Inverter IN and υ[Execute Ii function of Table 2 consisting of the other OR circuit EX In order to develop an input stage EG2 with a correspondingly strict structure, Machine 2 is created and tJ must be 1 Table 3 shows the individual preprocessed operands Y. Functional expressions are shown for the bits. They are the function signals F1. ．． using F2 It is formed by

Table 3 73- ((bl + b2) Fl) (F2b3 + F2 ・b3) + (( bl + b2) PI) (F2b3 + P2b3) Input stage EG2 is referenced respectively. Subcircuit T with at least one multiplexer designated AMUX It consists of S. Connected to one data input end of this output multiplexer AMUX. Corresponding bits of operand B are connected. For example, the output The multiplexer AMUXO has the operand bit bO, and the output multiplexer AMU The operand bin) bl is connected to X1 (hereinafter referred to as the same), and an output multiplexer At the other data input terminal of AMUX, the associated bit of operand B is reversed. It is converted and supplied. Mapping in unaffected or inverted form The through-connection of the bits is connected to the control signal at the input SH of the multiplexer AMUX. It is carried out by the number.

If one data input of the output multiplexer AMUX is connected through or the other To determine whether the data input terminal is connected through the In the first partial circuit TSO that Connected through without being changed. Should bO be connected through? bO is connected through The distinction between exponents and exponents is determined exclusively by the function signal F2. The first partial times accordingly The output multiplexer AMUXO of the circuit TSO receives only the function signal F2 at the control input S. Supplied to H.

The second partial circuit TSI is used to generate the pinpoint y1 from the bit ybl. Ru. Here, both function signals F1 are used to drive the output multiplexer AMUX +. and F2 are required. The control signals for the output multiplexer AMUX1 are shown in the table below. 3, row 2 of function signals F1 and F2. child Thus, the partial circuit TSI performs an exclusive OR operation along with the output multiplexer AMUX+. conditional on EXI and primarily by the configuration of multiplexers and exclusive-OR circuits. It includes an inverter IN which is turned off.

The subcircuit TS2 for generating bit y2 from bit B2 is more expensive.

Here, B2 of the operand B is connected to the output multiplexer A in relation to the control signal. A form that is not inverted by one input terminal D1 of MLIX2 or the other input terminal D2 or inverted form, for which a separate multiple Lexers MυXI and MUχ2 are used. To output multiplexer AMUX2 The control signal for the function is generated using the function signal Fl and the bit) bl of the operand B. be exposed. The control signal for multiplexers MUX1 and MUX2 is the function signal F Obtained from 2. The signal b2 to the data input terminal of the output multiplexer AMUX2 The connection and generation of control signals for the multiplexer are shown in Table 3 Functional formula for Φy2 is shown in more detail. Thus the subcircuit TS2 is the output multiplexer AM Alongside UX2 two other multiplexers MUX1 and MLIX2, inverter data and a Noah element N0RO.

The subcircuit TS3 for generating bit y3 is likewise relatively expensive. out again If the focus b3 is not inverted at the data input terminal of the power multiplexer AMUX3, Connected in reverse or reversed form. The correspondence is multiplexer MUX3 and M This is done via UX4. Control input terminals of multiplexers MUX3 and MUX4 is also driven by the function signal F2. Control of output multiplexer AMUX3 At the input terminal, a logical operation signal obtained from the function signal F1 and bits b1 and b2 is provided. It is given. The logical operations are shown in the functional formula for F3 in Table 3. instructor The subcircuit TS3 also includes several inverters IN, a function signal F1 and an operand. Three logic operation circuits VK that perform logic operations on bits bl and b2 of number B. It consists of a multiplexer. This logic operation circuit is designated with the reference symbol VK. , and also performs the OR operation of operand bins) bl and b2, and then the OR operation. An AND operation is performed between the result of the operation and the inverted *n signal F]. This kind of theory The configuration of Rien Summer Kai iVK is known, and can be easily realized using logic circuits, for example. obtain.

The input stage EG2 thus appears in the various columns of Table 1 in relation to the function signals F1 and F2. Preprocess operand B so that the case shown is realized. thus A preprocessed operand Y is generated at the output end of the input circuit EC2, and the liquid temperature)E number Y is Subsequently, a logical operation is performed on the preprocessed operand X in the dual X adder DA.

At that time, for dual adders, whether the BCD logic operation should be performed or It does not matter whether the logical operation should be performed; these cases can be treated equally. handle it.

As already mentioned, the logic operation results of the dual adder iDA are similar to many BCD logic operations. The necessary conditions a and which must be corrected at zero have already been shown. suitable machine The Noh table is j! ! It is shown in Table 4.

Table 4 F3 Cro rl F2 F3 0 1 sOs2 s2 s3 1 0 sOs2 s2 53 11sos2s2 s3 Different cases can be distinguished in relation to the carry signal C and the function signal F3. that time Function signal F3 indicates whether the BCD logic operation is performed or not, and F3 is logic O. If so, BCD logical denominator 0 is performed. Carry signal from the most significant bit position of sum S Now, whether the result has to be corrected to the BCD logical denominator 0 line is determined by C. If the determined zero carry signal C is a logic 0, the result S is the number 6 subtracted from the result. must be corrected so that the individual positions of the sum result S The functional formula shown in row 1 of Table 4 with 0wA positive result is denoted by R. There is. For all other cases, the result S of El (Dair addition) must be uncorrected. stomach.

That is, the result R at the output of the output stage AGS corresponds to the sum result S. Sunawa In other words, what must be corrected is that function signal F3 and carry C are common according to Table 4. is a logic 0, otherwise no correction is made.

A circuit J1g device with which the correction can be performed is shown in FIG. This circuit device is a dua one for each of the various bits SO to S3 of the sum result from the adder DA. The logical operation circuit VS is executed. Logical operation circuit for sum bit sl or $3 ■ S each includes one exclusive-OR circuit EXI to EX3.

, are associated with exclusive OR circuits EX3 and one input terminal D4 of EX3, respectively. The sum bits sl to s3 are supplied to the other input terminal D3. (F3, carry signal C and possibly a beep) logical operation from sl or S2. The calculation result is provided.

The associated functional expressions executed by each logic operation circuit vS are shown in Table 5. has been done.

Table 5 The first, least significant bit SO of the sum result is unaffected and is already a corrected result. ・Produces rO. Only one conductor is required for this logic circuit vSO. Ru.

The second logic operation circuit, that is, the logic operation circuit VSI, includes an exclusive OR circuit EXI, It consists of a NOR element N0R1 that performs a logical operation on the function signal F3 and carry signal C. There is. The method of logical operation is shown in row 2 of Table 5.

Logic operation circuit VS2, along with exclusive OR circuit EX2, performs function signal F3, carry A NOR element N0R that performs a NOR logic operation on the signal C and the inverted sum bit Sl The correct form of the 6 individual signals, including 2, is obtained by an inverter.

The generation of the signal r3 from the sum bit s3 is performed by another node in addition to the exclusive OR circuit EX3. By logical operation 7tyIllr V S3 with a elements NOR3 and N0R4. will be held.

Bits S1 and S2 are logically operated on each other by NOR element N0R4, and NOR element The result of the logical operation of NOR element N0R4 is logically operated with the function signal F3 by NOR3. It will be done. The correct value of this signal is also generated via the inverter +N. logic The method of operation is shown in row 4 of Table 5.

As shown in the figure, the output stage AGS includes an exclusive OR circuit EX and a NOR element, respectively. Contains logical operation circuits VSI to VS3 having NOR and inverter IN There is.

The input stage EC2 according to FIG. 2 and the output stage AGS according to FIG. 3 have a regular structure. and a small number of various cells, such as multiplexer MUX, exclusive OR circuit E It consists of X, NAND and Noah elements and an inverter. configured like this The developed circuit can be easily used in a CAD system.

Furthermore, the circuit described above is similar to the multiplexer in FIG. 4 and the drain in FIG. As shown for other OR circuits, it can be constructed in C-MO3 technology.

As a result, fewer transistors are required for these circuits, and The circuit can be realized saving area. Overall, it is very suitable for various calculation modes. By requiring only a small number of circuit elements, propagation times are kept very short. Ru.

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Claims (11)

[Claims] 1. Code with BCD code or dual code using dual adder In a circuit device for adding or subtracting operands, a) one of the operands is A first input stage before one input of the dual adder (DA) for arithmetic (B) (EG2) is connected, and the first input stage (EG2) is -BCD operand When performing a logical operation, when the operand is positive, add the number 6 to one operand (B), -For negative operands, add number 6 to one operand (B) and negate the result. death, - This applies when both operands have different signs and one operand (B) has a positive sign. without changing their operands, - When both operands have different signs, and one operand (B) has a negative sign, deny this, - Use this when one of the negative operands (B) is used in logical operations with dual codes. Deny, otherwise do not change, b) A second input stage (EGI) is connected before the second input of the dual adder (DA). If the second input stage (EGI) is negative and the other operand (A) is deny it, otherwise do not change it, c) An output stage (AGS) is connected to the output end of the dual adder (DA), and the corresponding The output stage (AGS) performs the BCD logical operation of the operands (A, B) and the sum result (S). In the absence of a carry (C) from the most significant bit position, a corrected sum (R) is issued. In order to obtain the result, subtract the number 6, otherwise the result (S) is characterized by having no effect. circuit device. 2. The first input stage (EG2) has two functions for two function signals (F1, F2). The first function signal (F1) is added to one operand (B) by the number 6. The second function signal (F2) determines whether one operand (B) is negated. 2. The circuit device according to claim 1, wherein the circuit device determines whether or not the data is transmitted. 3. The first input stage (EG2) has one constraint per bit of one operand (B). control input terminal (SE) and two data input terminals (D1, D2), one for one one for the associated bit of arithmetic (B), the other in its negated form. has an output multiplexer (AMUX) for this bit of A partial circuit (TS) is provided, - the first partial circuit (TS) for the least significant bit (b0) of one operand (B); The output multiplexer (AMUXO) of 0) transfers this bit (bO) to the second function. When the signal (F2) has one value (1), it is connected to the output end, otherwise If so, pass through this bit in inverted form to the output and The output of the second partial circuit (TS1) for the next most significant bit (b1) of (B) The power multiplexer (AMUX1) connects this bit (b1) to the first and second When the exclusive OR operation of the function signal takes one binary value (1), a pass connection is applied to the output terminal. otherwise connect this bit in negated form to the output, - the third partial round for the next most significant bit (b2) of one operand (B); The output multiplexer (AMUX2) of the path (TS2) selects this bit (b2) as 2 functional signals (F2) are present and the first functional signal (F1) and one operand The NOR logic operation on the next lower bit (b1) of the number takes one binary value and also means that the second function signal (F2) takes the binary value of the other and the first function signal and one The OR logical operation of the immediately next lower bit (b1) of the operand is one binary value (1 ), connect it through to the output end, otherwise this bit is negated. Connect to the output end in the form of - the fourth partial circuit (T The output multiplexer (AMUX3) of S3) transfers this bit (b3) to the second The function signal takes one binary value (1) and the first function signal (F 1) and the values of the two immediately next lower bits (b1, b2) of one operand (B). When an AND logical operation with a logical operation takes one binary value, or the inverted form the second function signal in the state, the inverted first function signal (F1) and one operand; Inverted AND with both lower bits (b1, b2) of number (B) When the logical operation takes one binary value (1), connect it through the output terminal, otherwise If so, this bit (B3) is passed through to the output terminal in a negated form. 3. The circuit device according to claim 2. 4. The output multiplexer (AMUX0) of the first subcircuit (TS0) controls the A second function signal is applied to the input terminal (SE) in inverted form, and Invert the least significant bit (b0) of one operand to one data input terminal (D1) This bit is not inverted in the other data input terminal (D2). 4. A circuit arrangement as claimed in claim 3, characterized in that it is provided with. 5. The output multiplexer (AMUX1) of the second subcircuit (TS1) is The bit (b1) associated with the data input terminal (D1) of one operand in its inverted form and also inverts this bit to its second data input (D2). and the inverted second machine at its control input (SE). a first exclusive OR that performs a logical operation on the function signal and the inverted first function signal; 4. The circuit according to claim 3, wherein an output signal of the circuit (EX0) is provided. road device. 6. The third partial circuit (TS3) is the output multiplexer (AMUX2), the first Multiplexer (MUX1) and second multiplexer (MUX2) and Noah element (NOR0) and a first and second multiplexer (MUX1 , MUX2) is controlled by the inverted second function signal (F2). the first data input of the first multiplexer and the second multiplexer. The bit (b2 ) in an inverted form, and the first multiplexer and the second multiplexer This bit is applied uninverted to the other data input terminal of the A first multiplexer at one data input end of the power multiplexer (AMUX2) (MUXl) is also connected to the other data input of the output multiplexer. The output terminal of the multiplexer (MUX2) is connected, and the output terminal of the multiplexer (MUX2) is connected. The first function signal (F1) and the lower bits of one of the operands are It is characterized by being formed by a NOR logical operation of the bit (bI) and given a signal. 4. The circuit device according to claim 3. 7. The fourth subcircuit (TS3) connects the output multiplexer (AMUX3), the third and the fourth multiplexer (MUX3, MUX4) and logic operation circuit (VK)? control of the third and fourth multiplexers (MUX3, MUX4) An inverted second function signal (F2) is applied to the input terminal, and the third multiplex one data input of the lexer and the other data input of the fourth multiplexer is given the associated bit (b3) of one operand (B). , the other data input of the third multiplexer and one of the fourth multiplexers. This bit is inverted and applied to the data input terminal of the output multiplexer. One data input terminal of the multiplexer (AMUX3) is connected to the output terminal of the third multiplexer, or The other data input terminal is connected to the output terminal of the fourth multiplexer. At the control input of the output multiplexer, an inverted first function signal (F1) and one OR logic between the two immediately next lower bits (b1, b2) of the operand (B) of It is formed by a logic operation circuit (VK) by the inverted AND logic operation with the operation. 4. The circuit device according to claim 3, wherein a signal is applied to the circuit device. 8. In the output stage (AGS), a) The least significant bit (s0) of the sum result (S) is converted to the least significant bit (s0) of the corrected sum ( A conducting wire (VS0) passing through and connecting to the output end is provided as r0), and b) a sum connection. A BCD logical operation is performed on the next most significant bit (s1) of the result (S). and there is no carry signal (C) in the most significant bit position of the sum result, The associated bit (s1) is inverted and output as a correction bit (r1). a first logical operation circuit which is transit tangent to and otherwise passes through in an uninverted form; c) for the next most significant bit (s2), This occurs when a BCD logical operation is being performed and there is no carry signal (C). The exclusive OR logic operation of bit (s2) and the next lower bit (ε1) is As the associated bit (r2) of the corrected sum (R), If not, a second logical operation circuit (VS2) is provided that does not affect this bit. d) A BCD logical operation is performed on the most significant bit (s3) of the sum result. This bit and the inversion of the sum result when the carry signal (C) is present and the carry signal (C) is not present. Exclusive OR with the OR logical operation of the two immediately next lower bits (s2, s1) Pass-through logical operations as associated bits (r3) of corrected sum However, a third logic operation circuit (VS3) is provided that would otherwise not affect this bit. being given The circuit device according to claim 1, characterized in that: 8. Each logical operation circuit (VS1, VS2, VS3) is one exclusive OR circuit (EX1, EX2, EX3), and their exclusive OR circuits include The bits (s1, s2, s3), and the third function signal (F3), carry signal (C) and and, in some cases, the logical operation result of the lower bits of the sum result. 8. The circuit device according to claim 7. 9. The second logical operation circuit (VS1) is an exclusive OR circuit (EX1) and a NOR element. (NOR1), and the NOR element (NOR1) is an exclusive OR circuit (EX1). ), and is also connected to one input end of the third function signal (F3) and carry 9. The circuit device according to claim 8, wherein the signals (c) are logically operated on each other. 10. The second logical operation circuit (VS2) is an exclusive OR circuit (EX2) and a NOR circuit. (NOR2), and one input terminal of the exclusive OR circuit (EX2) The bit (s2) to which the signal is associated is also connected to the NOR element (N The output terminal of OR2) is connected, and the NOR element (NOR2) is connected to the third function signal. signal (F3), carry signal (C), and the next lower bit (s1) of the surface result. 9. The circuit device according to claim 8, wherein the circuit device performs logical operations on each other in an inverted form. . 11. The third logic operation circuit (VS3) is connected to the exclusive OR circuit (EX3) and the two Consists of NOR elements (NOR3, NOR4), one input of exclusive OR circuit The bit (s3) associated with the sum signal is at one end, and the third bit (s3) is at the other input end. The output end of the NOR element (NOR3) is connected, and the fourth NOR element (NOR4) performs a logical operation on the inverted two lower bits (s1, s2) of the sum result, Also, the third NOR element (NOR3) is connected to the output signal of the fourth NOR element (NOR4). The result of the NOR logic operation of the function signal (F3) and carry signal (C) of 3 is inverted. 9. The circuit device according to claim 8, wherein the circuit device performs logical operations on each other.