JPH0449711A - Differentiation circuit - Google Patents

Abstract

PURPOSE:To generate a pulse with extremely narrow width in this invention by performing the differentiating operation of a logic inversion circuit consisting of a complementary MOS transistor in the rise and fall periods of a pulse supplied to the input terminal of the circuit. CONSTITUTION:A pulse waveform to be differentiated is inputted to the input of the logic inversion circuit consisting of an n-MOS transistor 6 and a p-MOS transistor 7 via the input terminal 1. The potential of a terminal 4 can be set as potential of logic level '0' only in the rise and fall periods of the pulse supplied to the input terminal 1 by comparing a constant current supplied to a constant current input terminal 3 with a through current supplied from the logic inversion circuit consisting of the transistors 6 and 7 and setting it so as to make it small, and an operation as a differentiation circuit is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differentiating circuit, and particularly to a differentiating circuit used in a complementary MOS transistor integrated logic circuit.

[Conventional technology]

Conventionally, this type of differentiating circuit has been realized by calculating the exclusive OR of a pulse delayed by a delay circuit and an original pulse. Here, a conventional example of a differential circuit according to the above method will be explained with reference to the drawings.

FIG. 7 shows an example of a conventional differential circuit, and FIG. 8 shows a circuit developed by expanding the circuit described using logic blocks in FIG. 7 at the transistor level. Figure 9 shows the 6th
9 is a timing chart for explaining the operation of the differentiating circuit shown in FIGS.

In FIG. 7, terminal 1 is an input terminal, connected to the input of exclusive OR 4, and input to delay circuit 2 shown by a block surrounded by a broken line. Delay circuit 2
The output of is inputted to exclusive OR 4 via terminal 3.

The output of exclusive OR 4 is connected to terminal 5, which is an output terminal.

Next, the operation of the conventional example will be explained using FIGS. 7 and 9. In the circuit shown in FIG.
A pulse indicating a waveform is input to a), and is input to a delay circuit 3 consisting of a three-stage cascaded logic expansion circuit surrounded by a broken line 2, and to an exclusive OR 4, respectively. The pulse input to the delay circuit 2 is delayed by the time ip, d necessary for passing through the three stages of logic decision circuits, and its polarity is reversed, so that it is exclusively output as the pulse shown in FIG. 9(b). logical sum 4
is input via terminal 3. Exclusive OR 4 is the 9th
The exclusive OR of the pulse shown in figure (a) and the pulse shown in figure (b) is taken, and the pulse shown in figure 9 (a) is calculated as shown in figure 9 (C).
) and the logic level of the pulse shown in Figure 9(b) match, the logic level "0°°" is output, so the rise and rise of the waveform shown in Figure 9(a) A logic level with a pulse width of tpd immediately after the downlink.
A pulse of 0'' is output to terminal 5.

In the end, the circuit of this conventional example is
It operates as a differentiating circuit that outputs a pulse that becomes logic level "0" immediately after the rising and falling edges.

[Problem to be solved by the invention]

The above-mentioned conventional differentiating circuit uses a three-stage cascade connection of logic inverting circuits for the delay circuit, which has the drawback of increasing the number of elements.

In addition, the output pulse width is almost determined by the product of the delay time per stage of the logic inversion circuit and the number of stages connected, so if you want to obtain a narrow output pulse, it is necessary to use the logic inversion circuit. It is necessary to reduce the number of stages. For example, if the number of stages of the logic inversion circuit is set to one stage, there is almost no difference between the delay time per stage of the logic inversion circuit and the delay time of the wiring until it is directly input to the exclusive OR, and complementary Type M
The operation of the differential circuit itself is no longer guaranteed due to various possible variations in the device parameters of the OS+- transistor or the process that realizes the circuit. Therefore, it has the disadvantage that it is not possible to generate a differential pulse with a very narrow width.

SUMMARY OF THE INVENTION An object of the present invention is to provide a differential circuit that requires only a small number of elements and can generate differential pulses with a narrow width.

[Means to solve the problem]

F) The VR branch circuit of the present invention includes transistors of one conductivity type and opposite conductivity type transistors connected in series that receive the same input signal to the gate, and a current flowing between the one conductivity type transistor and the opposite conductivity type transistor. The present invention is characterized in that it has a current mirror circuit whose input is connected to an output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Terminal 1 is an input terminal, terminal 2 is a power supply terminal, terminal 3 is a constant current input terminal, terminal 4 is an output terminal, and terminal 5 is an installation terminal. n-type MOS
A logic inversion circuit is constructed by the transistor 6 and the P-type 1-range staf. N-type MOS transistor 8 and n-type MO8! - transistor 9, P-type MOS transistor 10, and P-type MOS transistor] 1 constitute a current mirror circuit, respectively.

In a logic inversion circuit consisting of an n-type MO5)-transistor and an n-type MOS transistor 7, the source of the p-type MO3)-transistor is connected to the power supply terminal 2, and the soak of the n-type MOS transistor 6 is the fl-type MO5! - connected to the input of a current mirror circuit consisting of transistors 8 and 9;

[The sources of type 1 MOS transistors 8 and 9 are connected to the connection terminal 5
commonly connected to p-type MOS transistors 10 and 11
The sources of are commonly connected to the power supply terminal 2. n-type MOS
the output of a current mirror circuit consisting of transistors 8 and 9;
The outputs of the current mirror circuit consisting of p-type MO3I transistors 1o and 11 are commonly connected to the output terminal 4. p-type M
O8) The input of the current mirror circuit consisting of transistors 10 and 11 is connected to the current input terminal 3.

Next, the operation of this embodiment will be explained. A differentiated pulse waveform is inputted via the input terminal 1 to the input of a logic inversion circuit consisting of an n-type MOI transistor and an n-type MOS transistor 7.

When the potential of the input pulse is at the logic level "1", the n-type MOS transistor 7 becomes non-conductive, and when the potential of the input pulse is at the logic level "0", the n-type MOS transistor 7 becomes non-conductive. 6 becomes non-conductive, p
No current flows in the path leading from the source of the type MO8) Ranjistaf to the source of the n-type MO3)-Rangestaro.

However, the input pulse does not take only potentials corresponding to logic "1" and logic "0°", but takes a value intermediate between the potentials of logic "0" and "1" in its rising and falling periods. Therefore, during the rising and falling periods of the input pulse, the n-type MOS transistor 6 and the n-type MOS
At the same time, transistor 7 becomes conductive, and a through current flows in a path from the source of n-type MOS transistor 7 to the source of n-type MOS transistor 6.

This current flows from the source of the n-type MOS transistor 6 to n
The current is output to terminal 4 via a current mirror circuit consisting of type MoS transistors 8 and 9.

A constant current applied to the constant current input terminal 3 is also applied to the terminal 4 via a current mirror circuit consisting of p-type MO3) transistors 10 and 11. n-type MOS transistor 6 and n-type MO
By setting in advance to be smaller than the through current given from the logic inverting circuit consisting of the S transistor 7, the potential of the terminal 4 remains at the logic level only during the rising and falling periods of the pulse given to the input terminal 1. “
It can be set to a potential of 0'° and can operate as a differential circuit.

In the first embodiment shown in FIG. 1, the polarity of the output differential pulse was in the direction toward the logic level "0", but in the second embodiment shown in FIG. Set the polarity of the pulse to logic level ``1''.

It can be set in the direction towards.

In the second embodiment shown in FIG. 2, the n-type MOS transistors 8 and 9 in the embodiment shown in FIG. This is a circuit in which transistors 210 and 211 are respectively replaced. The direction of the constant current applied to the constant current input terminal 4 is simply changed to the direction in which it flows.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

Elements and terminals common to those in the first embodiment will be given the same element numbers and their explanations will be omitted.

In this embodiment, the n-type MOS transistor 7 operates as a constant current circuit between the source of the n-type MOS transistor 7 and the power terminal 2.
An OS transistor 12 is connected. This p-type MO
3) By the transistor 12, the n-type MOS transistor 6
It is possible to limit the maximum value of the through current flowing through the logic inverting circuit consisting of the P-type MO3) and Langistaff, and it is possible to reduce the current consumption of the differentiating circuit compared to the first and second embodiments. There are advantages.

FIG. 4 shows a circuit for generating differential pulses of different polarities according to the embodiment shown in FIG. 3, and has a configuration in which the p-type MO5) transistor 12 is replaced with an n-type MOS transistor 212. FIG. 5 is a circuit diagram of a fifth embodiment of the present invention. Elements and terminals common to those in the first to fourth embodiments are given the same element numbers, and their explanations will be omitted.

The source of the n-type MOS transistor 7 is connected to the power supply terminal 2 via a parallel circuit of a Schottky barrier diode 13 and a resistor 14. It is also connected to the gate of the source follower transistor 312. The source of the source follower transistor 312 is connected to the drain of the constant current transistor 10 and the output terminal 3.

In this embodiment, a through current flowing through a logic inversion circuit consisting of an n-type MOS transistor 6, a p-type MoS transistor 6, and a p-type MOS transistor 7 is controlled by a parallel circuit of a key barrier diode 13 and a resistor 14.
Voltage conversion: After that, source voltage 40 watts 1 helangister 3
By adopting a circuit format that outputs to output terminal 3 through 13, a circuit that combines a differential circuit and a KCI-logic 1 novel conversion circuit is realized, and is used to realize an integrated circuit. Although the process is complicated, it has the advantage that a very narrow differential pulse can be directly converted into ECL1/Bell and output.

FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention. Elements and terminals that are common to the first to fifth embodiments will be given the same element numbers, and their explanation will be omitted.

In this embodiment, a NOR logic gate circuit is constructed by an n-type MO5I transistor 17°]8 and a ρ-type MOS transistor 1.5.16. With this configuration, there is an advantage that the operation of the differentiating circuit can be stopped by setting one terminal to the logic "1'° level."

〔Effect of the invention〕

As described above, the present invention is directed to a logic inverting circuit constituted by complementary MOS transistors or a gate 1 circuit, or a through current consumed during the rising and falling periods of a pulse applied to its input terminal. By detecting and performing current-voltage conversion to perform differential operation, a very narrow pulse can be generated using a simple circuit with a small number of elements.

In addition, by changing the format of the current-voltage conversion circuit, the polarity of the output pulse can be reversed, and the output logic 1/
Since it is possible to change the bell, there is an effect that it is possible to easily interface with a circuit connected to a subsequent stage of this circuit.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Fig. 2 is an FfPf diagram showing a second embodiment of the invention, and Fig. 3 is a circuit diagram showing a third embodiment of the invention. 4 is a circuit diagram showing a fourth embodiment of the present invention, FIG. 5 is a circuit diagram showing a fifth embodiment of the present invention, and FIG. 6 is a circuit diagram showing a sixth embodiment of the present invention. 7 and 8 are circuit diagrams of conventional differential circuits, and FIG. 9 is an operating waveform diagram of the circuit shown in FIGS. 7 and 8. 1... Input terminal, 2 ...Power terminal, 3... Constant current input terminal, 4... Output terminal, 5... Ground terminal, 6, 8
9--- ri type MOS l-transistor, 7,10
．． 1 ]・= p-type MOS transistor. Figure 1

Claims (1)

[Claims] 1. A transistor of one conductivity type and a transistor of opposite conductivity type connected in cascade receiving the same input signal at their gates, and a current flowing between the one conductivity type transistor and the opposite conductivity type transistor as input; A differentiator circuit comprising a current mirror circuit whose output is connected to an output terminal. 2. A transistor of one conductivity type and a transistor of opposite conductivity type that receive the same input at a signal gate and are connected in cascade, a means for converting a current flowing between the one conductivity type transistor and the opposite conductivity type transistor into a voltage, and the conversion. and means for generating an output signal in response to a voltage applied to the differential circuit. 3. The differential circuit according to claim 1, further comprising current limiting means for controlling the amount of current flowing into the one conductivity type transistor and the opposite conductivity type transistor. 4. The differential circuit according to items 1 to 3, characterized in that a logic gate circuit is formed by providing a plurality of the transistors of one conductivity type and the transistors of the conductivity type.