JPH0448499A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve the yield of product even at the time of over-deletion by performing the read/write of information through a spare bit line to a spare memory cell when the specified bit line is selected. CONSTITUTION:A half latch circuit composed of transistors 15, 16, and 17 of a low decoder 21 receives the input 'H' of an NAND gate 18, and the voltage level of a word line 8 is turned to 'L' level. By this operation, all the word lines are turned to the 'L' level. Next, reading operation is performed while the low address is fixed and only the column decoder address is rotated against the all addresses. Only the bit line including the over-deleted memory transistor is turned to the 'L' level since all the voltage level of the word line is turned to the 'L' level. In this way, the bit line including the over-deleted memory transistor is specified, and the bit line is replaced by the spare bit line. Thus, the yield of the product can be improved even when there is an over-deleted transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to an electrically rewritable and batch erasable nonvolatile semiconductor memory device (FLASHEEPROM).

[Prior Art] FIG. 5 is a block diagram of a conventional nonvolatile semiconductor memory device.

In the figure, the nonvolatile semiconductor memory device includes an address buffer 10 into which addresses of memory cells to be stored are input.
7 and a column decoder 10 into which the column address is input.
8, a row decoder 109 to which a row address is input, and a high voltage switch 110 to switch the potential of the word line.
I10 buffer 111 where data is input/output;
A sense amplifier/write driver 112 for amplifying read data or holding write data, a Y gate 113 for selecting a predetermined bit line, and a memory cell array in which memory cells arranged in a matrix are arranged. 114, a high voltage control circuit 119 for controlling the high voltage applied to the memory cell array 114, a control signal buffer 120 to which control signals are input, a control circuit 121 for controlling various operations, and a high voltage control circuit 119 for controlling the high voltage applied to the memory cell array 114; and an array source switch 122 that switches the potential.

In the memory cell array 114, the configuration of one memory cell is representatively illustrated. Memory cell 118 is arranged at the intersection of one bit line 115 and word line 116. A bit line 115 is connected to the drain of the memory cell 118. The source line 11 is connected to the source of the memory cell 118.
7 is connected, and the other source line 117 is connected to the array source switch 122. Word line 116 is connected to the floating gate of memory cell 118 .

Next, the operation of the nonvolatile semiconductor memory device configured as above will be explained.

The operation of this nonvolatile semiconductor memory device is divided into write, erase, and read operations, and in the case of a write operation, it is necessary to erase information contained in memory cells at all addresses.

First, the write operation will be explained.

Address data of an address to be written is inputted via address buffer 107, and a control signal that enables writing is inputted via control signal buffer 120.

Next, high voltage vPP is applied to high voltage control circuit 119. The input address data is decoded by the row decoder 109 and one word line is selected. The input high voltage vPP is controlled by a high voltage control circuit 119 and applied to the high voltage switch 110.

The high voltage switch 110 of the selected word line makes the selected word line a high voltage, and the high voltage switches of other unselected word lines output Ov.

On the other hand, data input via the I10 buffer 111 is latched by the write driver 112. The write driver 112 applies a high voltage to the bit line containing the bit to which information "0" is to be written, and a high voltage to the bit line containing the bit to which information "1" is to be written, via the Y gate 113 selected by the column decoder 108. gives a potential of At this time, the potential of the source line 117 is changed to the switched array source switch 122 based on the signal output from the control circuit 121.
The potential is maintained at Ov.

Here, the schematic structure of the memory cell 118 will be explained with reference to FIG.

Two impurity regions are formed at a predetermined interval on the main surface of semiconductor substrate 105, one of which becomes drain 103 and the other becomes source 104.

An insulating film 106 is formed on a region of a semiconductor substrate 105 sandwiched between a drain 103 and a source 104, and a floating gate 102 is further formed thereon. A control gate 101 is formed on the floating gate 102 with an insulator interposed therebetween. In such a configuration, in a memory cell in which information "0" is written, a high voltage Vpp is applied to the control gate 101, that is, the word line 116, and the high voltage Vpp is applied to the drain 103, that is, the bit line 11.
A write voltage VBR is applied to the source 104 , that is, a source line 117 , and a potential Ov is applied to the source 104 , that is, the source line 117 . Therefore, in this state, avalanche breakdown occurs near the drain 103 of the memory cell and hot electrons are generated. Hot electrons accelerated by the high voltage of the control gate 101 jump over the barrier formed by the oxide film 106 and are injected into the floating gate 102.
It is accumulated there. Information “0” is written by this write operation.
The threshold voltage of the memory transistor to which V is written becomes higher than before the write operation, that is, the control gate 101 has a power supply voltage V. Even if voltage c (5V) is applied, this transistor is no longer ONL.

On the other hand, in the memory cell to which information "1" has been written, the potential of the bit line 115 is 0■, no hot electrons are generated, and the state is unchanged from before writing. That is, this state is an erased state, and the threshold voltage is low.

That is, in a FLASHEEPROM, during writing, electrons are injected from near the drain of the memory transistor to raise the threshold voltage, and during erasing, electrons are extracted to the source to lower the threshold voltage. Further, writing is performed in byte or word units, and erasing is performed on the entire chip at once.

FIG. 7 is a diagram showing erase characteristics of a memory transistor.

Memory transistors are subject to manufacturing process variations,
For example, due to variations in the thickness of the oxide film 106, a memory transistor (A) with high erase characteristics and a memory transistor (B) with low erase characteristics may appear.

FIG. 7 is a diagram showing changes in threshold voltage during erasing of memory transistors having different erasing characteristics.

In the figure, the horizontal axis represents erasing time, and the vertical axis represents threshold voltage. On the vertical axis, the threshold value OV and the erase verify level are shown by broken lines. If the memory transistor (B) has a low erasing characteristic, it takes a long time for erasing, so it takes a considerable amount of time to reach the threshold voltage O■. On the other hand, in the memory transistor (A) with high erase characteristics, the memory transistor (B) is already in a negative threshold voltage state by the time the threshold voltage reaches 0.

In this way, if the erasing time is set sufficiently long to match the memory transistor that erases slowly, the threshold value of the memory transistor that erases quickly becomes a negative value. For reading, it is determined whether the memory transistor is in an erased state or a written state by detecting whether or not current flows through the memory transistor. Therefore, if there is a difference in the threshold voltages of such memory transistors, a problem occurs when reading information.

FIG. 8 is a schematic diagram showing the structure of a part of the memory cells arranged on the matrix in the memory cell 114 of FIG. 5. In FIG.

In the figure, memory cells M11 to M44 are connected to word line W1
~W4 and the intersections of bit lines B1 to B4. Also, the source of each memory cell is the source line S, ~
Connected to S4. Based on the configuration shown in Fig. 8,
The above-mentioned problem at the time of reading will be explained.

First, in the read operation of this device, a power supply voltage V is applied to the word line or control gate 101 of a selected memory cell. 0 and the potential Ov is applied to the word line of the other unselected memory cells, and in this state, it is determined whether the memory transistor of the selected memory cell is turned on, that is, whether a current flows through the bit line. Detect.

For example, assume that the memory cell M22 is the selected memory cell in FIG. 8, and the threshold voltage of the memory cell M4□ is lower than normal due to batch erasing as shown above.

In this case, the word line W2 is selected and the power supply voltage V(() is applied, but the word line W4 is not selected, so its potential remains QV. For example, information "0" is written to the memory cell M2. If the word line W
Even with the selection of 2, this memory transistor is not turned on, that is, no current is generated in the bit line B2. but,
When the threshold voltage of memory cell M42 is a negative value, even if the word line W4 is not selected,
This memory transistor will be turned on. As a result, the bit line B2 connected to the memory transistor M4°
A current is generated in the memory transistor M2°, and this causes the memory transistor M2° to be judged as if information “1” had been written therein. In this way, if even one of the memory cells connected to a bit line has a negative threshold voltage, current will flow through that bit line even if that memory cell is not selected. As a result, the correct information of the selected memory cell cannot be compared.

Furthermore, in writing, a high voltage is applied to the drain of the memory transistor, a current is caused to flow between the drain and the source, and hot electrons generated thereby are injected.

Therefore, if there is a transistor with a negative threshold voltage as described above, that transistor is always on (hereinafter referred to as "over-erased state"), so no high voltage is applied to that bit line, and writing cannot be performed. It's gone.

Therefore, in the conventional example, the erasing operation is performed according to a flowchart as shown in FIG. 9 to prevent over-erasing.

In the figure, when the erase mode is first entered in step S1,
A short erase pulse is applied in step S2. Next, in step S3, it is verified whether or not the memory transistor to which the erase pulse has been applied has been erased. If it has not been erased, the process returns to step S2 and the erase pulse is applied again. Such erasing operation is performed for all memory transistor addresses until the final address is reached (S4). This ends the erase mode (S5).

[Problems to be Solved by the Invention] In the above-mentioned nonvolatile semiconductor memory device, if a long erase pulse is applied due to an operational error or some other reason, and a part of the memory transistor is over-erased, the above-mentioned problem occurs. , it becomes impossible to write or read. If even one memory transistor is over-erased in this way, the chip will no longer be able to perform write and read operations correctly, which will reduce the yield of the product.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device that can improve product yield even when overerased. .

[Means for Solving the Problems] A nonvolatile semiconductor memory device according to the present invention is arranged in a matrix of rows and columns, each of which has a plurality of floating gates that can inject and extract electrons. a plurality of bit lines each provided corresponding to a row of memory cells and connected to each of the memory cells in the corresponding row; and spare memory cells corresponding to at least one column of memory cells. , a spare bit line provided corresponding to the spare memory cell and connected to each of the spare memory cells, a selection means for selecting one of the bit lines, and a memory cell via the selected bit line. reading/writing means for writing information into or reading information from either of the memory cells; and identifying means for identifying a bit line connected to a memory cell from which electrons have been extracted in excess of a predetermined amount; , a reading/writing means for writing/reading information to/from the spare memory cell via the spare bit line instead of the specified bit line when the bit line specified by the selection means is selected; and control means for controlling the.

[Operation] In this invention, if there is an overerased memory transistor, the bit line connected to that memory transistor is replaced with a spare bit line.

[Embodiment] FIG. 1 is a diagram showing a circuit configuration of a main part of an apparatus according to an embodiment of the present invention.

A word line 8 is connected to the control gate of each of memory transistors 1 to 3, and an end of the word line 8 is connected to a row decoder 21. The row decoder 21 is provided with a NAND gate 18 connected to a connection line 19 to which the signal πWL is input. The output of the NAND gate 18 is
It is connected to each gate electrode of P-channel type transistor 16 and N-channel transistor 17 connected in series between terminal 20b and ground power supply V3g. A P-channel transistor 15 is provided between node N and terminal 20a, and its gate electrode is connected to node N4. The sources of each of memory transistors 1 to 3 are connected to source line 7. In addition, the drains of each of them are connected to bit lines 4 to 4.
bit lines 4 and 5 are connected to sense amplifier 23 and write driver 24 via Y-gate transistors 9 and 10. Note that the memory transistor 3 is a spare memory cell transistor, and its drain is connected to the spare bit line 6 and similarly connected to the sense amplifier 23 and the write driver 24 via the spare Y gate transistor 11. Y gates 9 and 10
The gates of are connected to normal Y gate lines 12 and 13, and these gate lines are connected to column decoder 22. The gate of the spare Y gate transistor 11 is connected to a Y gate line 14 which becomes "H" level when selecting the spare bit line 6, and the gate line is connected to the column decoder 22.

FIG. 2 is a block diagram showing the entire chip according to one embodiment of the present invention.

Regarding its configuration, the differences from the block diagram shown in the conventional example in FIG. 5 will be mainly explained.

The difference from the conventional example shown in FIG. 5 is that a redundant circuit 41 is provided which receives the outputs of the address buffer 37 and the high voltage control circuit 39 and supplies the internally processed signals to the column decoder 34. be.

FIG. 3 is a diagram showing the internal configuration of this redundant circuit 41.

In the figure, a nonvolatile latch 50 and a comparator 51 each receiving address signals AO to AN are connected in series. Further, the address signals A0 to AN enter the nonvolatile latch 50 and are also directly input to the comparator 51. The output of the comparator 51 is input to a NAND gate 52, and is passed through an inverter 53 to a signal SP.
The configuration is such that I is given to the column decoder 34.

Next, the operation of a nonvolatile semiconductor memory device according to an embodiment of the present invention will be explained using FIGS. 1 to 3.

First, the operation of identifying a bit line including an over-erased memory transistor and the operation of replacing that bit line with a spare bit line will be described.

When a control signal for activating a bit line specifying mode is input, the signal AWL goes to "L" level, and the outputs of all NAND gates 18 of the row decoder 21 go to H" level. Transistor 15.1
A half latch circuit constituted by NAND gate 6 and transistor 17 receives the "H" input from NAND gate 18 and sets the voltage level of word line 8 to "L" level. This operation causes all word lines to go to "L" level.

Next, a reading comparison operation is performed in which the row address is fixed and only the column decoder address is rotated for all addresses. Since the voltage level of all the word lines is at the "L" level, only the bit line containing the over-erased memory transistor (threshold value is negative and is in the ON state) is at the "L" level. Become. Therefore, the column address that becomes this "L" level is memorized.

The above operation makes it possible to specify the bit line connected to the over-erased memory transistor.

Next, the operation of replacing the bit line identified in the above operation with a spare bit line will be described.

When a control signal for activating the bit line replacement mode and the column address stored above are inputted to the buffer 40 and the address buffer 37 from the outside, a high voltage is applied to the vPP pin connected to the high voltage control circuit 39. or given.

The column address enters the non-volatile latch 50 of the redundant circuit 41 and is stored non-volatilely using a high voltage. If you want to replace a plurality of bit lines, you can do so by repeating the same operation as above as long as there are spare bit lines.

Next, a case will be described in which normal read/write operations are performed after replacement as described above.

The input column address is also given to the redundancy circuit 41, and if the address is an address that replaced the bit line, the data in each nonvolatile latch 50 in the redundancy circuit 41 and the input address data are the same. become. Therefore, all outputs of the comparator 51 become "H" level. All inputs to the next stage NAND gate 52 are “H”
Therefore, the output of the inverter 53 becomes "H" level, and the signal SPI for selecting the spare bit line becomes "H" level.
” level. Signal 5PIJ (when it becomes “H” level,
In the column decoder 22, normal Y gate lines 12 and 1
3 are all set to “L” level, and the Y corresponding to the signal SPI
Only the gate line 14 is set to "H" level. By this operation, the replaced spare bit line can be selected.

On the other hand, if the input column decoder address is a normal address signal, at least one of the outputs of the comparator 50 in the redundant circuit 41 is at "L" level, so the NAND gate 52 outputs a "H" level signal. The signal SPI is kept at the "L" level, and the bit line is not replaced.

FIG. 4 is a block diagram of a nonvolatile semiconductor memory device according to another embodiment of the invention.

In this embodiment, the bit line specifying operation and replacement operation shown in the previous embodiment are automatically performed inside the chip. The difference from the previous embodiment shown in FIG. 2 is that the self-test control circuit 43 and address buffer 42
This is because an address latch function has been incorporated into the system. Self-test control circuit 43 generates signal AWL, determines read data, controls column address latch, and controls redundancy circuit 41. address latch 42
latches the column address of the bit line that becomes "L" level when all word lines are set to "L# level" and read.

[Effects of the Invention] As explained above, even if there is an over-erased memory transistor, the present invention allows correct write and read operations by replacing the bit line connected to the memory transistor with a spare bi-soto line. As a result, the yield of products is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a circuit configuration of a main part of a device according to an embodiment of the present invention, FIG. 2 is a block configuration diagram according to an embodiment of this invention, and FIG. 3 is a specific configuration of the redundant circuit shown in FIG. 2. 4 is a block diagram of another embodiment of the present invention, FIG. 5 is a block diagram of a conventional nonvolatile semiconductor memory device, and FIG. 6 is a cross-sectional structure of the memory cell shown in FIG. figure,
FIG. 7 is a diagram showing changes in threshold voltage of memory transistors with different erase characteristics, FIG. 8 is a diagram showing a specific layout of memory transistors included in the memory cell array of FIG. 5, and FIG. 9 is a diagram showing a conventional FIG. 3 is a flowchart showing an erase operation in erase mode. In the figure, 1 and 2 are memory transistors, 3 is a spare memory cell, 4 and 5 are bit lines, 6 is a spare bit line,
8 is a word line, 9 and 10 are Y gates, 11 is a spare Y gate, 12.13 is a Y gate line, 14 is a spare Y gate line, 15.16 is a P channel type transistor, 17 is an N
Channel type transistor, 18 is NAND gate, 19
22 is a signal line, 22 is a column decoder, 23 is a sense amplifier, 24 is a write driver, 41 is a redundant circuit, 50 is a nonvolatile latch, 51 is a comparator, 52 is a NAND gate, and 53 is an inverter. Note that in each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A plurality of memory cells arranged in a matrix of rows and columns, each of which includes a floating gate into which electrons can be injected and extracted, and each of which corresponds to a row of the memory cells. a plurality of bit lines connected to each of the memory cells in the corresponding row; a spare memory cell corresponding to at least one column of the memory cells; and a plurality of bit lines provided corresponding to the spare memory cell. a spare bit line connected to each of the spare memory cells, a selection means for selecting one of the bit lines, and a means for transmitting information to one of the memory cells via the selected bit line. a reading/writing means for writing or reading information from any of the memory cells; a specifying means for specifying a bit line connected to the memory cell from which electrons have been extracted in excess of a predetermined amount; and a selecting means. When the specified bit line is selected, the reading/writing is performed so that information is written to/read from the spare memory cell via the spare bit line instead of the specified bit line. A nonvolatile semiconductor memory device, comprising: a control means for controlling the control means.