JPH0448492A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up reading speed by making precharge potential applied to a bit line lower than a value obtd. by subtracting the threshold value of a line selection transistor from the power source potential of a memory circuit. CONSTITUTION:Since the operational speed of the memory depends on the discharge time of the precharged voltage of the bit line, the operational speed is speeded up when the precharge voltage to the bit line is lowered. A voltage source 31 with voltage lower than that obtd. by subtracting a threshold value Vthn of a line selection transistor 22 from a power source voltage VDD of the memory, are connected as the power source for precharge. When the voltage of this power source 31 is taken as E, the voltage of 'E-Vthn' (<VDD-Vthn) is precharged to a bit line A. Thus, the operational speed can be speeded up more than when the power source voltage is used as the precharge power source.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory in which the precharging portion of the bit line of the memory is improved.

(Prior Art) Examples of conventional RAM and ROM circuits are shown in FIGS. 13 and 14, respectively. A circuit 11 for precharging the bit line is connected to the bit line of each memory.

12 to 14 are N-channel transistors within the memory cell. Further, conventionally, the precharge circuit 11 includes a first
The one shown in Figure 5 is used. The operation at the time of reading from the above memory will be explained below.

First, the signal "B" shown in FIGS. 14 and 15 is set to "L" (low) level, and the P-channel transistor 21 is turned on and the N-channel transistor 13 is turned off. At this time, if the column selection signal input terminal C from the column decoder is at "H" (high) level, the column selection transistor 22 is turned on, and the bit line A is set to a voltage near the power supply VDD (VDD - Vthn
) (Vthn is the threshold voltage of the transistor 22). Next, terminal B is set to "H" level, P channel transistor 21 is turned off, and N channel transistor 13 is turned on. When the stored content of the memory cell selected by the row decoder is "H", the potential of the bit line does not change, and the output buffer 16 outputs a signal at the "H" level. When the memory content of the memory cell is 'L', rVo D-
When the charge on the bit line A charged in vthn J is discharged through the memory cell and the potential of the bit line becomes lower than the circuit threshold of the inverter 15 of the output buffer, the memory content "L" is output. The buffer 716 is output. The RAM shown in FIG. 13 operates in exactly the same way except that the N-channel transistor 12 functions as the N-channel transistor 13 described above.

Therefore, the operating speed of such a memory is such that when the stored content of the selected memory cell is Lm, after precharging, the bit line is at the precharge voltage rVDv -Vthn.
Since it is discharged from J to the circuit threshold value vth of the inverter 15, it is limited by time.

(Problem to be Solved by the Invention) When reading the stored content "L" in the memory, conventionally the bit line A was precharged to a voltage "VDDVthnJ" near VDD, so the charge accumulated in the bit line A was After starting to discharge, the output buffer inverter 1
It took a long time for the voltage to drop to a voltage lower than the circuit threshold of No. 5. This state is shown by the broken line in FIG. Therefore, the operation speed was slow.

Therefore, an object of the present invention is to speed up the read operation of a memory.

[Structure of the invention]

(Means and effects for solving the problems) The present invention includes a bit line, an output circuit that detects the potential of the bit line and determines its logic level, a precharge voltage source, and the precharge voltage source. switch means for performing a precharge operation by transmitting a voltage from a source via a column selection transistor, and the precharge potential applied to the bit line varies from the power supply potential of the memory circuit to the threshold of the column selection transistor. It is a semiconductor memory characterized by a value lower than the value obtained by subtracting the value.

That is, the present invention increases the operating speed of the memory by setting the precharge voltage of the bit line to a voltage lower than the conventional voltage.

(Example) As mentioned above, the operating speed of a memory depends on the discharge time of the precharged voltage on the bit line, so lowering the precharge voltage on the bit line will increase the operating speed. I understand. In FIG. 1, a voltage source 31 lower than the voltage obtained by subtracting the threshold value V thn of the column selection transistor 22 from the memory power supply voltage VDD is connected as a precharge power source. If the voltage of this voltage [31 is E, then rE-Vthn J (<VD o Vthn
) is precharged to the bit line A, and the operating speed becomes faster than when the power supply voltage VDD is used as the precharge power supply.

Next, an embodiment of the present invention is shown in FIG. Here, as a substitute for the P-channel transistor 21, a CM of the power supply VDD is used.
A circuit combining an OS inverter 41 and a transmission gate 42 is used. In addition, an inverter 41 and a transmission gate 42 are connected to the CMOS inverter 43.
Feedback is provided through a circuit that combines the two. Therefore, when the transmission gate 42 is conductive, a voltage (<VDD) corresponding to the dimension ratio of the P and N transistors constituting the inverter 43 is obtained at the input of the inverter 43, and this is applied to the precharge power supply 31. It is used as a corresponding one. Due to the dimensioning of the inverter 43, the voltage on the bit line A is “Vo 0−Vthn −aJ ((2
(dropped in the feedback loop of the inverter 43), and variations in the threshold value of the inverter 15 due to processes can be offset by variations in the threshold value of the inverter 43.

Another embodiment of the invention is shown in FIG. Here, in place of the transmission gate 42 and inverter 43 which are controlled manually using signal B used in FIG. 2, an inverter 51 which receives signal B as input and a clocked inverter 52 whose clock is φ and . Feedback is applied to the clocked inverter 52, and when the clocked inverter 52 is on, a voltage ( <VDD), which is used as the precharge power supply 31 in FIG. The dimension of clocked inverter 52 allows a low voltage to be applied to the bit line as in the case of FIG.

Further, variations in the threshold value of the inverter 15 due to the process can be offset with variations in the threshold value of the inverter 52.

Next, another embodiment of the present invention is shown in FIG. In FIG. 4, power supply voltage VDD is used as a precharge power supply. In this case, a diode 61 is forwardly connected to the drain side of the conventionally used P-channel transistor 21 shown in FIG. 15 to lower the voltage. If the N-channel transistor 22 is on, the voltage rVDo VF
VthnJ can be applied to bit line A. Here, VF is the forward voltage drop of the diode 61.

Next, another embodiment of the present invention is shown in FIG. Here, instead of the diode 61 used in FIG. 4, N-channel transistors 71 to 73 are connected in series, and the gates of these transistors are connected to the drains of the respective transistors. With this circuit, r V o
A precharge power supply voltage of D-V thn -V thnVthnj can be obtained, and if the N-channel toy transistor 2 becomes conductive, rVDD is applied to the human line A.
A voltage of 4VthnJ can be applied. In this case, the number of N-channel transistors connected in series is not limited to three.

Next, another embodiment of the present invention is shown in FIG. In this circuit, a voltage of rV+:+D-Vthnj is applied to the input of the bit line using the circuit shown in FIG. 15, which has been conventionally used up to the bit line, and a diode 81 is connected to the bit line in the forward direction.

In other words, rVDv Vt is applied to the anode of the diode 81.
Applying a voltage of hnJ, fyso Fl
: A voltage of rVo D-Vthn -Vp J is obtained. Here, VF is the voltage drop of the forward connection of the diode 81. Therefore, the human line A has [Vp p
A voltage of -Vthn -VF j can be applied.

Next, another embodiment of the present invention is shown in FIG. here,
In place of the diode 81 used in FIG. 6, N-channel transistors 91, 92, and 93 are connected in series. N
The gates of channel transistors 91-93 are connected to a respective train of N-channel transistors.

Here, “V” is applied to the input of the N-channel transistor 93.
Apply a voltage of DDVthnJ to bit line A and
A voltage of thn -3Vthn J is applied. Further, in this case, the number of N-channel transistors connected in series is not limited to three.

Another embodiment is shown in FIG. Here, VDD is applied to the output of an inverter 103 by series transistors 101 and 102. Inverter 103 with feedback of CMOS inverter 103 and transmission gate 104
A voltage of "VDD-α" is obtained at the input of. This voltage is set to [Vp O-a-Vthn J via the transistor 22, and this voltage is applied to the bit line A.

FIG. 9 shows yet another embodiment, in which the transistor 11
1 to the output of the inverter 103.

Inverter 104 and transmission gate 10
A voltage of ``rVD D-α'' is obtained at the input of the inverter 103 through the feedback loop of 4. Transistor 2
2 to "VDD-(, -Vthn J"), and this is applied to the bit line A.

FIG. 10 shows yet another embodiment, in which transistor 1
Applying VDD to the input of the inverter 103 via 21,
The input of the inverter 103 is connected to rVDD D~α through the inverter 103 and the transmission gate 104, and rVDD is connected to the bit line A through the transistor 22.
-a-Vthn J.

FIG. 11 shows yet another embodiment of the invention, in which the power supply V
rVD from DD via N-channel transistor 131
o VthnJ is obtained, and it is applied to the bit line A via the N-channel transistor 22 as "VD(, -2Vthn J
You will also get Noteal.

According to each of the embodiments described above, the read speed is increased by shortening the discharge time from the precharged state of the memory bit line to the logic level "0.degree.".

FIG. 12 shows how the bit line is charged and discharged. The broken line shows the conventional example, and the solid line shows the example of the present invention.

It can be seen that when the bit line is set at a voltage of rVDo VthnJ, the discharge time becomes τ1, and according to the example of the present invention, when a voltage lower than the conventional voltage (< VDD - Vthn) is applied to the bit line, the discharge time becomes τ2, resulting in high-speed operation.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied in various ways. For example, although the potential level has been considered in the positive direction, it may also be considered in the negative direction.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to increase the read speed of the memory.

[Brief explanation of drawings]

1 to 11 show transistors 31, low voltage power supply, 41.4B of each embodiment of the present invention. 51.103... Inverter, 42,104... Transmission gate, 52... Clocked inverter, 61.81... Diode, 71~73°91
〜93...transistor, 111,121.131・
...Switching transistor, VDD...Power supply, A
...Bit line. The applicant's representative, patent attorney Takehiko Suzue, shows a detailed drawing of the same part. 11... Precharge circuit, 15... Inverter,
16...Output buffer, 21.22...Switching D Fig. Δ Fig. Δ Fig. 14

Claims (1)

[Scope of Claims] (1) A bit line, an output circuit that detects the potential of the bit line and determines its logic level, a precharge voltage source, and a series of voltages from the precharge voltage source. switch means for performing a precharge operation by transmitting the signal through the selection transistor, and the precharge potential applied to the bit line is lower than the value obtained by subtracting the threshold value of the column selection transistor from the power supply potential of the memory circuit. Semiconductor memory characterized by low performance. (2) The semiconductor memory according to claim 1, wherein the potential of the precharge voltage source is lower than the power supply potential of the memory circuit. (3) Short-circuiting a bit line, an output circuit that detects the potential of the bit line and determines its logic level, an inverter whose input terminal is connected to the bit line, and the input terminal and output terminal of this inverter. and a switch means for precharging the bit line to a value lower than a value obtained by subtracting a threshold value of a column selection transistor from a power supply potential of a memory circuit. (4) a bit line, an output circuit that detects the potential of the bit line and determines its logic level; an input terminal is connected to the bit line, and the input terminal and output terminal are short-circuited to form the bit line; and a clocked inverter that performs precharging lower than the value obtained by subtracting the threshold value of the column selection transistor from the power supply voltage of the memory circuit. (5) The semiconductor memory according to claim 3, wherein a transmission gate is used as the switch means. (6) The semiconductor memory according to claim 1, wherein the precharge voltage source includes voltage dividing means for lowering the power supply voltage of the memory circuit. (7) The semiconductor memory according to claim 6, wherein a PN junction diode is used for the voltage dividing means. (8) The semiconductor memory according to claim 6, wherein a MOS transistor is used for the voltage dividing means. (9) A bit line, an output circuit that detects the potential of the bit line and determines its logic level, a diode provided between the bit line and the output circuit, and a power supply voltage of the memory circuit connected to the diode. What is claimed is: 1. A semiconductor memory comprising switch means for performing a precharge operation by transmitting information between the output circuit and the output circuit. (10) The semiconductor memory according to claim 9, characterized in that a MOS transistor whose drain and gate are short-circuited is used instead of the diode (11) A bit line and a potential of the bit line are detected. a first P-channel transistor whose gate input is the bit line, and a second P-channel transistor whose gate input is a control signal of the P-channel transistor; A semiconductor memory, characterized in that the output of an inverter that receives a bit line as an input is connected in series between the power supply of a memory circuit, and the output of the inverter is fed back to the input of the inverter via a transmission gate. (12) A bit line, an output circuit that detects the potential of the bit line and determines its logic level, an inverter that uses the bit line as a gate input, a precharge power source that uses a control signal as a gate input, and the inverter. A semiconductor memory comprising: a P-channel transistor connected between the output of the inverter; and a circuit that feeds back the output of the inverter to the input of the inverter via a transmission gate. (13) A bit line, an output circuit that detects the potential of the bit line and determines its logic level, an inverter that receives the bit line as an input, a precharge power supply that uses a control signal as a gate input, and a precharge power supply and the inverter. A semiconductor memory comprising: a P-channel transistor connected to an input; and a circuit that feeds back the output of the inverter to the input of the inverter via a transmission gate. (14) A bit line, an output circuit that detects the potential of the bit line and determines its logic level, and a transistor of the same channel type as the column selection transistor connected between the output circuit and the precharge power supply. A semiconductor memory characterized by comprising: