JPH0447897B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an optical information reproducing device for optically reproducing information from an information recording carrier, and particularly to tracking control thereof.

Conventional Structures and Their Problems In recent years, optical video discs, compact disc players, etc. have been developed by various companies and are beginning to become popular. In these devices, video signals, audio signals, and data signals are recorded at high density on information tracks on a record carrier. Focused laser light is applied to the information tracks, and information is detected from changes in the optical properties of the reflected light. I'm reading it. Such record carriers have very high recording densities and require precise projection of a focused light spot onto the information track. Generally, in the case of the above-mentioned equipment, the distance between the track and the center of the optical spot needs to be controlled to about 0.1 μm or less, and to do this, it is necessary to be able to stably detect the relative distance error between the track and the optical spot, that is, the tracking error. It won't happen.

FIG. 1 shows a schematic diagram of a conventional optical information reproducing apparatus, which is described in Japanese Patent Application Laid-open No. 74837/1983. FIG. 2 is a signal waveform diagram of each part in FIG. 1, and FIGS. 2A to 2G show signal waveforms at points A to G in FIG. 1, respectively. In FIG. 1, an information record carrier 1 is rotated by a spindle 2. In FIG. The information record carrier 1 has a concentric or spiral information track 3 and a laser light source 4.
The light emitted from the information storage medium 1 passes through a collimator lens 5, a beam splitter 6, and a focus lens 7, and is focused on an information track 3 on the information recording carrier 1 to connect light spots. After the light spot is modulated by the information recorded on the information track 3, it passes through the focus lens 7 and the beam splitter 6 and enters the detectors 8, 9, 10, and 11 arranged in a square shape. . These detectors 8, 9, 10, 11 are arranged in the substantial far field of the image of the information track 3, one of their boundaries being parallel to the information track and the other perpendicular to it. will be placed in Therefore, four detectors 8, 9, 10,
11 is the track direction in the far field
axis, virtual X-Y with the direction perpendicular to this as the Y axis
It is placed in each quadrant of the coordinate system and outputs S ₁ , S ₂ , S ₃ , and S ₄ depending on the distribution of light.

12 and 13 are sum circuits, S ₆ = S ₂ + S ₄ , S ₅ = S ₁ +
The sum circuit ₁₄ and the difference circuit 15 calculate the sum S ₇ =S ₅ +S ₆ and the difference S ₈ =S ₆ -S ₅ of these signals, and calculate the zero crossing point of the rising or falling edge of the sum signal Sγ. is detected and the sampling pulse trains S ₉ and S ₁₀ as shown in FIG.
occurs in These sampling pulse trains
The gate circuits 18 and 19 are opened by S ₉ and S ₁₀ , and the difference signal S ₈ is sampled and held by the hold circuits 20 and 21, and the signals S _{11 and 19} as shown in FIG. 2 E and F are generated.
_S12 is produced, and the difference is taken by the difference circuit 22 to obtain a tracking error signal _S13 as shown in FIG. 2G.

The reason why the tracking error signal S ₁₃ can be obtained in this way is described in detail in JP-A-57-74887 and JP-A-52-93222, but briefly, the difference signal S ₃ has a phase shift of ±π/2 with respect to the sum signal _S7 , and whether it becomes +π/2 or -π/2 depends on whether the optical spot shifts to the left or to the right with respect to the information track. It depends on whether it shifts. The difference signal S ₈ is sampled and held at each zero-crossing point of the rise and fall of the sum signal S _7. Depending on the sign of the value, whether the phase of S ₈ with respect to S ₇ is advanced, that is, shifted to the left or shifted to the right. The amount of tracking error can be determined based on the size of the hold value.

However, in this conventional configuration, two or one sample and hold circuits are required, and the difference signal S ₈
In some cases, incorrect values were sampled due to noise components included in the sum signal _S7 , and sampling timing errors occurred due to noise components included in the sum signal S7. Furthermore, the hold error of the sample and hold circuit itself has also been a problem. moreover,
It required a hold capacitor, and when considering IC implementation, it had the disadvantage of requiring many external circuit components.

Therefore, a method has already been proposed in which the phase difference between _S5 and _S6 is detected without using a sample and hold circuit. FIG. 8 is a block diagram showing such a second conventional example. A detailed explanation of this is disclosed in Japanese Patent Application Laid-open No. 181433/1983.
I will not explain it here, but I will briefly explain the principle.
Sum circuits 12 and 13 calculate the sum of the respective outputs of the detectors arranged diagonally: S ₆ = S ₂ + S ₄ , S ₅ = S ₁ + S ₃
After shaping the waveform with bandpass filters 23, 24 and limiter circuits 25, 26, the phase comparator 27 compares the respective phases to determine whether the optical spot is on the left or right side of the information track. Discern. FIG. 4 is a waveform diagram of each part of FIG. 3.

In this conventional example, when there is a defect in the disk and the recorded information is interrupted, the output of the phase comparator 27 is either 1 or 0.
Because a large offset voltage is applied to the
The drawback was that tracking control was easily disturbed.

Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks, to provide tracking error detection suitable for IC implementation, in which tracking control is unlikely to be disturbed even if there is a defect on the information recording carrier, and a sample and hold circuit is not required. The purpose of the present invention is to provide an information reproducing device that makes it possible to reproduce information.

Structure of the Invention In order to achieve the above object, an information reproducing apparatus of the present invention includes a light emitting means for emitting a light beam, and a light beam emitted from the light emitting means to be focused on an information track of an information recording carrier. a light focusing means for forming a light spot; a light focusing means for receiving reflected light or transmitted light of the light spot from the record carrier, and arranged in a substantially far field region of the image of the information track, in the direction of the information track and orthogonal thereto; The outputs of the four light detecting means are respectively divided into four light detecting means, and S ₁ , S ₂ , S ₃ , and S ₄ are the sum of the outputs of the light detecting means arranged in the diagonal direction. ₅ = S ₁ + S ₃ , S ₆ = S ₂ + S ₄ , S ₅ , S ₆ sum and difference S ₇
= S ₅ + S ₆ , S ₈ = S ₆ −S ₅ , then S ₅ , S ₆ or
Using S ₇ and S ₈ as input signals, extracts the phase components of each of the input signals, detects when both of the input signals are higher or lower than a predetermined level, and sets the output to a level approximately halfway between the high level and the low level. The structure is equipped with phase comparison means that fixes the voltage to a potential, and enables stable tracking error detection that is suitable for IC implementation and does not require a sample-and-hold circuit.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram of the tracking error detection means of the information reproducing apparatus according to the first embodiment of the present invention, and FIG. 6 is a waveform diagram of signals at each part. The detectors 8, 9, 10, 11, sum circuits 12, 13, bandpass filters 23, 24, limiter circuits 25, 26, and phase comparator 27 are
As mentioned in the conventional example, for signal S ₅ , signal S ₆
Determine whether the phase is leading or lagging. This indicates whether the light spot is shifted to the left or right with respect to the track. NOR circuit 2
8 passes the signals S ₅ and S ₆ to bandpass filters 23 and 2.
4. The limiter circuits 25 and 26 detect when the digitized signals S ₁₄ and S ₁₅ are both at low level to obtain the signal S ₁₇ , thereby closing the gate circuit consisting of the AND circuits 29 and 30. Output of phase comparator 27
_S16 is inverted through NOT circuit 31 and
The signal is input to a gate circuit consisting of AND circuits 29 and 30. The output _S18 of the differential amplifier circuit 32 becomes a high level or low level signal according to the output of the phase comparator 27 when the gate circuit is open, but becomes a high level or low level signal when the gate circuit is closed. ( _S18 in FIG. 16 is 0). The tracking error signal obtained in this way is then generally subjected to a low-pass filter, phase compensation, and, if necessary, integral compensation, and then applied to an actuator that moves a lens, etc., to pull the light spot back onto the track. to perform tracking control. This example does not require a sample and hold circuit, so it is resistant to noise.
In addition to the advantages of no hold error and being suitable for IC implementation, it also has the advantage of not causing unnecessary offsets even if the output of each detector is interrupted due to a disk defect or the like.

Next, we will discuss in more detail the reason why unnecessary offsets do not occur. FIG. 7 is a waveform diagram showing the signals of each part when the output of each detector is interrupted due to a disk defect or the like. If the output of each detector is interrupted due to a disk defect, etc., the value obtained by digitizing each output
Both S ₁₄ ′ and S ₁₅ ′ become high level or low level. Here, a case where the level becomes low level is shown. At this time, in the tracking error detection method shown in the second conventional example, the phase comparator 27 continues to output a high-level or low-level signal even during the scratch period, depending on the phase relationship just before the input signal disappears, and the actuator As a result of giving a large error signal to the truck, the truck sometimes flew to the adjacent truck. In this embodiment, it is detected that both S ₁₄ ′ and S ₁₅ ′ have become low level, and the AND gate circuit is activated.
By closing the circuits 29 and 30, the output of the phase comparison means is fixed at a value approximately between the high level and the low level, and since no erroneous signal is output to the actuator even during the scratch period, stable tracking control is possible. be. In this example, the case where the input signals of the phase comparison means 33 are both low level is detected, but if a focus shift occurs or another type of disk defect occurs, the phase comparison means 33
Since the input signals of both become high level, it is more effective to detect this time and fix the output of the phase comparison means to a value approximately between the high level and the low level.

FIG. 8 shows the phase comparison means 33 when the input signals of the phase comparison means 33 are both high level or low level.
FIG. 3 is a configuration diagram showing another embodiment of the phase comparison means configured so that the output of No. 3 has a value approximately intermediate between a high level and a low level. When both inputs are low level, NAND gates 34, 35, 36, 37, 3
The outputs of the NAND gates 39 and 40 are all at a low level, and the output of the differential amplifier 43 outputs a value approximately between the high level and the low level, for example, 0V. Furthermore, when both inputs are at high level, the NAND gate 36
The output of the NAND gates 39 and 40 are at a low level, so the outputs of the NAND gates 39 and 40 are all at a high level, and the output of the differential amplifier 43 outputs a value approximately intermediate between a high level and a low level, for example, 0V. In addition, when the input is a combination of high level and low level, the output of the NAND gate 39 and the NOT circuit 4
1 to the NAND gate 34, the inverted output to the NAND gate 37, and the NAND gate 37, respectively.
The output of gate 40 and the inverted output through NOT circuit 42 are respectively connected to NAND gate 38,
Feedback is applied to 35, and depending on the input phase difference,
A state is created in which the NAND gate 39 is at a high level and the NAND gate 40 is at a low level, or the NAND gate 39 is at a low level and the NAND gate 40 is at a high level. At this time, the output of the differential amplifier 43 is a high level, for example 1V, and a low level, for example -1V.

FIG. 9 shows a third embodiment of the phase comparison means of the present invention, in which a switch 44 and an operational amplifier 45 are used in place of the differential amplifier 32 in the first embodiment, and when both inputs are at low level, the NOR The configuration is such that the switch 44 is opened upon detection by a gate, and the other operations are the same as in the first embodiment. When the switch 44 is closed, the output is a high level or low level signal according to the phase difference of the inputs, and when it is open, a voltage V approximately halfway between the high level and the low level is output from the non-inverting input of the operational amplifier 45. It is connected to the terminal voltage and is output as is. Other methods may be used to fix the output of the phase comparator at a voltage approximately between the high level and the low level; for example, a configuration as shown in FIG. 10 may be used. 1st
FIG. 0 shows a switch 4 in place of the differential amplifier 32 in the phase comparison means according to the first embodiment of the present invention.
6, 47, and an operational amplifier 48. When the gates of AND circuits 29 and 30 are both closed, for example, switches 46 and 47 are both open, and the output of the operational amplifier is a high level +V volt and a low level. Level 0 volts intermediate value 1/
2V volts are output.

Note that the input to the phase comparison means may be any signal whose phases are shifted from each other due to a tracking error.
For example, the signal of the difference between the sum of S ₅ and S ₆ S ₇ = S ₅ + S ₆ , S ₈ =
The same is true when using S ₆ −S ₅ . Further, the band pass filter may be simply a high pass filter or a low pass filter depending on the case, or may be omitted. Further, the limiter circuit may be a comparator. Furthermore, an analog type phase comparator may be used as the phase comparator.

Effects of the Invention As is clear from the above description, the present invention has the phase comparison means extracting the phase component of the input signal, detecting the tracking error component, and further detecting when the input signals are both higher or lower than a predetermined level. The output is fixed at a potential approximately midway between high and low levels, and does not require a sample-and-hold circuit.Therefore, it has the advantages of being resistant to noise, free of hold errors, and suitable for IC implementation. has
Furthermore, even if the output of each detector is interrupted due to a disk defect or the like, unnecessary offset voltages are not generated, making it possible to perform stable tracking control, which has a significant effect.

[Brief explanation of the drawing]

Fig. 1 is a schematic configuration diagram of a conventional optical information reproducing device, Fig. 2 is a waveform diagram of each part thereof, Fig. 3 is a block diagram of the second conventional example, and Fig. 4 is a waveform diagram of each part thereof. FIG. 5 is a block diagram in the first embodiment of the present invention, FIGS. 6 and 7 are waveform diagrams of each part thereof, and FIGS. 8, 9, and 10 are phase comparison means in different embodiments. FIG. 3... Information track, 8, 9, 10, 11...
Detector, 12, 13, 14... Sum circuit, 15...
Difference circuit, 27... Phase comparator, 32... Differential amplifier, 33... Phase comparison means, 44, 46, 47...
...Switch, 45, 48... operational amplifier.

Claims (1)

[Scope of Claims] 1. A light emitting means for emitting a light beam; a light focusing means for focusing the light beam emitted from the light emitting means onto an information track of an information record carrier to form a light spot; Four light detectors receiving reflected light or transmitted light from the record carrier in a light spot, arranged in a substantial far-field area of the image of the information track, and divided in the direction of the information track and in a direction perpendicular thereto. and the outputs of the light detection means are respectively S ₁ , S ₂ , S ₃ , S ₄ , and the sum of the outputs of the light detection means arranged diagonally.
S ₅ = S ₁ + S ₃ , S ₆ = S ₂ + S ₄ , S ₅ , the sum and difference of S ₆ as S ₇ =
When S ₅ + S ₆ , S ₈ = S ₆ − S ₅ , S ₅ , S ₆ or
Using S ₇ and S ₈ as input signals, extracts the phase components of each of the input signals, detects when both of the input signals are higher or lower than a predetermined level, and sets the output to a level approximately halfway between the high level and the low level. An information reproducing device equipped with phase comparison means that fixes the potential. 2. The phase comparison means changes the two outputs differentially according to the phase difference of the input signals, and when the input signals are both higher or lower than a predetermined level, the two output signals are both at a high level or both are at a low level. 2. The information reproducing apparatus according to claim 1, comprising a logic circuit that determines a level, and a differential amplifier circuit that takes a difference between the respective output signals. 3. The phase comparison means includes a second logic circuit that outputs an output signal that changes depending on the phase difference of the input signals, a detection circuit that detects that both of the input signals are higher or lower than a predetermined level, and the second
2. An information reproducing apparatus according to claim 1, comprising a logic circuit and a switch controlled by said detection circuit.