JPH0447828A - Header driving type switch - Google Patents

Abstract

PURPOSE:To reduce the reduction of throughput caused by the read/write of a RAM by providing a shared memory divided into plural independently operatable memory blocks, address control part, input/output line correspondence part and arbiter. CONSTITUTION:A common RAM 101 is divided into plural blocks (into two blocks in this case), and attending on the division, an arbiter 105 and an idle address memory 106 are provided at every block. In the front step of each RAM 101, a multiplexing part 109 is provided to multiplex a write data and before and behind the idle address memory 106, a selector part 108 and a distribution part 107 are provided. The imbalance of simultaneous access to the RAM between a read side and a write side caused by the difference of the state of a requirement from an input/output part to each arbiter is absorbed by the arbiter with an arbitrating function for controlling the read/write access allocation of the arbiter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides high-speed packet switching and asynchronous transfer mode (
Hereinafter, ATV, A5ynchronous
This relates to a header-driven switch that transfers a data block between arbitrary input/output lines based on connection information (header information) given to the data block in data transfer (transfer mode).

[Prior Art] Conventionally, variable link speed switches have been proposed as ATM exchanges that handle multimedia such as voice, images, data, etc., and which change the inter-switch link speed according to load conditions (for example, Hirano Value “Study of packet communication network with variable link speed” IEICE Technical Report 5E-72.198
(see 7).

Variable link speed switch uses RAM as a common buffer
This is a switch that allows you to freely assign the speed of the input and output terminals.

FIG. 2 is a block diagram of a conventional header-driven switch.

This switch has a general configuration (2
×2 switch size).

In FIG. 2, 2 is a 2×2 unit switch, 202
A, 202B is the input section, 2011:! RAM, 204A
, 204B is an output section, 205 is an arbiter for read/write control of RAM 2o1, 106 is an empty address memory, 121-1.2 is an incoming line, 122-1.2 is an outgoing line, 21
1A and B are the input section 202 from the free address memory 106.
215A and B are address sending lines from the input section 202 to the output section 2o4, 21OA and B are address sending lines from the output section 204 to the free address memory 106, and 209 is an address sending line from the input section 202 to the RAM 201. Internal data lines 213 are internal data lines from the RAM 201 to the output unit 204, 216A and B are RAM write control lines between the input unit 202 and the arbiter 205, and 217A and B are RAM read control lines between the output unit 204 and the arbiter 205. be.

First, the input units 202A and 202B input the free address memory 10.
6 through address sending lines 211A and 211B. Next, the input units 202A and 202B
When a data block is input from input line 121-1.2,
RAM write control line 216A to arbiter 205
, B to send a write request signal to the RAM. Next, the input units 202A and 202B receive data from the RAM from the arbiter 205.
Upon receiving a write permission signal to the RAM via write control lines 206A and 206B, the data block is sent to the RAM via internal data line 209 and written to a vacant address location. Next, the input units 202A and 202B input R
After writing a data block to AM201, the written RAM address is sent to one of the output sections 204A and 204B corresponding to the output line 122-1゜2 to be output based on the routing information in the data block. It is sent out via sending lines 215A and 215B. Output section 204A.

Alternatively, B selects the address to which the oldest data block has been written from the RAM addresses held within the output section. Next, the output section 204A.

B stores the data block corresponding to the selected address in R.
To read from AM, RAM read control line 217
A read request signal from the RAM is sent to the arbiter 205 via A and B.

Next, the output units 204A and 204B output the RA from the arbiter 205.
M read control line 2] When a read permission signal from the RAM is received via the 7A and 7B, the data block is read from the RAM 201, taken in via the internal data line 213, and then output to the output line +22-1.2. Send via. Next, after the output units 204A and 204B finish transmitting the data block, the used RAM addresses are transferred to the free address memory 106 via the address transmission lines 210A and 210B.
Send to.

The above is an overview of the operation of this switch. This switch uses the RAM 201 as a common buffer, and data blocks of each input/output line are transferred between the input section 202A, B, the output section 204A, B, and the free address memory 106 according to the RAM address information. Performing read/write operations to. As a result, access operations to the RAM are performed on a time-sharing basis for both input and output lines.

[Problem to be solved by the invention]

As mentioned above, in the conventional RAM type switch, R
Since AM access operations cannot be performed on multiple input/output lines simultaneously, it is necessary to perform time-sharing operations for each line.

As a result, the throughput of a RAM type switch is
The bottleneck is reading and writing to.

Therefore, in conventional RAM-type switches, if you want to improve the throughput of the switch, increase the speed of input/output lines, or increase the scale of switch terminals, it is necessary to improve the speed performance of the RAM. There was no other way but to let it happen.

The purpose of the present invention is to solve such conventional problems and improve RA
It is an object of the present invention to provide a header-driven switch that can reduce the reduction in throughput due to M read/write, reduce the RAM size, and increase the speed of the switch.

[Means to solve the problem]

In order to achieve the above object, the header-driven switch of the present invention has a shared memory divided into a plurality of memory blocks that can each operate independently, and a shared memory that manages addresses for each memory block, and each input line corresponding section. an address management unit that allocates addresses to different memory blocks, an input/output line support unit that accesses the shared memory independently when each memory block holds addresses of different memory blocks, and an input/output line support unit for each input/output A feature of the present invention is that it includes an arbiter that performs an arbitration operation so as to access the memory in a time-sharing manner when the line corresponding parts cannot hold addresses of different memory blocks and hold addresses for the same memory.

[For production]

In the present invention, the shared memory operates independently for each memory block, and the address management section manages addresses for each memory block, and for the incoming line correspondence section,
As far as possible, assign addresses to different memory blocks.

With this, it is possible to assign RAM identification numbers to each input section so as not to overlap each other, so that each input section can access the RAM at the same time. Also, in each output section, if the identification numbers of the RAMs to be read do not overlap, each output section can read out data from the RAM at the same time.

As a result, it is possible to physically divide the RAM while keeping it logically of a common RAM type, which reduces the R
Decrease in throughput due to AM read/write can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a 2×2 unit switch showing one embodiment of the present invention.

In Figure 1, it is clear that compared to the conventional Figure 2,
The common RAM 10I is divided into a plurality of pieces (in this case, 2 pieces), and an arbiter 105 and a free address memory 106 are provided for each block, and each RAM 1
A multiplexing unit 10 that multiplexes write data in the previous stage of 01
9, and a selector section 1 before and after the free address memory 106.
08 and an allocation section 107 are provided.

In FIG. 1, l is a 2×2 unit switch circuit, 101
A and B are divided RAMs, 102A and B are input parts, 1
03A and B are multiplexing units, and 104A.

B is an output section, 105A, B is an arbiter that manages read/write of RAM, 106A, B are free address memories corresponding to each RAM identification number, 107 is a distribution section, 108 is a selector section, 109A, B are multiplexing sections Cell data transmission line from section 103A,B to RAMI OIA,B, ll0A
, B is a transmission line for the RAM identification number and address from the output section 104 to the distribution section 107, IIIA, B is a transmission line for the RAM identification number and address from the selector section 108 to each input section 102A, B, 112- 1 to 112-4 are input section 1
Cell data transmission lines from 02A and B to multiplexing units 103A and B, 113-1 to 113-4 are RAM l0IA and cell data output lines from B to output unit 104A and B, 114A
, B is input cell data, 115A, B is input section 102A
, 116A-1, 2, 116B-1, 2 are the RAM between the input section 102A, B and the arbiter 105A, 8.
Write control line, 117A-1, 2, 117B-1, 2
is the RA between the output units 104A, B and the arbiters 105A, 8.
M read control line, 121-1.2 is input line, 122-
1.2 is an output line.

The free address memories 106A and 106B each contain RAMI.
Vacant addresses are held corresponding to I-specific numbers. Here, when cell data is input to both input units 102A and 102B, two free address memories 106A,
106B, the input sections 102A and 102B have different RAM identification numbers (input section #o has RAM#O1 input section #1
AM#1) and the address are sent to the input units 102A and 102B via the selector unit 108.

Here, two free address memories 106A.

If only one of the RAMs B has a free address, that is, if one of the RAMs is full, the RAM identification number and address of the free RAM are sent to the two input units 102A and 102B via the selector unit 108, respectively. Send to B.

Next, each input section 102A, B stores RAM1
A RAM write request signal is sent to the arbiters 105A and 105B according to the i-specific number via the RAM write control lines 116A-1, 2 and 116B-1 and 2. Arbiter 105
A and B are connected to the RAM write control line 116A after arbitration processing for the input units 102A and B that have received a write request.
-1,2° 106 Sends a RAM write permission signal via B-1,2. Input units 102A and 102B are arbiter 1
R from 05A and B via the RAM write control line 116.
When the AM write permission signal is received, cell data 114A and 114B are sent to the multiplexing circuits 103A and 103B in accordance with the RAM identification number according to the RAM identification number and address information given from the free address memories 106A and 106B, so that the RAM l01A , write this in B.

When writing of all cell data from the input sections 102A, B to the RAMI OIA, B is completed, the input sections 102A, B
Now, based on the routing information in the cell data, the written RAM identification number and address are transmitted via the address transmission lines 115A and 115B to the output units 104A and 104B corresponding to the output line 122-1.2 to be output. .

Next, in the output sections 104A and 104B, first, the input section 102A,
Extract the RAM identification number from the oldest RAM identification number and address information sent from B, and
A RAM read request signal is sent to the arbiter 105A, B corresponding to the different number via the RAM read control lines 117A-1, 117B-1, 117B-1, 2.

Arbiters 105A and 105B are output units 104A that receive a read request via the RAM read control line.

After the arbitration operation, a RAM read permission signal is sent to B.

In the output units 104A and 104B, an arbiter 105A.

When a RAM read permission signal is received from B, cell data is read from the corresponding RAM based on the oldest RAMm specific number and address information held, and this is sent to the outgoing line 122-
Output to 1.2.

The output units 104A and 104B output cell data to the output line 122-1.
．． 2, the RAM identification number and address are transmitted to address transmission lines 110A and 110B, and the allocated portion is transmitted to section 107.

The distribution section 107 distributes the addresses returned from the output sections 104A and 104B to the free address memories 106A and 106B corresponding to the RAMff1 separate numbers that were returned at the same time and sends them out. Note that the arbiters 105A and 105B perform arbitration operations for RAM write and read request signals from all input/output units.

In the above embodiment, the case where the switch size is 2×2 and the number of RAMs is 2 was explained, but in the present invention, the switch size is NXN (N is a natural number of 2 or more) and the number of RAMs is A similar operation is possible for natural numbers. In this case, the selector unit 108 cyclically checks whether there are any free addresses in the O- free address memory. As a result, when a free address is detected,
These vacant addresses are sequentially sent to the input section requesting an address among the O-N input sections.

By operating in this way, the addresses of different RAM identification numbers can be held in the N input sections, so that an NXN switch can also be easily configured.

Next, the operation of the switch shown in FIG. 1 will be explained in detail while comparing it with the operation of a conventional RAM type switch.

FIG. 3(a) is an operational diagram of a conventional RAM type switch, and FIG. 3(b) is an operational diagram of a switch using the present invention.

In FIG. 3(a), 202A-1, 202B-1 are RAM write address holding memories, 209-1.
2 is the cell data write route to RAM, 201-1
．． 3 is a data area of RAM in which cell data is written, 201-2.4 is a data area of RAM for reading by output units 204A and 204B, 204A-1, 204B-1
is a memory that holds read addresses from RAM, 213
-1.2 is the read route from the RAM to the output section.

In FIG. 3(b), 10IA-2 and 101B-1 are data areas 10 and 10 of the RAM where cell data is written.
2A-1, 10IB-2 are RAM data areas to be read, 102A-1, 102B-1 are RAM to write.
112; memory for holding RAMQ-specific numbers and addresses;
A-1, 112B-1 is a RAM cell data write route, 104A-1, 104B-1 is a memory that holds the RAM identification number and address of the RAM to be read, 11
3-IA and 113-4A are read routes from the RAM.

First, the operation of a conventional RAM type switch will be described using FIG. 3(a).

Input units 202A and 202B each receive free addresses (addresses #0 and #5) in free address memory IO6, and write them into RAM 201 according to the received addresses. Here, since cells are input to the two input sections 202A and B, the two input sections 202A and B simultaneously send a write request signal to the RAM to the arbiter 205.
It is sent via write control lines 206A and 206B.

Since the arbiter 205 receives the request signals at the same time, the arbiter 205 notifies each input unit 202A, B of a write permission signal via the RAM write control lines 216A, B through an arbitration operation.

Next, when each of the input sections 202A and 202B receives a write permission signal from the arbiter 2.5, the cells of the input section 202A are transferred to the RAM 201-1 via the route 209-1, and the cells of the input section 202B are RAM20 at the root of 209-2
Written in 1-3.

In this manner, when writing to the RAM, cell data on two incoming lines must be multiplexed to be written alternately in a time-division manner. Also, even when two output units simultaneously send output requests from RAM,
Likewise, they cannot be read from RAM at the same time.

This causes a reduction in the throughput of the RAM type switch, and is a bottleneck in increasing the speed.

Next, the operation of the switch of the present invention will be described in detail using FIG. 3(b).

In the switch of the present invention, the free address memory 106A,
In B, free addresses are managed by RAM identification number. For example, in the free space memory areas 106A and 106B,
Address #5 and address #0 are held in each of the addresses. When address #5 is given to each input section 102A in RAM#O, and address #0 is given to input section 102B in RAM#1, the arbiters 105A and 105B for each RAM1i number are as follows.
Since write permission signals can be sent to the input units 102A and 102B independently, the cell data on the incoming line 121-1 is routed through the input line 112A-1, according to each held address.
Further, the cell data of the human power 121-2 can be simultaneously written into the RAM through the route 112B-1.

Furthermore, if the output units 104A and 104B hold addresses with different RAM identification numbers, for example, the output unit 1
When the RAM identification number #O and address #O are held in 04A and the identification number #address #5 is held in the output unit 104B, the read permission signal from the RAM can be received independently from the arbiter. Therefore, reading can be performed using separate routes. That is, cell data 101A- at address #O in RAMgO
1] ] 3A-IA route, cell data l○IB-2 at address #6 in RAMRI is read out from the RAM at the same time through the route 113-4B.

In this way, the two input sections 102A and 102B have different RAs.
If the M identification number and RAM address are held, it is possible to write to RAM at the same time. Also, two output units 104A.

If different RAM11 numbers and RAM addresses are held in B, they can be read from the RAM at the same time.

Here, due to the difference in the request state from the input/output unit to each arbiter, an imbalance occurs in simultaneous access to the RAM on the read side and the write side, but in the switch of the present invention, the read/write access allocation of the arbiter is adjusted. The arbitration function allows the arbiter to absorb this imbalance.

FIG. 4 (a-1 to a-2) is a diagram of a conventional RAM type switch, and FIG. 4 (b-1 to b-10) is a diagram of a switch using the present invention. a-1, 2) are shown in Figure 3 (a-1, 2).
) has the same configuration as Further, FIG. 4(b-1, 2) shows the switch of the present invention, where all the input sections and all the output sections request access to different RAMs, and the conditions are the same as in FIG. 3(b). Figure 4 (b-3, 4) shows that when all input/output units request access to the same RAM (10), Figure 4 (b-3, 4)
b-5, 6), all input parts are in RAM80, all output parts are in R
When an access request is made to AM#1,
), all inputs are in different RAMs and all outputs are in the same RAM.
When an access request is made to M#O, Fig. 4 (b-9, 1
0) indicates the access allocation of each arbiter when all input sections request access to the same RAM #O and all output sections request access to different RAMs.

In both cases, the arbiter's read/write access allocation is compared when an access request is made only once from all input/output units to each one-word cell at the same time. Note that the same reference numerals as in FIGS. 1 and 2 represent the same parts.

In Figure 4 (a-1, 2) (b-1 to 10), 40
1 to 404 are cell data (A, B, C, D), 405 to
428 is a cell data transmission route, 430 to 453 are lines indicating access requests to the arbiter, and 4-■ to 4-■ are diagrams indicating read/write access allocation of the arbiter.

In addition, in FIG. 4, one cell is one word, and the RAM is
Access is performed word by word, with write priority.

First, in FIG. 4 (a-1, 2) (pattern ■), the input section 202A has a cell A (405), the input section 202Bi: SE, IL, B (406) is held, and the arbiter 205 has a cell A (405). A write request signal to the RAM is outputted through routes 431 and 431, respectively.

Also, in the RAM, cell C (407), cell D (40
8) is held and output from the output section 204A to the cell C1 output section 2.
In order to read cells D from 04B, output request signals from the RAM are sent to the arbiter 205 via routes 432 and 433. Therefore, the arbiter's read/write access allocation is based on the write timing from the input section 202A, as shown in 4-■ in FIG. 4(a-2).
Read timing from output section 204A, input section 202
Write timing from B and read timing from output section 204B are assigned, and four timings are always required.Next, in Fig. 4 (b-1, 2) (pattern ■), each input section 102A , B output write request signals to the RAM to the arbiter 105A and the cell B to the arbiter 105B through routes 434 and 435, respectively. Moreover, each output section 104A.

In B, the output section 104A is the cell C1 output section 104.
B reads each cell D, but the cells to be read are stored in different RAMs@RAMs with different numbers. Therefore, the output section 104A sends the output section 1 to the arbiter 105A.
04B outputs a read request signal from the RAM to arbiter 1.54B via routes 436 and 437, respectively. In this case, the arbiter's read/write access allocation requires a total of two timings, as shown by 4-■ in FIG. 4(b-2).

Next, in FIG. 4 (b-3, 4) (pattern ■), since all input/output units request access to the same RAM#O,
In this case, there is no advantage even if the arbiter is divided. In this case, a total of four timings are required, as shown in 4-■ in FIG. 4(b-4).

Next, in Figure 4 (b-5, 6) (pattern ■), all input sections request access to RAM#O, and all output sections request access to RAM#1, so the arbiter has access requests for input and output. The advantages are realized by dividing the In this case, Fig. 4 (b
As shown in 4-■ of -6), two write timings are required on the arbiter #0 side and two read timings are required on the arbiter #1 side, but since the arbiter can operate independently, the total number of times is 2. The timing is fine.

Next, in FIG. 4 (b-7, 8) (pattern ■), all input sections request access to different RAMs, and all output sections request access to the same RAM #O. In this case, Fig. 4 (b-
As shown in 8) 4-■, on the arbiter #O side, there are two read timings and one write timing, a total of three times.
On the arbiter #1 side, only one write timing is required, resulting in a total of three timings.

Finally, in Figure 4 (b-9, 10) (pattern ■),
All inputs are in the same RAM#O, all outputs are different in RA
Requesting access to M. In this case, Figure 4 (
As shown in 4-■ of b-10), the arbiter #0 side requires two write timings and one read timing, a total of three times, while the arbiter #l side requires only one read timing. , a total of three timings are required.

In this way, when the number of divisions is 2 in the 2×2 switch using the present invention, the arbiter will have to allocate read/write access a maximum of 4 times and a minimum of 2 times. Compared to a RAM type switch, RAM can be read and written more efficiently.

Note that when the same RAM identification number is held in each input/output unit, data is written to or read from the RAM alternately in a time-sharing manner, as in the conventional RAM type switch. However, by increasing the number of RAM divisions, this frequency can be reduced, and in most cases, each input/output section can hold an address with a different RAM identification number, and write to or read from RAM at the same time. Is possible. For this reason, in actual design, the number of divisions is determined by taking into account improvements in throughput and increases in the amount of hardware.

In this manner, in the present invention, since RAM identification numbers can be given to each input section so as not to overlap with each other, each input section can access the RAM at the same time. Similarly, R to be read at each output section
Since the AM identification numbers can be different, each output can be read from the RAM at the same time. In addition, R
Since the AM can be divided into multiple parts, the size of the RAM can be reduced and the capacity can be reduced. As a result, it becomes easier to achieve the required speed performance of the RAM, which is advantageous in realizing higher speed and larger capacity of the switch.

〔Effect of the invention〕

As explained above, according to the present invention, logically common R
Since the RAM can be physically divided while remaining an AM type switch, it is possible to reduce the decrease in throughput due to RAM read/write compared to a conventional RAM type switch.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a 2×2 unit switch showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional RAM type switch, and FIG. 3 shows the operation of the switch of the present invention in a conventional RAM type switch.
FIG. 4 shows the detailed operation of the switch of the present invention, and is a comparison diagram of the read/write access allocation of the arbiter with the conventional one. 101A, B, 201: RAM, 102A, B. 202A, B: Input section, 104A, B, 202A. B: Output section, ] 05A, B, 205: 7-vita, 1
06A, B, 106: Free address memory, 107.
The distribution is as follows: 1o8: Selector section, 103A, B: Multiplexing section, 114A, B: Cell, 109A, B: Se/L
, data transmission line, +10A, B: RAM identification number and address transmission line, IIIA, B: RAM identification number and address transmission line, 112-1 to 112-4: Cell data transmission line, 113-1 to 113 -4 +Cell data output line. Figure (Part 3) (b-1) 0LA 105 to 3 Figure (Part 4) (b-2) Arbiter read/write access allocation time pattern ■ Switch using the present invention (115) Figure (Part 5) (b-3) Horizontal diagram (Part 7) Figure (Part 8) (b-6) Arbiter read/write access allocation time pattern ■ Switch using the present invention (315) Figure (Part 9) ( b-7) Figure (Part 10) (b-8) Arbiter read/write access allocation - 1111 time pattern■ Switch using the present invention (415) Figure (Part 1) (b-9) (b-10) Arbitana O Arbitana 1 Pattern ■ Monthly diagram of the present invention (Part 12) Read/Write access allocation 11111 hours] switch (515)

Claims (1)

[Claims] (1) The incoming line handling unit receives the address information of the shared memory from the address management unit, writes a data block having the output destination line identification information input from the incoming line in the header to the shared memory according to the address information, and after the writing is completed. , by sending the address information to the outgoing line corresponding unit according to the output destination line identification information, the outgoing line corresponding unit reads the data block from the shared memory according to the address information, outputs it to the outgoing line, and also outputs the data block to the outgoing line, A header-driven switch that returns information to the address management section includes a shared memory divided into a plurality of memory blocks that can each operate independently, and a shared memory that manages addresses for each memory block and corresponds to each input line. an address management section that allocates addresses to different memory blocks for each section; an input/output line corresponding section that accesses the shared memory independently when each section holds addresses of different memory blocks; When the input/output line correspondence section cannot hold addresses of different memory blocks and holds addresses for the same memory,
A header-driven switch comprising: an arbiter that performs an arbitration operation so as to access the memory in a time-sharing manner.