JPH0447282A - Storage battery measuring circuit - Google Patents
Storage battery measuring circuitInfo
- Publication number
- JPH0447282A JPH0447282A JP2156220A JP15622090A JPH0447282A JP H0447282 A JPH0447282 A JP H0447282A JP 2156220 A JP2156220 A JP 2156220A JP 15622090 A JP15622090 A JP 15622090A JP H0447282 A JPH0447282 A JP H0447282A
- Authority
- JP
- Japan
- Prior art keywords
- contacts
- group
- relays
- storage batteries
- storage battery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Tests Of Electric Status Of Batteries (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は蓄電池測定回路に関するもので・さらに詳しく
言えば多数の直列接続された蓄電池の４１ｖ電圧を測定
する蓄電池測定回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an accumulator measuring circuit, and more particularly to an accumulator measuring circuit for measuring the 41V voltage of a large number of series-connected accumulators.
従来の技術
大型のｃｖｃｙｔ源装置などでは、数百上ｙの蓄電池が
直列に接続されたものがあり、このよ゛うな装置に備え
られる蓄電池のセＩ％／を圧を測定する測定回路として
は第２図のようなものが知られている０すなわち、第２
図において、直列接続されたｎ−ｔμの蓄電池１−１〜
１−ｎの各々にリレーの接点ＲＹ１−１〜ＲＹ１−ｎが
接続され、オンさせたリレーの接点ｔこ接続された蓄電
池のセル電圧が測定され、その測定電圧がム／Ｄ変換器
２によってディジタμ変換されてＣＰＵ３に入力され、
そのデータはメモリ回路４に送出されて記憶させたり、
表示器５に送出されて表示させたりする。一方、このＣ
ＰＵ５からはラインデコーダ乙に信号が送出され、この
ラインデコーダ６から前記リレーの接点ＲＹ１−１〜Ｒ
Ｙ１−ｎＩｃ対応したりレーコイ＊ＲＣ１−１〜Ｒｃ１
−ｎを励磁する信号が送出されて該リレーの接点ｎｙ１
−１〜ＲＹ１−ｎをオンさせるように構成されている。Conventional technology Some large CVCYT source devices have several hundred or more storage batteries connected in series, and the measurement circuit for measuring the pressure of the storage batteries provided in such devices is as follows. 0, that is, the second
In the figure, series-connected n-tμ storage batteries 1-1 to
Relay contacts RY1-1 to RY1-n are connected to each of 1-n, and when the relay contacts are turned on, the cell voltage of the connected storage battery is measured, and the measured voltage is transmitted by the Mu/D converter 2. Digital μ converted and input to CPU3,
The data is sent to the memory circuit 4 and stored,
It is sent to the display device 5 and displayed. On the other hand, this C
A signal is sent from the PU5 to the line decoder B, and from this line decoder 6, the relay contacts RY1-1 to R
Y1-nIc compatible or Rekoi *RC1-1~Rc1
-n is sent to contact ny1 of the relay.
-1 to RY1-n are turned on.
発明が解決しようとする課題
上記のような蓄電池測定回路では、多数の蓄電池が直列
に接続されていると、リレーの接点ＲＹ１−１〜ＲＹｊ
−ｎの耐圧を大きくする必要があり、回路が大型になっ
て高延になるという欠点があった。Problems to be Solved by the Invention In the storage battery measuring circuit as described above, when a large number of storage batteries are connected in series, the relay contacts RY1-1 to RYj
It is necessary to increase the withstand voltage of -n, which has the disadvantage that the circuit becomes large and expensive.
課題を解決するための手段
上記欠点を解決するため、本発明の蓄電池測定回路は、
直列接続された各々の蓄電池から第１群のリレーの接点
を介して該蓄電池のセル電圧が入力されるＩＩ数のトラ
ンスデユーサと、該トランスデユーサに入力されたセル
電圧をディジタル変換するム／Ｄ変換器と、このディジ
タル変換された信号が入力されるＣＰＵとを有し、この
ＣＰＵに入力されたデータを記憶または表示させるとと
もに、前記ム／Ｄ変換器と前記複数のトランスデユーサ
の各々との間にｗｇ２群のリレーの接点を介挿し、前記
第１群のリレーの接点のオン、オフを制御するりレーコ
イμを備えた第１のラインデコーダと、前記第２群のリ
レーの接点のオン、オフを制御するリレーコイルを備え
た第２のラインデコーダとを設け、前記ＣＰＵから送出
される信号によって前記第１群のリレーの接点と第２群
のリレーの接点とを制御して蓄電池のセル電圧を測定す
るものであるＯ
作用
ム／Ｄ変換器と蓄電池の七μとの間に複数のトランスデ
ユーサを設けて蓄電池をこのトランスデユーサと同数の
ブロックに分け、ＣＰＵかも送出される信号によって各
ブロックごとにセル電圧が測定できる構成にしているの
で、各グロ、り内の第１群のリレーの接点の耐圧を低下
させることができる。Means for Solving the Problems In order to solve the above drawbacks, the storage battery measuring circuit of the present invention has the following features:
II number of transducers to which the cell voltage of each storage battery connected in series is inputted through the contacts of the first group of relays, and a module for digitally converting the cell voltage inputted to the transducer. A/D converter and a CPU to which the digitally converted signal is input, and the CPU stores or displays the data input to the CPU. A first line decoder equipped with a relay μ and a first line decoder having relay contacts of the second group and controlling the ON/OFF state of the contacts of the first group of relays are inserted between the WG and the second group of relays. A second line decoder equipped with a relay coil for controlling on/off of the contacts is provided, and the contacts of the first group of relays and the contacts of the second group of relays are controlled by signals sent from the CPU. A plurality of transducers are installed between the O action MU/D converter and the 7μ of the storage battery, and the storage battery is divided into the same number of blocks as the transducers. Since the structure is such that the cell voltage can be measured for each block based on the signal sent out, it is possible to reduce the withstand voltage of the contacts of the first group of relays in each group.
実施例
以下、実施例により説明する。第１図は本発明の蓄電池
測定回路のグロ、り図で、第２図と同じ機能を有する部
分には同じ符号を付している。第１図において、蓄電池
１−１〜１−ｎのセル電圧が入力される複数のトランス
デユーサは７−１．７−２で、トランスデユーサ７−１
にはｍ個の蓄電池１−１〜１−ｍ＊（ｍ＜ｎ）のセル電
圧が入力され、トランスデユーサ７−２には（ｎ−ｍ）
個の蓄電池１−（ＥＩ＋＋１）〜１−ｎのセル電圧が入
力されるように構成されている。EXAMPLE The following is an explanation using examples. FIG. 1 is a schematic diagram of a storage battery measuring circuit according to the present invention, in which parts having the same functions as those in FIG. 2 are given the same reference numerals. In FIG. 1, a plurality of transducers to which cell voltages of storage batteries 1-1 to 1-n are input are 7-1, 7-2, and transducer 7-1.
The cell voltages of m storage batteries 1-1 to 1-m* (m<n) are input to the transducer 7-2, and (n-m) is input to the transducer 7-2.
It is configured such that the cell voltages of storage batteries 1-(EI++1) to 1-n are input.
すなわち、前記トランスデユーサ７−１．７−２により
ｎ個の蓄電池１−１〜ｊ−ｎは２つのブロックに分けら
れ、蓄電池１−１〜１−ｍとトランスデユーサ７−１と
の間には第１群のリレーの接点ＲＹ１−１〜ＲＹ１−ｍ
が介挿され、蓄電池１−（ｍ＋１）〜１−ｎとトランス
デユーサ７−２との間ｔこは他の第１群のｙｖ−の接点
ＲＹ１−（ｍ＋１ ）〜ＲＹ１−ｎが介挿されている。That is, the n storage batteries 1-1 to j-n are divided into two blocks by the transducer 7-1, 7-2, and the storage batteries 1-1 to 1-m and the transducer 7-1 are divided into two blocks. Between them are the contacts RY1-1 to RY1-m of the first group of relays.
are inserted, and other first group yv- contacts RY1-(m+1) to RY1-n are inserted between the storage batteries 1-(m+1) to 1-n and the transducer 7-2. has been done.
そして・前記トランスデユーサ７−１とム７句変換器２
との間には第２群のリレーの接点ＲＹ２−１が介挿され
、前記トヲンスデュ−？７−２とム／Ｄ変換器２との開
には他の第２群のリレーの接点Ｒｙ２−２が介挿されて
いる。このム／Ｄ゛変換器２ｒ−よってディジタル変換
された蓄電池１−１〜１−ｎのセル電圧は０ＰＵ３に入
力され、該ｃｐｕｓからメモリー回路４に送出して記憶
させたり、表示器５に送出して表示させたりする。and the transducer 7-1 and the transducer 2
A contact point RY2-1 of the second group of relays is inserted between the two and A contact Ry2-2 of another second group of relays is inserted between the contact point 7-2 and the Mu/D converter 2. The cell voltages of the storage batteries 1-1 to 1-n, which have been digitally converted by the system/D converter 2r-, are input to the 0PU3, and are sent from the CPU to the memory circuit 4 for storage, or are sent to the display 5. and display it.
一方、このＣＰＵ３からは、第１のラインデコーダ６−
１に信号が送出されて前記第１群のリレーの接点Ｒｙ１
−１〜ＲＹ１−ｎ−μ対応するりレーコイ／Ｉ／ＲＯ１
−１〜ＲＣ１−Ｈが励磁され、そのオン、オフが制御さ
れるとともに、第２のラインデコーダ６−２に信号が送
出されて前記第２群のリレーの接点ＲＹ２−１ ＋ Ｒ
Ｙ２−２に対応するりレーコイＡｚＲＣ２−１、ＲＣ２
−２が励磁され、そのオン、オフが制御される。すなわ
ち、第２のラインデコーダ６−２によって第２群のりし
−の接点ｎｙ２−１をオンさせた場合には、第１群のリ
レーの接点ＲＹ１−１〜Ｒｙ１−Ｉｎに接続された蓄電
池１−１〜１−ｍのセル電圧が順次測定され、第２のラ
インデコーダ６−２によって他の第２群のリレーの接点
ｕｙ２−２をオンさせた場合には、他の第１群のリレー
の接点ＲＹｊ−（ｍ−Ｎ） 〜ＲＹ１−ｎに接続された
蓄電池１−（ｍ＋１）〜１−ｎのセル電圧が順次測定さ
れる。On the other hand, from this CPU 3, a first line decoder 6-
A signal is sent to contact Ry1 of the first group of relays.
-1~RY1-n-μ corresponding Rikoi/I/RO1
-1 to RC1-H are excited and their ON/OFF states are controlled, and a signal is sent to the second line decoder 6-2 to connect the contacts RY2-1 + R of the second group of relays.
Rikoi AzRC2-1, RC2 corresponding to Y2-2
-2 is excited and its on/off is controlled. That is, when the second line decoder 6-2 turns on the contact ny2-1 of the second group of relays, the storage battery 1 connected to the contacts RY1-1 to Ry1-In of the first group of relays turns on. -1 to 1-m are sequentially measured, and when the second line decoder 6-2 turns on the contact uy2-2 of the other second group relay, the other first group relay Cell voltages of storage batteries 1-(m+1) to 1-n connected to contacts RYj-(m-N) to RY1-n are sequentially measured.
従って、蓄電池１−１〜１−ｎを、第１群のリレーの接
点ｕｙ１−１〜ＲＹ１−ｎがその耐圧より低くなるよう
な複数のブロックに分け、該ブロックと同数のトランス
デユーサを設けるように構成しているから、第１群のリ
レーの接点ＲＹ１−１〜ＲＹ１−ｎやそれに対応するリ
レーコイｆｉ／ＲＣ１−１〜ｕｃ１−ｎが大型化するこ
とを防止できる。Therefore, the storage batteries 1-1 to 1-n are divided into a plurality of blocks such that the contacts uy1-1 to RY1-n of the first group of relays are lower than their withstand voltage, and the same number of transducers as the blocks are provided. With this configuration, it is possible to prevent the contacts RY1-1 to RY1-n of the first group of relays and the corresponding relay coils fi/RC1-1 to uc1-n from increasing in size.
発明の効果
実施例において詳述した如（、本発明の蓄電池測定回路
は蓄電池のセル電圧を測定するためのリレーの耐圧を低
くすることができるので、回路を小型化することができ
、しかも高価になることを防止できる。Effects of the Invention As described in detail in the embodiments, the storage battery measuring circuit of the present invention can lower the withstand voltage of the relay for measuring the cell voltage of the storage battery, so the circuit can be made smaller and less expensive. can be prevented from becoming
第１図は本発明の蓄電池測定回路のブロック図、第２図
は従来の蓄電池測定回路のブロック図である。FIG. 1 is a block diagram of a storage battery measuring circuit according to the present invention, and FIG. 2 is a block diagram of a conventional storage battery measuring circuit.
Claims (1)
を介して該蓄電池のセル電圧が入力される複数のトラン
スデューサと、該トランスデューサに入力されたセル電
圧をディジタル変換するＡ／Ｄ変換器と、このデイジタ
ル変換された信号が入力されるＣＰＵとを有し、このＣ
ＰＵに入力されたデータを記憶または表示させるととも
に、前記Ａ／Ｄ変換器と前記複数のトランスデューサの
各々との間に第２群のリレーの接点を介挿し、前記第１
群のリレーの接点のオン、オフを制御するリレーコイル
を備えた第１のラインデコーダと、前記第２群のリレー
の接点のオン、オフを制御するリレーコイルを備えた第
２のラインデコーダとを設け、前記ＣＰＵから送出され
る信号によって前記第１群のリレーの接点と第２群のリ
レーの接点とを制御して蓄電池のセル電圧を測定するこ
とを特徴とする蓄電池測定回路。a plurality of transducers into which the cell voltages of the storage batteries are input from each of the storage batteries connected in series through the contacts of the first group of relays; and an A/D converter which digitally converts the cell voltages input to the transducers. , and a CPU to which this digitally converted signal is input.
The input data is stored or displayed in the PU, and contacts of a second group of relays are inserted between the A/D converter and each of the plurality of transducers, and the first
a first line decoder equipped with a relay coil that controls ON/OFF of the contacts of the group of relays; and a second line decoder equipped with a relay coil that controls ON/OFF of the contacts of the second group of relays; A storage battery measuring circuit comprising: a storage battery measuring circuit that measures a cell voltage of a storage battery by controlling contacts of the first group of relays and contacts of the second group of relays in accordance with a signal sent from the CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2156220A JP2576267B2 (en) | 1990-06-14 | 1990-06-14 | Battery measurement circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2156220A JP2576267B2 (en) | 1990-06-14 | 1990-06-14 | Battery measurement circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0447282A true JPH0447282A (en) | 1992-02-17 |
| JP2576267B2 JP2576267B2 (en) | 1997-01-29 |
Family
ID=15622984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2156220A Expired - Fee Related JP2576267B2 (en) | 1990-06-14 | 1990-06-14 | Battery measurement circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2576267B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705929A (en) * | 1995-05-23 | 1998-01-06 | Fibercorp. Inc. | Battery capacity monitoring system |
| JP2001305199A (en) * | 2000-04-20 | 2001-10-31 | Matsushita Electric Ind Co Ltd | Voltage detection circuit |
-
1990
- 1990-06-14 JP JP2156220A patent/JP2576267B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5705929A (en) * | 1995-05-23 | 1998-01-06 | Fibercorp. Inc. | Battery capacity monitoring system |
| JP2001305199A (en) * | 2000-04-20 | 2001-10-31 | Matsushita Electric Ind Co Ltd | Voltage detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2576267B2 (en) | 1997-01-29 |
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