JPH0446542U - - Google Patents
Info
- Publication number
- JPH0446542U JPH0446542U JP1990087943U JP8794390U JPH0446542U JP H0446542 U JPH0446542 U JP H0446542U JP 1990087943 U JP1990087943 U JP 1990087943U JP 8794390 U JP8794390 U JP 8794390U JP H0446542 U JPH0446542 U JP H0446542U
- Authority
- JP
- Japan
- Prior art keywords
- bump
- height
- semiconductor device
- insulating pillow
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990087943U JPH0446542U (US20070244113A1-20071018-C00169.png) | 1990-08-24 | 1990-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990087943U JPH0446542U (US20070244113A1-20071018-C00169.png) | 1990-08-24 | 1990-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0446542U true JPH0446542U (US20070244113A1-20071018-C00169.png) | 1992-04-21 |
Family
ID=31820742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990087943U Pending JPH0446542U (US20070244113A1-20071018-C00169.png) | 1990-08-24 | 1990-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0446542U (US20070244113A1-20071018-C00169.png) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303314A (ja) * | 2004-04-14 | 2005-10-27 | Samsung Electronics Co Ltd | バンプ構造を含む半導体素子及びその製造方法 |
-
1990
- 1990-08-24 JP JP1990087943U patent/JPH0446542U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005303314A (ja) * | 2004-04-14 | 2005-10-27 | Samsung Electronics Co Ltd | バンプ構造を含む半導体素子及びその製造方法 |
