JPH0445570A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent the breaking of electrode wiring by equipping it with a memory capacitor, which comprises an accumulating electrode, a dielectric film covering it, and an opposite electrode covering this dielectric film, and further thinning the insulating film at the part to form an electrode contact window. CONSTITUTION:This is equipped with a memory capacitor, which comprises a transfer transistor, an accumulating electrode 30 extending on this transfer transistor and contacting with an n<+>-type source region 25 or an n<+>-type drain region 26, a memory capacitor dielectric film 29 covering this accumulating electrode, and an opposite electrode 30 covering this, and further the thickness of the insulating film 31 and 33 formed on the opposite electrode 30 are made thicker than that of the insulating film 33 at the side. Thereupon, the electrode contact window for bringing the word line being the gate electrode of the transfer transistor into contact with the metallic electrode wiring can be made thin, so the breaking of the electrode wiring can be lessened.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor memory device having a structure that requires a shallow electrode contact window when bringing out lower layer electrodes/wirings to the surface, and a method for manufacturing the same, without increasing parasitic capacitance of bit lines. , the insulating film in the area where the electrode contact window is formed can be made thinner,
In order to prevent disconnection of electrodes and wiring, a transfer transistor, a storage electrode extending over the transfer transistor and in contact with the source or drain, a dielectric film covering the storage electrode, and a counter electrode covering the dielectric film are provided. The memory capacitor is configured such that the thickness of the insulating film formed on the upper surface of the counter electrode is thicker than the thickness of the insulating film similarly formed on the side surface.

[Industrial Field of Application] The present invention relates to a semiconductor memory device having a structure in which a shallow electrode contact window is required when lower-layer electrodes and wiring are brought out to the surface, and a method for manufacturing the same.

Currently, there is a strong demand for miniaturization, especially for semiconductor memory devices. Therefore, it is natural that the area of the contact window must be made small.However, in dynamic random access memories that use stacked capacitors as memory capacitors, wiring and glabellar insulating films are multilayered. When an electrode contact window like the one described above is formed, it becomes deep and the coverage deteriorates at the connection part between the lower layer electrode/wiring and the surface side electrode/wiring, so this problem can be solved. Have to,
The reliability of the semiconductor memory device cannot be improved.

[Prior Art] FIG. 13 shows a dynamic random access memory (dyn) having a conventional stacked memory capacitor.
amic random access mem
FIG. 2 shows a cutaway side view of essential parts for explaining the DRAM.

In the figure, 1 is a P-type silicon (St) semiconductor substrate, 2
3 is a field insulating film for element isolation made of silicon dioxide (SiO□); 3 is a gate insulating film made of Stow; 4 is a gate insulating film made of Stow;
5 is the word line which is the gate electrode made of polycrystalline Si in the transfer gate transistor, 5 is the n-type source region in the transfer gate transistor, and 6 is the n-type source region in the transfer gate transistor. ° type drain region, 7 is an insulating film made of 5iOz, 8 is a storage electrode made of polycrystalline Si in the memory capacitor, 9 is a Sin covering the surface of the storage electrode 8,
10 is a counter electrode made of polycrystalline Si in the memory capacitor; 11 is a Si
12 is a bit line made of polycrystalline Si, 13 is a phosphosilicate glass (phospho-silicate)
14 indicates an insulating film made of PSG), and an electrode/wiring made of aluminum (A).

In this semiconductor memory device, a bit line 12 is connected to a source region 5 of a transfer gate transistor, and a storage electrode 8, a dielectric film 9, and a counter electrode 10 constitute a memory capacitor. transfer·
It is connected to the drain region 6 of the gate transistor.

Further, the word line 4 made of polycrystalline St is connected to the electrode/wiring 14 made of A1 at the end of the cell array.

FIG. 14 shows a cutaway side view of essential parts for explaining the connection structure between the word line 4 and the electrode/wiring 14 at the end of the cell array, and the same symbols as those used in FIG. 13 are used. shall represent the same part or have the same meaning.

With this configuration, the resistance value of the word line 4 made of polycrystalline Si is substantially reduced.

Figure 15 is a DR diagram explaining Figures 13 and 14.
This shows an equivalent circuit diagram of the main part of AM, and the same symbols as those used in FIGS. 13 and 14 represent the same parts or have the same meaning.

In the figure, -Q indicates a transfer gate transistor, and MC indicates a memory capacitor.

[Problem to be solved by the invention]

In the DRAM explained with reference to FIGS. 13 to 15, the word line 4 made of polycrystalline Si and the electrode made of A1.
The depth of the electrode contact window for connecting with the wiring 14 is as follows: Thickness of insulating film 7: ~1500 (people) Thickness of capacitor dielectric film 9: 2 to 100 [people] Insulating film 1
Thickness of insulating film 13: ~2500 C] Thickness of insulating film 13: ~5
000 (people), so the total is ~9000 (
person] amount.

Here, if the diameter of the electrode contact window for connecting the word line 4 and the electrode/wiring 14 is set to 0.8 [μm], the aspect ratio (depth/diameter) is about 1.1, which means There is a risk that the connecting portion of the electrode/wiring 14 made of 〇 will not fit tightly into the electrode contact window and may be disconnected. It has been found that the frequency of occurrence of this disconnection increases rapidly when the aspect ratio of the electrode contact window exceeds 1.0.

By the way, in order to keep the aspect ratio of the electrode contact window low, it may be thought that it is enough to make the various insulating films thinner, but the problem is not that simple. In other words, when the insulating films are made thinner, the dielectric strength voltage decreases or Problems such as an increase in parasitic capacitance inevitably occur, and in particular, when the insulating film 11 is made thinner, the parasitic capacitance of the bit line 12 increases, which directly affects the reduction in DRAM operating speed and operating stability.

The present invention does not increase the parasitic capacitance of the bit line.
The insulating film in the area where the electrode contact window will be formed can be exposed to prevent disconnection of the electrodes and wiring.

[Means for Solving the Problems] In the semiconductor memory device and the manufacturing method thereof according to the present invention, (1) a transfer transistor and a source (for example, an n° source region 25) extending over the transfer transistor; Alternatively, a storage electrode (for example, storage electrode 28) that contacts the drain (for example, n-type drain region 26), a memory capacitor dielectric film (for example, memory capacitor dielectric film 29) that covers the storage electrode, and a memory capacitor dielectric film that covers the dielectric film. A memory capacitor configured with a counter electrode (for example, a counter electrode 30), and an insulating film (for example, an insulating film 31) formed on the upper surface of the counter electrode.
and (33) is thicker than the film thickness of the insulating film (for example, insulating film 33) also formed on the side surface, or (2) in (1) above, the memory cell array is Electrode contact window for metal electrode/wiring in the removed part (for example, electrode/wiring 3 consisting of word line 24 and A!
Insulating films (for example, insulating film 27, memory capacitor dielectric film 29, insulating film 33, PSG film 35
) is thinner than the sum of the insulating film underlying the storage electrode (for example, the insulating film 27) and the insulating film on the counter electrode (for example, the insulating films 31 and 33, and the PSG film 35). (3) In the above (1), the insulation II is located on the counter electrode and has the same shape as the counter electrode! (for example, the insulating film 31),
an insulating film (for example, insulating film 33) that covers the counter electrode and the insulating film having the same shape, or (4) in (3) above, the counter electrode is on the counter electrode and has the same shape as the insulating film. A certain insulating film (for example, BPSG film 37)
(5) In (3) above, the edges of the insulating film that is on the counter electrode and has the same shape as that of the counter electrode are formed to smooth curved surfaces. (6) forming a storage electrode contact window in a first insulating film (e.g., insulating film 27) covering a gate electrode (e.g., word line 24) of a transfer transistor; A storage electrode (for example, storage electrode 28) that contacts the source (for example, n-type source region 25) or drain (for example, n-type drain region 26) through the storage electrode contact window.
and then forming a memory layer covering the storage electrode.
Forming a capacitor dielectric WA (e.g. memory capacitor dielectric film 29) and then forming a conductive film (e.g. polycrystalline Si film) overlying the memory capacitor dielectric film and a second insulating film (e.g. The second insulating film and the conductive film are patterned into the shape of the counter electrode to form the counter electrode (31) in that order.
For example, a step of forming a counter electrode 30), and then a step of forming a third insulator 11A (for example, an insulating film 33) that covers the patterned second insulating film and the counter electrode located thereunder; Next, the third insulating film covering the second insulating film having the same shape as the counter electrode and the first insulating film covering the gate electrode are etched to form a bit line contact window (for example, bit line contact window 33A). Next, a step of forming a bit line (e.g. bit line 34) that contacts the drain or source through the bit line contact window, and then a fourth insulating film (e.g. Next, the fourth insulating film, the third insulating film, and the first insulating film are etched in a portion outside the memory cell array to form an electrode contact window. (7) In (6) above, the fourth insulating film is flattened. (8) In (6) above, does it include a step of flattening and reflowing the second insulating film and then buttering it? (6) includes a step of planarizing and reflowing the second insulating film after patterning the second insulating film and the counter electrode, or (10) in (6) above. The structure includes a step of planarizing and reflowing the third insulating film.

[Operation] By adopting the above-mentioned means, the thickness of the insulating film between the counter electrode and the bit line can be increased as in the conventional case.
The bit line parasitic capacitance does not increase, and since the electrode contact window for connecting the word line, which is the gate electrode of the transfer transistor, to the metal electrode/wiring can be made shallow, the electrode/wiring can be disconnected. There will be very little appetite for doing so.

〔Example〕

1 to 5 are cutaway side views of essential parts of a DRAM at key points in the process for explaining one embodiment of the present invention.
Explanations will be given with reference to each figure. Note that FIG. 5 is enlarged compared to the other figures.

See Figure 1 Selective thermal oxidation (l.

cat oxidation of 5ilic
A field insulating film 22 for element isolation made of Sin is formed on a p-type Si semiconductor substrate 21 by applying the LOCO3) method.

By peeling off the oxidation-resistant mask, the p-type Si semiconductor substrate 2
1 active area is exposed.

A gate insulating film 23 made of SiO□ is formed by applying a thermal oxidation method.

chemical vapor deposition

A first layer polycrystalline Si film is formed by using a polycrystalline deposition (CVD) method.

The first layer polycrystalline Si film is patterned by applying a normal Fort lithography technique to form a word line 24 which is a gate electrode in a transfer gate transistor. In addition, field insulating film 2
The word line 24 seen on 2 is a component of transfer gate transistors included in an array adjacent to the array of transfer gate transistors shown.

By applying the ion implantation method, Word! Using 24 as a mask, n-type impurities are introduced to form an n'' source region 25 and an n'' type drain region 26. In this case, it goes without saying that an n-type impurity is introduced into the word line 24, and if this is activated, the word 24 becomes conductive.

By applying the CVD method, the thickness can be reduced to, for example, 1500 mm.
An insulating film 27 made of SiOz is formed.

By applying the CVD method, the thickness can be reduced to, for example, 1000 mm.
(person) forms a second layer polycrystalline Si film.

Of course, impurities are introduced into this second layer polycrystalline Si film and activated to make it conductive, but at what stage and how is this process performed, that is, growth and It is optional to introduce ions at the same time or to perform ion implantation after growth. Note that the polycrystalline Si film to be formed thereafter is also formed in the same manner.

1=(9) The second polycrystalline layer 5ill is patterned to form the storage electrode 28 in the memory capacitor by using ordinary photolithography techniques.

1-(to) By applying a thermal oxidation method, a memory capacitor dielectric film 29 made of SiO□ with a thickness of, for example, 100 μm is formed.
form.

By applying the CVD method (see Fig. 2), the thickness of
Form a third layer polycrystalline Si film.

By applying the CVD method, the thickness can be reduced to, for example, 1500 mm.
An insulating film 31 made of 5 iOz (man) is formed.

CHF, +He (for SiOz) and C(1!4 +02 (for polycrystalline Si)) for resist process and etching gases in photolithography technology.
reactive ion etching
By applying a ton etching (RIE) method, the insulating film 31 and the third layer polycrystalline Si film are subjected to continuous turning.

As a result, a counter electrode (cell plate) 30 made of a third-layer polycrystalline Si film is obtained, and an insulating film 31 covering it has the same pattern as the counter electrode 30.

By applying the CVD method (see Fig. 3), the thickness can be, for example, 1000 mm.
An insulating film 33 made of [In] Sin is formed.

RI using CHF3 +He as resist, 7'o process and etching gas in photolithography technology
By applying the E method, the insulating films 33 and 27 are etched to form a bit line contact window 33A.

By applying the CVD method (see FIGS. 4 and 5), a thickness of, for example, 2000
A fourth layer polycrystalline Si film (in) is formed.

RIE with resist process and etching gas set to CCL +0□ in photolithography technology
By applying the method, the fourth layer polycrystalline Si film is patterned to form the bit line 34.

In this bit line 34, especially in the memory capacitor part, insulation WA33 and 3 are used as the base.
1 exists and the thickness is 1500 [people) + 1000 C people)
= 2500 C people], which is the same as in the case of the conventional DRAM described with reference to FIGS. 13 to 15, and the parasitic capacitance of the bit line 34 does not increase.

By applying the CVD method, the thickness can be reduced to, for example, 5000 mm.
r people] PSG film 35 is formed.

4-(4) (Hereinafter, refer to FIG. 5 in particular) The resist process and etching gas in photolithography technology is CH3+0z (for PSG) and CHF3.
By applying the RIE method with + He (for Si0 Form a contact window.

As described above, the underlying layer of the bit line 34 is thick enough to prevent an increase in parasitic capacitance, but the depth of the electrode contact window formed here is equal to the thickness of the PSG film 35 + insulating film 33 + insulating film 27. It is equivalent to 5000+1000+
1,500 = 7,500C people], which is about 20% less than if we relied on conventional technology.
It is clear that the aspect ratio is less than 1.0.

This is completed by forming electrodes/wirings 36 made of A1 by using the method of violence and photolithography.

Various modifications can be made to the embodiment described above. For example, in the process shown in FIG. By performing the planarization reflow, the influence of the unevenness of the storage electrode 28 can be eliminated, so that subsequent patterning can be performed satisfactorily.

In addition, in that case, the PSG film and the third layer polycrystalline 5ill
After patterning into the shape of a counter electrode, a Sin is formed in the same manner as in the process explained with reference to FIG.

By forming the insulating film 33 made of PSG, it is possible to block impurities in the PSG film from being diffused into the bit line 34, which is the fourth layer of polycrystalline St film to be formed subsequently. Impurities are introduced into the source region 2 through
5 and the problem of increasing the diffusion depth can be avoided.

FIGS. 6 to 10 are cutaway side views of essential parts of a DRAM at key process points for explaining other embodiments of the present invention, and the explanation will be given below with reference to these figures. . Note that the same symbols as those used in FIGS. 1 to 5 represent the same parts or have the same meanings.

Refer to FIG. 6 In exactly the same manner as in the previous embodiment, a p-type Si semiconductor substrate 21
Formation of field insulating film 22 for element isolation made of Sin, formation of gate insulating film 23 made of Sin, formation of word line 24 made of impurity-containing polycrystalline Si,
Formation of n' source region 25 and n' type drain region 26, formation of insulation M27 made of SiO□, formation of storage electrode 28 made of impurity-containing polycrystalline Si, formation of capacitor dielectric film 29 made of Sin, counter electrode A third layer polycrystalline Si film containing impurities to be 30% is formed.

By applying the CVD method (see Fig. 7), the thickness can be reduced to 200 mm, for example.
Boron-containing phosphosilicate glass (b.

rophosphosilicate glass
: BPSG) film 37 is formed.

The BPSG film is 5OG (spin on glass).
) can be replaced by a membrane.

The BPSG film 37 is planarized and reflowed by heat treatment for 20 minutes at a temperature of 850C''C).

Refer to Figure 8. The resist process in photolithography technology and the RIE method using etching gas of HF, /He (for BPSG) and CC1 = 10x (for polycrystalline Si) can be applied. Accordingly, the BPSG film 37 and the third layer polycrystalline Si film are patterned.

By going through this process, the third layer polycrystalline Si film is patterned into the shape determined as the counter electrode in the memory capacitor, and in the figure, this is indicated as the counter electrode 30. .

The patterning for forming this counter electrode 30 is performed using BPSG.
Pattern formation is easy because the step is absorbed by the film 37 of the storage electrode 28.

Referring to FIG. 9, heat treatment is performed at a temperature of 850 ("C) for a time of 20 [minutes] to perform smooth reflow of the BPSGliR37.

By going through this process, the edges of the BPSG film 37 have a rounded and inclined shape, and the vertical step difference is alleviated.

See Figure 1O 1O-(1) Depending on the CVD method, the thickness may be 1000 mm, for example.
A film 38 made of SiO□ (containing) is formed.

1O-(2) The insulating films 38 and 27 are etched to form the bit line contact window 38A by applying the resist process in the photolithography technique and the RIE method using CHF and +He as the etching gas. Form.

1O-(3) After this, although not shown in the drawings, it is sufficient to take steps exactly the same as in the embodiment described with reference to FIGS. 1 to 5. That is, by applying the CVD method, the thickness can be reduced to, for example, 200 mm.
A fourth layer polycrystalline Si film of 0 C thickness is formed.

■ CCX for resist process and etching gas in photolithography technology.

By applying the RIE method at +Oz, the fourth layer polycrystal 5ill is patterned to form a bit line.

In this bit line, especially in the memory capacitor part, there is a BPSC film 37 and an insulating film 38 as the underlying layer, and the thickness is about 2000 C+100.
0 C people]=approximately 3000 [in], and as in the case of the previous embodiment, no increase in parasitic capacitance occurs in the bit line.

1O-(4) After this, similar to the embodiment described with reference to FIGS. 1 to 5, a PSG film is formed, an MpSG film is formed at a location away from the cell array that has become a block, and insulating films 38 and 27 are formed.
The electrode contact window is formed by etching, and electrodes and wiring made of Al are formed to complete the process.

As mentioned above, the underlying layer of the bit line is thick enough that there is no increase in parasitic capacitance, but the depth of the electrode contact window formed here is as follows: PSG film + insulation film 38 + insulation film 2
Corresponds to the thickness of 7, 5000+1000+1500=7
500 (in), which is about 20% less than when relying on conventional technology, so in this case as well,
It is clear that the aspect ratio is less than 1.0.

FIGS. 11 and 12 show cutaway side views of essential parts of a DRAM at key points in the process for explaining still another embodiment of the present invention, and the explanation will be given below with reference to these figures. do.

Note that the same symbols as those used in FIGS. 6 to 10 represent the same parts or have the same meanings.

Refer to FIG. 11 1l-(1) After the step of FIG. 9 in the embodiment explained with respect to FIGS. 6 to 10, that is, after forming the counter electrode 30 and performing smoothing reflow of the BPSG film 37. , again by applying the CVD method, a BP of 3000 [man] thick, for example.
SG film 39 film type 9.

In this case as well, BPSG*39 can be replaced with an SOC film.

1l-(2) A heat treatment is performed at a temperature of 850° C. and a time of 201 minutes to reflow the BPSG film 39 to form 9.

Refer to Figure 12. RI using CHF3 +He as the resist, 7'o etching and etching gas in photolithography technology.
By applying the E method, the BPSG film 39 film type 9 edge film 27 is etched to form the bit line contact window 39A.
form.

A heat treatment is performed at a temperature of 850° C. and a time of 201 minutes to perform reflow to form a BPSG film 39 film type 9.

Thereafter, the same steps as in the embodiment described with reference to FIGS. 1 to 5 or 6 to 10 are taken to complete the process.

The DRAM obtained according to this embodiment can also exhibit exactly the same effects as those obtained according to other embodiments. In particular, when compared with each of the above embodiments, since the bit line contact window is formed in a flattened BPS G111, the lithography can be performed easily and accurately. Level differences can be alleviated.

In general, in this type of DRAM, for example, FIGS.
As seen at the right end of FIG. 2, in the part where the word lines are parallel, the recesses of the word line pattern and the recesses of the storage electrode pattern overlap, so the step difference is maximum. However, in the present invention, the counter electrode is present in the part where the step difference is maximum, and the PSG film thereon is planarized and reflowed, so that the SiO□ film to be formed thereafter is not planarized. The base for forming bit lines is sufficiently flat even without reflow, and therefore the processing can be carried out with high precision and easily.

The present invention particularly focuses on the first layer of polycrystalline 5il which becomes the word line.
This is effective when the difference in level caused by 1 is small and the difference in level caused by the second layer polycrystalline Si film serving as the storage electrode is large. The reason for this is that the step of the second layer polycrystalline Si film is the third layer polycrystalline 5ilI which becomes the counter electrode (cell plate).
i! , does not affect pattern formation such as etching, whereas the step difference in the first layer polycrystalline Si film has a direct effect.

[Effects of the Invention] A semiconductor memory device realized by the present invention includes a transfer transistor and a memory capacitor, and the thickness of the insulating film formed on the upper surface of the counter electrode of the memory capacitor is the same as that of the side surface. It is thicker than the thickness of the formed insulating film.

By employing the above structure, the thickness of the insulating film between the counter electrode and the bit line is as thick as in the conventional technology, and therefore, the bit line parasitic capacitance does not increase, so high speed is maintained. Furthermore, since the electrode contact window for contacting the word line, which is the gate electrode of the transfer transistor, with the metal electrode/wiring can be made shallow, there is less risk of the electrode/wiring being disconnected.

[Brief explanation of drawings]

1 to 5 are cutaway side views of essential parts of D R and A M at important process points for explaining one embodiment of the present invention, and FIGS. 6 to FIGS. 11 and 12 are cross-sectional side views of main parts of a DRAM at important process points for explaining an embodiment, and FIGS. FIGS. 13 and 14 are cutaway side views of the main parts of a DRAM, and FIGS.
Each shows an equivalent circuit diagram of AM. In the figure, 21 is a P-type Si semiconductor substrate, 22 is a field insulating film, 23 is a gate insulating film, 24 is a word line, 2
5 is an n-type source region, 26 is an n-type drain region 2
7 is an insulating film, 28 is a storage electrode, 29 is a memory capacitor dielectric film, 30 is a counter electrode, 31 is an insulating film, 33 is an insulating film, 34 is a bit, 7t wire, 35 is a PSG film, 36 is an A1
The electrodes and wiring made up of the following are shown.

Claims (10)

[Claims] (1) A memory capacitor consisting of a transfer transistor, a storage electrode extending over the transfer transistor and contacting the source (or drain), a dielectric film covering the storage electrode, and a counter electrode covering the dielectric film. A semiconductor memory device comprising: an insulating film formed on the upper surface of the counter electrode, which is thicker than an insulating film also formed on the side surface. (2) The insulating film located on the area where the electrode contact window for metal electrodes and wiring in the area outside the memory cell array is to be formed is the underlying insulating film of the storage electrode and the opposing insulating film. 2. The semiconductor memory device according to claim 1, wherein the film thickness is thinner than the thickness including the insulating film on the electrode. (3) The semiconductor memory device according to claim 1, further comprising: an insulating film located on the counter electrode and having the same shape as the counter electrode, and an insulating film covering the counter electrode and the insulating film having the same shape. . (4) The semiconductor memory device according to claim 3, wherein the insulating film located on the counter electrode and having the same shape as the counter electrode is formed so as to smooth out the unevenness of the base. (5) The semiconductor memory device according to claim 3, wherein an edge of an insulating film located on the counter electrode and having the same shape as the counter electrode is formed to form a smooth curved surface. (6) Forming a storage electrode contact window in the first insulating film covering the gate electrode of the transfer transistor, and then forming a storage electrode in contact with the source (or drain) through the storage electrode contact window. Then, a step of forming a memory capacitor dielectric film covering the storage electrode, a step of forming a conductive film and a second insulating film covering the memory capacitor dielectric film in that order, and then, forming a counter electrode made of the conductive film by patterning the second insulating film and the conductive film in the shape of a counter electrode, and then forming the patterned second insulating film and the counter electrode thereunder. forming a third insulating film covering the gate electrode; and then etching the third insulating film covering the second insulating film having the same shape as the counter electrode and the first insulating film covering the gate electrode. forming a line contact window, forming a bit line that contacts the drain (or source) through the bit line contact window, and forming a fourth insulating film covering the bit line. and then etching the fourth insulating film, the third insulating film, and the first insulating film in a portion outside the memory cell array to form an electrode contact window, and then etching the fourth insulating film, the third insulating film, and the first insulating film in a portion outside the memory cell array to form an electrode contact window. 1. A method of manufacturing a semiconductor memory device, comprising the step of forming electrodes and wiring. 7. The method of manufacturing a semiconductor memory device according to claim 6, further comprising the step of: (7) planarizing and reflowing the fourth insulating film. 8. The method of manufacturing a semiconductor memory device according to claim 6, further comprising the step of flattening and reflowing the second insulating film and then patterning the second insulating film. (9) The method of manufacturing a semiconductor memory device according to claim 6, further comprising the step of planarizing and reflowing the second insulating film after patterning the second insulating film and the counter electrode. 7. The method of manufacturing a semiconductor memory device according to claim 6, further comprising the step of: (10) planarizing and reflowing the third insulating film.