JPH0445008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a NOT circuit used in Josephson logic circuits and Josephson memory circuits.

(Prior art and its problems) When configuring a logic circuit using Josephson circuits,
As in the case of constructing logic circuits using conventional silicon technology, generation of a negation signal is essential. However, Josephson logic circuits have a small signal amplification factor, so clutch operation is the main operation.
The drawback was that it was difficult to construct a negative circuit.

Conventionally, as a circuit that generates a complementary signal to an input signal, there is a circuit that generates a complementary signal to an input signal.
development), Volume 24, No. 2, Page 139, and a negative circuit consisting only of resistors and Josephson junction elements, excluding inductance, published in April 1982. Proceedings of the 1981 National Conference of the Institute of Electronics and Communication Engineers, Volume 2, page 2-448 Timed inverter NOR logic circuits are known.

As shown in FIG. 5, the timed inverter circuit has two inductances 511 to 511, respectively.
514 and two Josephson junction elements 521-5
This is a circuit in which two 2-junction squids 501 and 502 consisting of 24 are connected in series as switch gates. A gate current is injected into the two two-junction squids 501 and 502 via a terminal 544. A data signal to be negated is applied from a terminal 541 to the first two-junction squid 501.
A timing signal for generating a negative signal is input to the second two-junction squid 502 from a terminal 542. The output signal is taken out from the output terminal 543 via the load resistor 532.

The inverter circuit operates as follows.

1 Data signal “1” is 2-junction squid 501
The two-junction squid 501 switches, and most of the gate current flows into the load resistor 531. Even if a timing signal is then input to the 2-junction squid 502, the 2-junction squid 502 does not switch because almost no gate current flows through the 2-junction squid 502. Therefore, no output current appears at the output terminal 543. That is, "0" is output.

2 Data signal “0” is 2-junction squid 501
is input. At this time, 2-junction squid 50
1 is not switched and the gate current continues to flow through the two-junction squid 502. Subsequently, when the timing signal is input to the two-junction squid 502,
The two-junction squid 502 switches and an output current, or "1", appears at the output terminal 543.

In the manner described above, a complementary signal of the input data signal is generated.

FIG. 6 shows a conventional timed inverter NOR logic circuit. This circuit consists of Josephson junction elements 601-607 and resistors 611-607.
618, input resistors 619 and 620, and a load resistor 621. The data signal is input to a data signal input terminal 631, and the timing signal is input to a timing signal input terminal 632. Gate current is injected from terminal 634.

Operation when data signal "1" is input: When data signal "1" is input, Josephson junction elements 601 and 602 are switched in sequence. By switching the Josephson junction elements 601 and 602, the gate current is changed to the Josephson junction element 60.
6 and switches Josephson junction 606. Josefson junction element 601, 602, 6
06, the gate current flows into the load resistor 621 and the Josephson junction element 603.
~605, current stops flowing.

A timing signal is input to input terminal 632 with a delay from the data signal. At this time, since almost no gate current flows through the Josephson junction elements 603 to 605, the Josephson junction elements 603 to 605
3 to 605 do not switch. Due to the above operation, no output appears at the output terminal 633. That is, a complementary signal "0" of the data signal "1" is output.

Operation when data signal “0” is input: Data signal “0” means that the signal current is zero. Therefore, even if the data signal "0" is input to the data signal input terminal 631, the states of the Josephson junction elements 601 to 605 do not change. That is, the gate current continues to flow through the Josephson junction elements 601-605.

Subsequently, when the timing signal is input to the timing signal input terminal 632, the Josephson junction element 6
03-605 switch. By switching Josephson junction devices 603-605, gate current flows into Josephson junction devices 606 and 607, switching both gates. Due to the switches of Josephson junction elements 601 to 607, the gate current flows to the output terminal 633, and the output signal is "1".
is obtained. That is, a complementary signal "1" of the data signal "0" is output.

(Problems to be Solved by the Invention) In the conventional timed inverter circuit shown in FIG. 5, a switch gate is constructed of a squid composed of an inductance, a transformer, and a Josephson junction element. Therefore, there is a drawback that the area of the negative circuit cannot be reduced in order to realize a desired inductance value. That is, when the Squid inductance is L and the gate current value used for logic is I, there is a relationship of LIΦ ₀ /2 (Φ ₀ represents a magnetic flux quantum, and Φ ₀ =2.07×10 ^-5 Weber). Therefore, in order to reduce power consumption,
When the logic current I is reduced, L becomes larger and larger, making it even more difficult to reduce the circuit area.
Furthermore, an increase in circuit area results in an increase in signal transmission time, which has been an obstacle to increasing the speed of logic circuits and memory circuits.

On the other hand, the conventional timed inverter NOR logic circuit shown in Figure 6 consists of only resistors and Josephson junction elements, excluding inductance, so it is possible to reduce the circuit area and increase the speed of the circuit. Since the Josephson junction element 607 for input/output signal separation is grounded via the input resistor 620, there is a drawback that the operating margin is narrow for the following reason.

That is, as described above, when the data signal is "0", the Josephson junction elements 606 and 607 are switched after the Josephson junction elements 603 to 605 are switched. In this case, a wider operating margin can be obtained under the condition that Josephson junction element 606 is switched first. However, even in the case where Josephson junction element 606 is switched first, the gate current is
Since the gate current is shunted to ground via the input resistor 620, the gate current injected into the Josephson junction element 606 is reduced, and the lower limit of the operating margin becomes large, narrowing the operating margin of the circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current-limited Josephson inverter which eliminates the drawbacks of the conventional Josephson inverter described above, reduces the area, increases the speed of circuit operation, and provides a wide operating margin.

(Means for solving the problem) The current-limited Josephson inverter of the present invention has the following features:
two or more Josephson junction elements for a first switch having an injection end and an extraction end for gate current; a resistor circuit for injecting gate current into the Josephson junction elements; one end connected to the injection end and the other end; is connected to a first signal input terminal, an input resistor connected between the first signal input terminal and ground, and the input/output isolation Josephson junction element is connected. a load resistor connected to an injection end different from that of the first Josephson logic circuit, the output end of the Josephson junction element for the first switch being a current output end of the circuit; two or more Josephson junction elements for a second switch, each having an injection end and an outflow end, a resistor circuit for injecting a gate current into the Josephson junction element for the second switch, and one end for the second switch; A current-limiting Josephson junction element connected to an injection end of the Josephson junction element and whose other end is connected to a second signal input terminal, and the current-limiting Josephson junction element of the second Josephson junction element are connected. and a load resistor connected to an output terminal and an injection end different from that of the second Josephson logic circuit, wherein the output terminal of the second Josephson junction element is the current output terminal of the circuit. wherein an input resistor is not connected between the second signal input terminal and ground, and a current extraction end of the first Josephson logic circuit is connected to a resistance circuit of the second Josephson logic circuit. , is obtained by grounding the current extraction end of the second Josephson logic circuit.

(Function) The current-limited Josephson negation circuit of the present invention has the following characteristics:
A data signal is input to the first signal input terminal, and a timing signal is input to the second signal input terminal, and by raising the timing signal later than the data signal, a complementary signal of the data signal is generated at the rise of the timing signal. It is a circuit.

That is, when a data signal "1" is input, the gate current injected into the second Josephson logic circuit is reduced by switching the first Josephson logic circuit, and the gate current injected into the second Josephson logic circuit is also reduced by the subsequently input timing signal. Circuit constants are set so that the second Josephson logic circuit does not switch.

On the other hand, when the data signal "0" is input, the first Josephson logic circuit does not switch, and most of the gate current is injected into the second Josephson logic circuit. The logic circuit switches,
A complementary signal "1" of the data signal "0" is output.

In the circuit of the present invention, since the second signal input terminal is a low impedance circuit and is not grounded, the operating margin for switching the input/output separation Josephson junction element is widened, and the circuit operating margin is widened.

(First Embodiment) A first embodiment of the current-limited Josephson inverter according to the present invention is shown in FIG. The Josephson junction elements 101 and 102 for the first switch of the first Josephson logic circuit are connected in parallel through resistors 111 and 112 forming a resistance circuit. Similarly, the second
Josephson junction element 103, 10 for switch
4 are connected in parallel via resistors 113 and 114 of a resistor circuit. The current extraction end of the first Josephson logic circuit is connected to the current injection end of the second Josephson logic circuit, and the current extraction end of the second Josephson logic circuit is grounded. Hereinafter, the circuit operation of this embodiment will be explained based on FIG.

Generation of complementary signal of data signal “1”: Data signal “1” is connected to the first signal input terminal 121
, the first switching Josephson junction element 101 switches. Switching the Josephson junction element 101 subsequently switches the Josephson junction element 102 for the first switch. The switching of the Josephson junction elements 101 and 102 causes the gate current to flow towards the input/output isolation Josephson junction element 105, causing the input/output isolation Josephson junction element 105 to switch.
The switching of Josephson junction devices 101 , 102 , 105 causes most of the gate current to flow into load resistor 116 . Therefore, the gate current flowing through the second Josephson junction elements 103 and 104 for the second switch in the second Josephson logic circuit is reduced to almost zero.

Subsequently, a timing signal is input to the second signal input terminal 122. The timing signal flows into the second switching Josephson junction element 103 of the second Josephson logic circuit, but since almost no gate current flows through the Josephson junction element 103, it does not switch. Accordingly, the second switching Josephson junction element 104 also does not switch, and no output current appears. With the above operation,
A data signal “0” which is a complementary signal of the input data signal “1” is obtained from the output terminal 123.

Generation of complementary signal of data signal “0”: Data signal “0” is input to the first signal input terminal 12.
1 is input. A signal "0" means that the input current is zero. Therefore, the first switching Josephson junction element 101 of the first Josephson logic circuit does not change, ie does not switch. Thus, gate current continues to be injected from the first Josephson logic circuit into the second switching Josephson junction elements 103, 104 of the second Josephson logic circuit.

Subsequently, a timing signal is input to the second signal input terminal 122. Josephson junction element 10 for the second switch of the second Josephson logic circuit
Since a gate current flows through transistors 3 and 104, Josephson junction elements 103 and 104 are sequentially switched by injection of a timing signal current. Most of the gate current is shunted to the input/output isolation Josephson junction element 105 by switching the Josephson junction elements 103 and 104. The gate current diversion ratio is determined by the resistance value r ₁ of the input resistor 115 and the load resistance 1
It almost depends on the resistance values r ₄ and r ₅ of 16 and 117 and the current value I _t of the timing signal. Here, the resistance values r ₂ and r ₃ of the resistors 111 to 114 of the resistance circuit are ignored as they are sufficiently smaller than the resistance value r ₁ of the input resistance.
Josephson junction element 10 for input/output isolation switch
By setting the critical current value a _Ip of 5 to be below the shunted current value, Josephson junction element 10
5 switches. Therefore, the gate current and the timing signal current are connected to the load resistor 116 and the load resistor 11.
7 and flows. Therefore, the output terminal 123 receives a signal “1” which is a complementary signal of the data signal “0”.
is output.

As described above, the circuit of this embodiment generates the complementary signal of the data signal input to the first signal input terminal 121 in synchronization with the timing signal input to the second signal input terminal 122. , output terminal 1
Send to 23. In this embodiment, the gate current I _g is injected from the gate current injection terminal 124 before inputting each signal.

Figure 2 shows Josephson junction element 1 for switch.
The threshold characteristic of this example is shown when the critical current value of 01 to 104 is I _p and the critical current value of the current limiting Josephson junction element 106 is bIo. The vertical axis in the figure shows the gate current _Ig injected into the terminal 124, and the horizontal axis shows the data signal current input into the first and second signal input terminals 121 and 122.
I _d and timing signal current I _t are shown, respectively. In the figure, the gate current I _g , the data signal current I _d , and the timing signal current I _t are all normalized by the critical current value I _p of the Josephson junction elements 101 to 104 for switches. Figure 2a shows the relationship between gate current _Ig and data signal current _Id , and Figure 2b shows the relationship between gate current Ig and data signal current Id.
The relationship between I _g and timing signal current I _t is shown.

First, the operating threshold value when a timing signal is input after a data signal "1" is input will be explained. A threshold value 201 indicates a critical current value aI _p of the input/output separation Josephson junction element 105. A data signal current I _d greater than or equal to aI _p is not injected into the switch Josephson junction elements 101 and 102 via the input/output separation Josephson junction element 105 .

The threshold value 202 is a threshold value I _g > which switches the Josephson junction element 101 for switching when the gate current I _g and the data signal current I _d are added together.
(2+r ₃ /r ₁ )(I _p −I _d ). aI _p
The above data signal current I _d is not injected into the Josephson junction element 101, so the threshold value 202
is constant in the region I _d > aI _p where the data signal current is larger than the threshold value 201 I _g > (2+r ₃ /r ₁ ) (1-a) I _p
becomes the threshold value 203.

The threshold value 204 is the threshold value at which the input/output separation Josephson junction element 105 switches after the switch Josephson junction elements 101 and 102 switch, I _g > (1 + r ₁ / r ₄ ) aI _p + (r ₁ / r ₄ ) It shows I _d . This is the resistance value of input resistor 115
r ₁ , the resistance value r ₄ of the load resistor 116, and the critical current value aI _p of the Josephson junction element 105. However, the resistance value r ₂ of resistors 111 and 112 is
It is omitted because it is sufficiently small compared to r ₁ and r ₄ .
More specifically, it is calculated including the resistances 111 and 112.

Josefson junction elements 101, 102, 105
The gate current is controlled by the load resistor 116 by the switch of
flows into. The resistance value r ₄ of the load resistor 116 is
When set smaller than V _g /I _g (where V _g is the gap voltage of the Josephson junction element), most of the gate current is absorbed by the load resistor 116, and the leakage current to the second Josephson logic circuit is The nonlinear resistance value of elements 101 and 102 is
When R _n , it becomes 2V _g /R _n or less. Therefore, the timing signal is then sent to the second signal input terminal 122.
Even if input to Josephson junction element 103,
104 does not switch.

The threshold value 205 indicates the condition I _g <(2+r ₃ /r ₁ )I _p under which the Josephson junction elements 101 and 102 for switching do not switch with only the gate current.

In deriving the above conditions, the nonlinear resistance of Josephson junction elements 101 and 102 is calculated for each resistance value.
It is assumed that it is sufficiently larger than r ₁ , r ₂ , r ₃ , and r ₄ and is omitted from the calculation formula for simplicity. More precisely, each threshold value is determined by considering the specific linear resistance of each Josephson junction element.

Next, based on FIG. 2b, the operation when a timing signal is input after the data signal "0" is input to the first signal input terminal 121 will be described. Critical current value of current limiting Josephson junction element 106
Since bI _p , a threshold 211 similar to the threshold 201 is obtained.

The threshold value at which the switching Josephson junction element 103 of the second Josephson logic circuit is switched by _the current I _t of the timing signal is _{I g >} (2+r ₃ /r ₁ ) (I _p − I _t ) threshold value 212
and I _g > ( ₂ + r _{3 /} r ₁ ) (1-
b) It becomes the threshold value 213 of I _p . Subsequently, the threshold value 214 at which the input/output separation Josephson junction element 105 switches is I _g > (1 + r ₁ / (r ₄ + r ₅ )) aI _p
+I _t . Here, the resistance value r ₃ of the resistors 113 and 114 is ignored because r ₃ < r ₁ < r ₄ , r ₅ .

The threshold value 215 represents the condition I _g <(2+r ₃ /r ₁ ) I _p under which the Josephson junction elements 103 and 104 are not switched by the gate current alone.

In deriving the above conditional expression, the specific linear resistance of Josephson junction elements 101 to 105 is calculated for each resistance value.
The resistance values r _{2 and r 3 of} the resistors 111 to 114 of the resistance circuit are sufficiently large compared to the resistance values r ₁ , r ₄ , and r ₅ of the other resistors. Assuming that,
For the sake of simplicity, we omitted all the important points from the calculation. More precisely, each threshold value is determined by considering all of these resistance values. However, the difference between this accurate threshold and the threshold shown in FIG. 2 is extremely small.

Above, threshold values 202, 203, 204, 20
5, and a hatched area 2 surrounded by threshold values 212, 213, and 215.
22 is the operating area of this embodiment. From the figure, it can be seen that the threshold value 214 which is switched by the input/output separation Josephson junction element 105 when the data signal is "0" does not affect the operating characteristics. More precisely, the resistances 111-1 of nonlinear resistance and resistance circuits
14, the operating areas 221 and 222 are somewhat reduced.

Although not mentioned above, the operating range of this NOT circuit changes greatly depending on the setting of the resistance value _r4 of the load resistor 116. In particular, a problem arises when the resistance value of the load resistor 116 is set to r ₄ >V _g /I _g in order to increase the output current of the NOT circuit of this embodiment. r ₄
>V _g /I _g , the gate current (I _g −V _g /r ₄ ) (2/(2
+a)) leaks into the second Josephson logic circuit. Due to this leakage current and the timing signal current inputted subsequently, the Josephson junction element 10 for the switch of the second Josephson logic circuit
3,104 is required not to switch. This condition is I _g < (2 + a) I _p + V _g /r ₄ - (2
+a) _It can be expressed as a threshold value 216. In the figure, threshold 216 and threshold 211 intersect in a region where gate current I _g is greater than threshold 215 . Here, the threshold value 211 is constant I _t in the region where the timing signal current is I _t >bI _p
= bI _p, indicating that a timing signal current greater than bI _p is not injected into the Josephson junction element for the switch. Therefore, the threshold value 2 in the region I _t > bI _p
16 does not affect the switch of the second Josephson logic circuit. That is, when the threshold value 216 crosses the intersection of the threshold value 211 and the threshold value 215, the condition is such that the threshold value 216 provides the maximum resistance value r ₄ without affecting the operating characteristics. Therefore, by setting the resistance value r ₄ of the load resistor 116 below the above-mentioned condition value, the effect of the leakage current of the first Josephson logic circuit on the second Josephson logic circuit can be eliminated.

As described above, since this embodiment does not use an inductance as a circuit element, the circuit area can be reduced. Furthermore, since the input resistor is removed from the second Josephson logic circuit and a current limiting Josephson junction element is inserted, the operating range is expanded.

Note that there is no problem in eliminating the input resistance of the second Josephson logic circuit because of the way the NOT circuit is used. That is, the timing signal input to the second Josephson logic circuit is input in parallel to all the NOT circuits. Also, from the threshold characteristics shown in Figure 2b,
A timing signal current greater than or equal to bI _p does not affect the operation of the inverter. This means that even if the timing signal current I _t flowing into another NOT circuit increases due to a load change in a certain NOT circuit, the operating range of the other NOT circuit is not affected at all. Furthermore, the timing signal is inputted to all the NOT circuits at once, causing each NOT circuit to operate simultaneously. In addition, since the switching operation of the first Josephson logic circuit caused by the data signal does not affect the second signal input terminal, noise flows from the inverting circuit into the previous stage timing signal generation circuit, causing the previous stage circuit to be damaged. No failure modes occur that cause a switch.

(Second Embodiment) A circuit diagram of a second embodiment of the present invention in which three Josephson junction elements for a switch are connected in parallel is shown in FIG. Josephson junction elements 301 to 303 for the first switch of the first Josephson logic circuit
are the resistors 311 to 315 that constitute the resistance circuit.
are connected in parallel via. Similarly, the second switch Josephson junction elements 304-306 of the second Josephson logic circuit are connected in parallel via resistors 316-320 of the resistive circuit. The other circuit configurations are the same as in the first embodiment.

This embodiment has a configuration in which Josephson junction elements 303 and 306 for switches are added to the first embodiment, and operates in the same way as the first embodiment. That is, upon input of the data signal "1", the first switch Josephson junction elements 301 to 303 are sequentially switched on, and then the input/output separation Josephson junction element 307 is switched on. Therefore, the gate current flows into the load resistor 322, with little leakage to the second Josephson logic circuit. Therefore,
Subsequently, the timing signal is sent to the second signal input terminal 33.
2, the Josephson junction element 304 for the second switch of the second Josephson logic circuit
~306 is not switched and no output current appears at the output terminal.

On the other hand, when the data signal "0" is input to the first signal input terminal 331, the first and second Josephson logic circuits do not change, and the gate current I _g continues to be injected into the second logic circuit. . Therefore, when the timing signal is subsequently input to the second signal input terminal 332, the second
Josephson junction elements 304-30 for switches
6 switches sequentially. Subsequently, the input/output separation Josephson junction element 307 is switched on, and an output current is injected into the output terminal 333.

FIG. 4 shows threshold characteristics showing the operation of this embodiment. Josephson junction element 301 for switch
306 critical current value is I _p , critical current value of input/output separation Josephson junction element 307 is aI _p , critical current value of current limiting Josephson junction element is bI _p , gate current is I _g , resistance value of resistors 311 to 313 r ₂ ,
Let the resistance value of the resistors 316 to 318 be _r3 .

FIG. 4a shows the relationship between the gate current _Ig and the data signal current _Id . The threshold value 401 indicates the critical current value of the input/output separation Josephson junction element 307, and the threshold values 402 and 403 are threshold values I _g for switching the Josephson junction element 301 for the first Josephson logic circuit switch. ＞
(3 + r ₃ / r ₂ ) (I _p − I _d ), I _g > (3 + r ₃ / r ₁ ) (1−
a) I _p is shown. After the Josephson junction elements 301 to 303 for switches switch,
The threshold value 404 at which the input/output separation Josephson junction element 307 switches is I _g > (1+r ₁ /r ₄ )aI _p
+(r ₁ /r ₄ )I _d . The threshold value 405 is the condition that the Josephson junction elements 301 to 303 for switching do not switch with only the gate current _{I g} <(3+r ₃ /
r ₁ ) indicates I _p .

FIG. 4b similarly shows the relationship between the gate current _Ig and the timing signal current _It . The threshold value 411 is the critical current value of the current limiting Josephson junction element 308, and the threshold values 412 and 413 are the gate current I _g and the timing signal current I _t of the Josephson junction element for the switch of the second Josephson logic circuit. Conditions for switching 304 to 306, I _g
＞(3+r ₃ /r ₁ )(I _p −I _t ), I _g ＞(3+r ₃ /r ₁ )(1
−
b) Indicate I _p respectively. The condition for the input/output separation Josephson junction element 307 to switch after the switching Josephson junction elements 304 to 306 are switched is I _g > (1 + r ₁ / (r ₄ + r ₅ )) aI _p + I _t , which is indicated by the threshold value 414. has been done. The threshold value 415 is
Conditions I _g < (3
+r ₃ /r ₁ )I _p .

When the resistance value r ₄ of the load resistor 322 is r ₄ >V _g /I _g , the condition indicated by the threshold value 416 (I _g −V _g /
r ₄ ) (3/(3+a)) is added. threshold 416
When the threshold value 411 and the threshold value 415 intersect, this is a condition in which the maximum output current can be obtained under the condition that the threshold value 416 does not affect the operating region of the NOT circuit.

Above, threshold value 402, 403, 404, 40
5, and the threshold value 41
An area 422 surrounded by 2, 413, and 415 is the operating area of this embodiment. From the figure, when the data signal is "0", the input/output separation Josephson junction element 30
It can be seen that threshold 414, which is switched by 7, does not affect the operating characteristics. More precisely, the nonlinear resistance of Josephson junction element and the resistance 31 of the resistance circuit
1 to 320 must be taken into account, which reduces the operating areas 421 and 422 to some extent. In this embodiment, three Josephson junction elements for a switch are connected in parallel, so that the operating range of the gate current _Ig is wider than in the first embodiment. However, the critical current values aI _p , bI _p of the input/output separating Josephson junction element 307 and the current limiting Josephson junction element 308
The optimal value is selected.

As described above, this embodiment also provides the same effects as the first embodiment. In addition, as another embodiment of the present invention, there is a circuit in which two or more Josephson junction elements for switches of the first and second Josephson logic circuits are connected in parallel via a resistor, etc., and gate current is injected by the resistor circuit. can be mentioned.

(Effects of the Invention) As described above, according to the present invention, a negative circuit without inductance, which was conventionally used in negative circuits, is realized, and the disadvantage that the circuit area cannot be reduced due to inductance constraints is eliminated, and the circuit can be miniaturized. It is measured. The speed of the circuit can be increased by reducing the signal transmission delay due to the miniaturization of the circuit, and the speed can also be increased by eliminating the switch control of Josephson junction elements using magnetic field coupling. Furthermore, by eliminating the input resistance for timing signals, the operating range is expanded. Moreover, the removal of the input resistance does not impose any restrictions on the use of the present NOT circuit.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the first embodiment of the present invention, Fig. 2 is a diagram showing the threshold characteristics of the circuit of the first embodiment, and Fig. 2a shows the data signal current. Figure 2b is a diagram showing the relationship between I _d and gate current I _g , Figure 2b is a diagram showing the relationship between timing signal current I _t and gate current I _g , and Figure 3 is a diagram showing the relationship between timing signal current I t and gate current I g. The illustrated circuit diagram, FIG. 4, is a diagram showing the threshold characteristics of the circuit of the second embodiment, and FIG. 4a shows the data signal current I _d
Figure 4b shows the relationship between timing signal current It and gate current _Ig , and Figure 5b shows the relationship between timing signal current _It and gate current _Ig .
The figure is a circuit diagram of a conventional inverter circuit using a two-junction squid, and FIG. 6 is a circuit diagram of a conventional timed inverter NOR logic circuit. 101-104, 301-306... Josephson junction element for switch, 105, 307... Input/output separation Josephson junction element, 106, 308
...Current limiting Josefson junction element, 111~1
14,311-320...Resistance of resistance circuit, 11
5, 321...Input resistance, 116, 117, 32
2,323...Load resistance, 121,331...First signal input terminal, 122,332...Second signal input terminal, 123,333...Output terminal, 12
4,334...Gate current injection terminal, _Ig ...Gate current, _Id ...Data signal current, It...Timing signal current, _{Ip ...} Critical current value of Josephson junction element for switch, 201-205 ,211-2
16,401-405,411-416...threshold value, 221,222,421,422...operating area, 501,502...2 junction squid, 5
11-514...Inductance, 521-52
4... Josephson junction element, 531, 532...
...Load resistance, 541...Data signal input terminal, 5
42...Timing signal input terminal, 543...Output terminal, 544...Gate current injection terminal, 601
~607... Josephson junction element, 611~6
18...Resistance, 619,620...Input resistance, 6
21...Load resistance, 631...Data signal input terminal, 632...Timing signal input terminal, 633
...Output terminal, 634...Gate current injection terminal.

Claims (1)

[Claims] 1. Two or more Josephson junction elements for a first switch having a gate current injection end and a gate current exit end,
a resistance circuit for injecting a gate current into the Josephson junction element; an input/output separation Josephson junction element having one end connected to the injection end and the other end connected to a first signal input terminal; and the first signal input. an input resistor connected between the terminal and ground, and a load resistor connected to an injection end different from that to which the input/output isolation Josephson junction element is connected;
a first Josephson logic circuit in which the outlet end of the Josephson junction element for the first switch is a current outlet end of the circuit; and two or more second switches each having a gate current injection end and a gate current outlet end. a resistance circuit for injecting a gate current into the Josephson junction element for the second switch, one end of which is connected to the injection end of the Josephson junction element for the second switch, and the other end of which is connected to the injection end of the Josephson junction element for the second switch; a current-limiting Josephson junction element connected to the input terminal; and a load resistor connected to an injection terminal and an output terminal different from that to which the current-limiting Josephson junction element of the second switch Josephson junction element is connected. comprising a second Josephson logic circuit with the outlet end of the second Josephson junction element for the switch as the outlet end of the current of the circuit, and an input resistance between the second signal input terminal and ground. The current extraction end of the first Josephson logic circuit is connected to the resistance circuit of the second Josephson logic circuit, and the current extraction end of the second Josephson logic circuit is grounded. A current-limited Josephson negation circuit characterized by: