JPH0443625A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable accurate mask alignment by a simple method, by setting the distance between wafer marks in each wafer mark pair so as to be different in the adjacent wafer mark pairs. CONSTITUTION:In wafer mark pairs 1-3, a distance l1 between wafer marks 1a and 1b, a distance l2 between wafer marks 2a-2b, and a distance l3 between wafer marks 3a and 3b are previously arranged so as to be different in the adjacent wafer mark pairs. Mask marks 4a, 4b are set to the alignment wafer marks 1a, 1b of the wafer mark pair 1; mask marks 5a, 5b are set to the alignment marks 2a, 2b of the wafer mark pair 2; mask marks 6a, 6b are set to the alignment marks 3a, 3b of the wafer mark pair 3. When the mask marks 4a, 4b are set, by mistake, not to the wafer marks 1a, 1b as the normal alignment but to, e.g. the wafer marks 2a, 2b, deviation amounts d1, d2, d3, d4 exceed specifications, so that mask alignment can not be performed and imperfect alignment can not be performed and imperfect alignment can be detected.

Description

[Detailed description of the invention] [Industrial usage] The present invention relates to a method for manufacturing a semiconductor device.

[Prior Art] Conventionally, during the manufacturing process of semiconductor devices (for example, IC),
There is a process of aligning the semiconductor wafer and the mask. Usually, alignment wafer marker pairs are formed on the left and right sides of the semiconductor wafer for the number of times mask alignment is performed. The above alignment is performed by aligning the mask mark with the alignment wafer mark, determining the deviation between the marks using an optical method, etc., and moving the relative position between the masks based on the deviation to determine the amount of deviation. When it becomes smaller than a certain value,
Alignment is complete. This alignment will be explained with reference to FIG.

A pair of square alignment wafer marks WIW1a are arranged on the semiconductor wafer at a predetermined distance Ω apart from each other in the left and right directions in FIG. 4(A), and similarly, a plurality of pairs of alignment wafer marks W2. W2a.

W3. W3a is arranged, and the pair of alignment wafer marks are spaced apart by the length of forceps Mm.

Mask matching is performed in the following manner.

Then, as shown in FIG. 4(A), mask marks Ml, M
Align la on the alignment wafer mark W1 and wafer mark Wla, and measure the lateral positional deviations dLl, dL2, dRl, and dR2 of both marks using an optical method, and make sure that both of these values are below a certain standard value. Alignment is performed by changing the relative positions of the wafer mark and mask mark so that Similarly, alignment is performed in the vertical direction as well.

Then, as shown in FIG. 4(B), the mask mark M2.
M2a and the alignment wafer mark W2.2a are then aligned with the mask mark M3.2a as shown in FIG. Mask alignment between M3a and the alignment wafer marks W3, 3a is performed in sequence in the same manner as described above.

[Problems to be Solved by the Invention] According to the conventional example, the wafer marks W1 to W3, W1a-WS constituting each alignment wafer mark pair
The distance g between a and adjacent wafer mark pairs is set equal. For this reason, when aligning, as shown by the open chain line in FIG. 4(A), the alignment mark M1 is mistakenly
, M 1 a is Wahama, '7W 1 , W
Mark W2 of the wafer mark pair adjacent to the wafer mark pair consisting of 1a. When aligned with W2a, the above positional deviations dLl, dL2, dRl, dR2 of both marks
Naturally, the value corresponding to is within the standard value, and it is determined that the alignment is correct, resulting in the inconvenience that poor alignment cannot be detected.

Also, as shown in the chain line in FIG. 4(B), the mask mark M2
If mask mark M2 of M2a is erroneously aligned with wafer mark W3, one of the wafer mark pairs, there will be the same problem as in the above case.

An object of the present invention is to enable correct mask alignment using a simple method and to avoid manufacturing defective semiconductor devices.

[Means for Solving the Problems] In the method for manufacturing a semiconductor device according to the present invention, one pair of wafer marks is selected for each mask alignment process from among a plurality of pairs of alignment wafer marks formed on a semiconductor wafer. In this method of manufacturing a semiconductor device selectively, the distance between the wafer marks in each wafer mark pair is formed to be different for adjacent wafer mark pairs.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

When manufacturing a cliff conductor device, a first layer is placed on a semiconductor wafer in advance.
As shown in Figure (A), wafer mark pair 1 and wafer mark pair 2 consist of a pair of left and right alignment wafer marks.
and wafer mark pairs 3 are arranged 17 in the vertical direction in the figure.

Wafer mark pair 1 consists of square wafer marks la and lb separated by a distance of 1!1 in the left and right directions.

Wafer mark pair 2 adjacent to wafer mark pair 1 consists of alignment wafer marks 2a and 2b having the same shape as the alignment wafer marks 1a and lb.

Between the pair of left and right alignment wafer marks 2a and 2b,
The alignment wafer marks la and lb are spaced apart by a distance g2 which is longer than the distance g1 between them.

Further, the wafer mark pair 3 which is adjacent to the wafer mark pair 2 by force in the figure is the alignment wafer mark 1a.
, 1b and alignment wafer marks 3a, 3 having the same shape as
Consists of b. A pair of left and right alignment wafer marks 3a
, 3b are arranged at a distance [3] longer than the distance Mjl12 between the alignment wafer marks 2a, 2b.

In this way, wafer marks 1a and lb and 2a and 2b in each wafer mark pair 1 to 3 are set in advance.

Distance D1 between 3a and 3b. D2 and N3 are arranged differently in adjacent wafer mark pairs.

After setting the positional relationship as described above, the mask alignment process begins.

First, as shown in FIG. 1(A), align the square mask marks 4a and 4b with the alignment wafer marks la and lb of wafer mark pair 1, and then align the mask marks as shown in FIG. 1(B). 5a.

5b to the alignment wafer marks 2a, 2b of the wafer mark pair 2, and then sequentially align the mask marks 6a, 6b to the alignment wafer marks 3a, 3b of the wafer mark pair 3 as shown in FIG. Let's go.

During this process, if you accidentally remove the mask mark 4a.

4b is the wafer mark la which is the regular alignment position.

If the wafer marks 2a and 2b are aligned instead of wafer marks 1b as shown in FIG. 2, the deviation amounts di, d2,
Since da and d4 (FIG. 1) do not fall within the standard values, mask alignment cannot be performed and a misalignment can be detected.

After the detection, the mask marks 4a and 4b are aligned to the proper positions.

Semiconductor devices are manufactured while accurately aligning the marks in this way.

In the above example, three wafer mark pairs 1 to 3 were formed, but 2 pairs or 4 or more pairs may be formed.

And wafer mark 1 a, 1 b s 2 a
, 2b.

The shapes of 3a and 3b are not necessarily limited to square shapes.

Further, in the above example, wafer marks la, lb, 2a, 2b, and 3a in wafer mark pairs 1 to 3.

3b distance N1. N2. Although g3 are different from each other, it is sufficient that at least the distances between the wafer marks of adjacent wafer mark pairs are different.

For example, as shown in FIG. 3, the distance between wafer marks lla, llb, 13a, and 13b between the first and third or odd-numbered wafer mark pairs 11 and 13 is &! 11 and even numbered wafer marks vs. 1
2. Wafer marks 12a, 12b, 14a between 14,
For 14b comrades, the distance N 12 is made equal, and the distance N
11 and the distance Ill 12 may have different lengths.

[Effect of the invention] According to the invention, between adjacent wafer mark pairs,
Since the alignment wafer marks that make up each pair are formed at different distances from each other, incorrect mask mark alignment can be easily detected and manufacturing of defective semiconductor devices can be prevented. It can be prevented.

[Brief explanation of the drawing]

Figures 1 to 3 relate to this invention; Figures 1 (A) to (C) are top views showing the mask alignment process step by step; Figure 2 shows a state in which mask marks have been incorrectly set; FIG. 3 is a plan view showing another example, and FIG. 4 is a plan view showing a step-by-step mask alignment process in a conventional example. Above 1 to 3... Wafer mark pair, la, lb, 2a, 2bs 3a, 3b alignment wafer mark, 11 to 14 Wafer mark pair, 11a, llb, 12a, 12b, 13a 13b, 14
a, 14b...Wafer mark for alignment and above Applicant: Seikosha Japan Precision Circuits Co., Ltd.

Claims (1)

[Scope of Claim] A method for manufacturing a semiconductor device in which a pair of wafer mark pairs is selected for each mask alignment process from among a plurality of alignment wafer mark pairs formed on a semiconductor wafer, A method of manufacturing a semiconductor device, characterized in that the distance between the wafer marks in each of the wafer mark pairs is formed to be different for adjacent wafer mark pairs.