JPH0442553A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a transistor of test pattern enabling accurate measurement of threshold characteristics, in case that a plasma nitride or plasma nitride and oxide film are formed as the final protection film, by providing a structure in which a gate electrode and a third region are electrically connected. CONSTITUTION:The numeral 7 denotes a P type diffused layer formed within an N type well as a second region, namely a third region having a second conductivity type formed within the second region. The numeral 12 denotes a wiring for electrically connecting a wiring for a gate electrode 8 and a wiring for the P type diffused layer 7 formed within the N type well as the second region 3. This structure is provided within a transistor of test pattern for confirming the basic characteristic. Thereby, even when a plasma nitride is formed or a double-structured layer of an oxide film and plasma nitride is formed as the final protection film, such characteristic irregularity that a threshold voltage of a transistor of the P channel becomes high for the target value but that of the N channel becomes low and fluctuation becomes large can be prevented perfectly.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an MIS type semiconductor device.

[Conventional technology]

In a general M-type S-type semiconductor device, the gate electrode of a transistor formed in a first region consisting of a semiconductor substrate or well having an impurity of a first conductivity type is formed in the first region depending on the intended circuit. It is electrically connected to a semiconductor substrate or well containing impurities of a conductivity type or a second conductivity type.

However, in semiconductor devices, in test patterns that are set up separately from integrated circuits to check basic characteristics such as transistor characteristics and various resistance values, the gate electrode is in a floating state, that is, it is not connected to the substrate or well. It is common that this is not done.

[Problem to be solved by the invention]

In the conventional test pattern provided for checking basic characteristics, when plasma nitride or a double layer of oxide film and plasma nitride is formed as the final protective film, the threshold voltage, C characteristics,
Variations in subthreshold characteristics, etc. are known. In particular, with regard to the threshold voltage of the transistor, abnormalities tend to occur, such as the P channel being higher than the target value and the N channel being lower than the target value, and the variation becomes large. The cause of this is thought to be the influence of charging by hydrogen ions during devotion of plasma nitride. The unique feature is that the threshold voltage of the transistor is measured before the final protective film is formed. and all (
The characteristics of the semiconductor integrated circuit are completely normal even though the threshold voltage is abnormal after the final protective film is formed. From this, it can be said that although the threshold voltage in a semiconductor integrated circuit is normal, the threshold voltage becomes abnormal only in the conventional test pattern provided for checking basic characteristics. In mass production processes, the result of this threshold voltage is used to determine whether lofts or wafers pass or fail, which poses a major problem in that pass/fail decisions cannot be made. This invention was made to solve the above problems, and its purpose is to enable accurate threshold voltage measurement when plasma nitride or plasma nitride and oxide film is formed as the final protective film. It provides a test pattern transistor structure.

[Means to solve the problem]

A semiconductor device according to the present invention includes: a first region made of a semiconductor substrate or well having impurities of a first conductivity type;
a source/drain region having an impurity of a second conductivity type opposite to that of the conductivity type; a gate electrode formed above the first region between the source/drain; and a gate electrode formed outside the first region. A semiconductor device comprising a second region made of a well or a semiconductor substrate having a first impurity, and a sixth region formed in this second region and having a second conductivity type. The above problem is solved by adopting a structure in which the first and fifth regions are electrically connected.

〔Example〕

One embodiment of the present invention will be explained using a characteristic diagram of FIG. 1, which is a characteristic diagram applied to the method of the present invention, taking as an example a P-channel transistor formed on a P-type semiconductor substrate. 1 in Figure 1 is P
1 is a type semiconductor substrate, and numeral 2 in FIG. 1 is an N-well formed on this substrate, a first region having a first impurity as described in the claims. 3 in FIG. 1 is an N-well, a second region having a first impurity formed outside the first region described in the claims. 4 in FIG. 1 is an N well potential N well formed in the first region.
It is a type diffusion layer. 5 and 6 in FIG. 1 are P-type source and drain regions formed in the N well, that is, source and drain regions that are formed in isolation from each other in the first region and have second conductivity type impurities. . Reference numeral 7 in FIG. 1 is a P-type diffusion layer formed in the N-well which is the second region, that is, a sixth region formed in the second region and having the second conductivity type. 8 in FIG. 1 indicates the first
This is the gate electrode formed above the region. 9 in Figure 1
．． 10 and 11 are wirings for N-well potential, source potential, and drain potential, respectively.

Reference numeral 12 in FIG. 1 is a wiring that electrically connects the gate electrode wiring and the P-type diffusion layer wiring formed in the N well, which is the second region. By providing this structure in the transistor of the test pattern for checking basic characteristics, even if plasma nitride or a double-layer film of oxide film and plasma nitride is formed as the final protective film, the threshold voltage of the transistor as described above can be maintained. P for the value of
The channel is set high, the N-channel level is set low, and it is possible to completely prevent characteristic abnormalities such as large variations in characteristics. In this invention, a P-channel transistor formed on a P-type semiconductor substrate has been used as an example. Also, although an N-well has been explained as an example of the first region having impurities of the first conductivity type, it is applicable not only to wells but also to semiconductor substrates having the first impurity. , specifically, it is also applicable to the case where an N channel is formed in an N substrate and a P channel is formed in a P substrate.Also, in the second region having the first impurity, in this invention, N
Although the description has been given using a well as an example, the present invention is not limited to wells, and is similarly applicable to all substrates having a first impurity.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a first region including a semiconductor substrate or a well having impurities of a first conductivity type, and a first region formed in isolation from each other in the first region. a source/drain region having an impurity of a second conductivity type opposite to that of the source/drain region, a gate electrode formed above the first region between the source/drain, and a first region formed outside the first region. In the semiconductor device, the gate electrode and the sixth region are formed in the second region and have the second conductivity type. By providing a semiconductor device characterized in that regions are electrically connected, it is possible to eliminate the problem of transistors that occur when a plasma nitride film or a double layer film of a molten film and a plasma nitride film is formed as the final protective film. It is possible to completely prevent characteristic abnormalities such as the threshold and voltage being higher for the P channel and lower for the N channel with respect to the target value, and having large variations.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing one embodiment of a semiconductor device of the present invention. 1--...P-type semiconductor substrate 2...N-well region 3...N-well region 4--...For N-well potential N-type diffusion layer 5.
--- P-type source region 6 --- P-type drain region 7 ---
...P-type diffusion layer 8 formed in the N well...
--- Gate electrode 9 --- Wiring 10 for N-well potential ---
−・Wiring 11 connected to the P-type source region−・−・−・
Wiring 12 connected to the P-type drain region...-
... Wiring that electrically connects the wiring for the gate electrode and the wiring for the P-type diffusion layer formed in the N-well No. 10

Claims (1)

[Claims] A first region consisting of a semiconductor substrate or well having impurities of a first conductivity type; and a second region of a semiconductor substrate or well having impurities of a second conductivity type opposite to the first conductivity type formed in the first region in isolation from each other. Consisting of a source/drain region having an impurity, a gate electrode formed above the first region between the source/drain, and a well or semiconductor substrate having a first impurity formed outside the first region. A semiconductor device comprising a second region and a third region formed within the second region and having a second conductivity type, the semiconductor device having a structure in which the gate electrode and the third region are electrically connected. A semiconductor device characterized by: