JPH0442169A - Ion recording head driving circuit of image forming device - Google Patents

Abstract

PURPOSE:To speed up image formation and output and increase the picture quality by switching a DC high-voltage power source by a high-speed switching semiconductor element with high dielectric strength. CONSTITUTION:Gate driving circuits 421-4220 drive the gates of switching circuits 431-4320 of electrostatic induction type transistors (TR) according to input signals LIN1-LIN20 to put the switching circuits 431-4320 in operation. Further, those switching circuits 431-4320 are supplied with a voltage from a common DC high- voltage power source 44 and the respective switching circuits 431-4320 are connected to respective line power sources 121-1220 of the ion recording head 11. In this constitution, a stable and equal burst-shaped high-frequency high voltages can be supplied to any line electrode in the ion recording head and an image of high quality with no irregularity can be outputted.

Description

[Detailed Description of the Invention] U Field of Industrial Application] This invention relates to an ion recording head drive circuit for an image forming apparatus, and in particular to a circuit for applying high frequency and high voltage to an ion recording head that forms an electrostatic latent image corresponding to image information. The present invention relates to an ion recording head drive circuit for an image forming apparatus.

[Prior Art] Among conventionally used image forming apparatuses, it is known that there is an ion flow type image forming apparatus that outputs image information using an ion recording head as an ion generating means to form an electrostatic latent image. ing.

Such an image forming apparatus is disclosed in, for example, Japanese Patent Application No. 59-279.
It is disclosed in Publication No. 084.

That is, an ion recording head equipped with an ion flow generation device projects an ion flow modulated in accordance with an image signal to be recorded onto a dielectric drum rotating in a predetermined direction in a dot shape to form an electrostatic charge image. , this is developed with a developing device to form a toner image.

Next, this toner image is transferred and fixed onto the recording paper by the pressure of a pressure transfer roller. In addition, the toner image remaining on the dielectric drum without being transferred to the recording paper is removed by a toner removal device, and then the static charge on the dielectric drum is removed by a static eliminator, and a new electrostatic charge image is created. Prepare for formation.

On the other hand, the recording paper is transported from the paper feed tray outside the image forming apparatus to the transfer unit by a separation roller and a paper feed roller, and after being transferred and fixed, it is transported to the external paper ejection tray by a paper ejection roller. It has become.

FIG. 23 is a diagrammatic plan view showing the configuration of the above-mentioned ion flow type ion recording head.

The recording head 11 includes three types of electrodes that are insulated from each other. That is, for example, 20 line electrodes 12 (12122, -1
220) and these line electrodes 12 (12°] 22, .
・ J, 22 o) are arranged diagonally across the line electrode and have small holes 13 in the part facing the line electrode.
For example, 124 finger electrodes 13 (13
+13°, . . . 13+24 ) and a screen electrode 14 which is arranged at the ±force of these finger electrodes and has a small hole 14a formed at a position opposite to the small hole 13a made in the finger electrode 13. ing.

FIG. 24 shows a partial cross section of the ion recording head facing the dielectric drum described above and the configuration of the drive circuit for this ion recording head.

1, a negative bias Vsc (for example, -600V) is applied to the screen electrode 14 provided at a position facing the dielectric drum 15, and a positive bias VSC is applied to the negative bias VSC (for example, -600V). Bias vbb (200
V ) is applied. And this positive bias vbb
Negative bias Vf (161200V~250V
) or come to exist. Also, the positive bias v
A high frequency power source for ion generation Vrf (
For example, 2.5KVpp, 1MHz) is connected.

Further, the bias voltage Vbb having the above voltage is connected to the connection terminal a of the switch J6, the negative bias r is connected to the connection terminal S of the switch 16, and the finger electrode I3 is connected to the switching terminal C of the switch 16.

Here, when the high frequency power supply Vrf for ion generation connected to the line electrode 121 is operating, the switch)
When switching terminal C of 6 is switched from connection terminal a side to b side,
Since the blocking electric field that was blocking negative ions disappears, the ions that were present near the finger electrode 131 or the small holes 14
It flows out to the dielectric drum 15 through a. This results in
An electrostatic latent image is formed on the dielectric drum 15. Therefore, by selectively energizing the line electrodes 12 + 122 . . . 122° and the finger electrodes 13° I32, . can.

FIG. 25 schematically shows the relationship between the ion flow emission position formed on the recording head 11 and the dot pattern formed on the recording paper. According to this, a dot line is made up of 2480 dots, and the number of lines on one screen varies depending on the length of the recording paper, but 10 or more dot lines are formed per one screen.

The interval between the small holes made in each finger electrode 13,
That is, the spacing between the line electrodes 12 is equal to four dot lines. Figure 26 shows the line electrode 12 and finger electrode 13.
In the timing chart of the signal applied to the line electrode I2, for example, as mentioned above, the voltage applied to the line electrode I2 is at its peak.
Peak value is 2500V.

It is an alternating current voltage having a burst voltage waveform with a frequency of IMIIz, and the voltage applied to the finger electrode 13 is 20
It is a DC voltage of 0■. Further, the application time of these voltages was approximately 6 μSeC.

First, the first line electrode 12. A voltage is applied to the first
A voltage corresponding to the image data on the dot line is simultaneously applied to the first to 124th finger electrodes 131 to 13124. Each finger electrode 13 has 20
Since it is in charge of recording dots, the 1st, 21st, 41st, . . . , 2461st dots on the first dot line
Image information for each dot is recorded at the same time. That is, in the case of a black dot, the corresponding finger electrode 13 is
A DC voltage of V is applied, and in the case of a white dot, no voltage is applied to the corresponding figure pole.

Next, an AC voltage is applied to the second line electrode 12□ after a period of 6.8 μsec, and the finger electrode 1
31 to 13124 are the second and second dots on the fifth dot line.
2, 42nd, . . . DC voltage is applied corresponding to the image information of the 2462nd dot. The images of the 1st, 21st, 41st, . . . , 2461st dots on the fifth dot line are formed by the lines corresponding to the dot lines on the recording paper being connected to the first line electrode 12. It has already been recorded four cycles before the opposite one. Then, the same operation is performed on the 20th line electrode 12□. I'll wait.

When an AC voltage is applied to the 20th line electrode 122o, the 20th, 40th, . . .
A DC voltage is applied to the finger electrodes 13 to 13□24 in accordance with the image information of the 2480th dot, and the dot on the line of the recording paper corresponding to this dot line is
All will be formed.

In this way, the first line electrode 12. to the 20th line electrode 12□. The time required to scan the bar is (6+6.
8) X20=256μSee. And then 2
After a period of 54 μsec, the above-described operation is repeated again. Therefore, one period T is 256+254=510
μsec, and in the 13th period of this period, the recording paper was 89 lbs.
The vehicle travels downward for 42 minutes as shown in the direction of arrow A in FIG. 25. Therefore, the time it takes to completely form one dot line is 519x77-
It becomes 39,270 μsec. In the next cycle,
While an alternating current voltage is applied to the first line electrode 12,
1st, 21st, etc. on the newly recorded Tosotline
- Direct current voltage is selectively applied to the first to 124th finger electrodes 131 to 13124 according to the image information of the 2461st dot.

Next, an AC voltage is applied to the second line electrode 122, and the finger electrodes 131 to 13124 are provided with image information corresponding to the second, 22nd, 42nd, . . . , 2462nd dots on the fifth dot line. A DC voltage is applied.

Thereafter, similar recording was performed using the 20th line electrode 12□. When an AC voltage is applied to the finger electrodes 13□ to +3124 in accordance with the image information of the 20th, 40th, . . . , 2480th dot on the 76th dot line. As a result, recording is completed only on the 76th dot line. In this way, an image consisting of a large number of dot lines is formed by repeating the sequential operations.

In an image forming apparatus using such a recording head, a predetermined write electrode is selected in the sequence described above according to an image signal transmitted from an image data generating device, and a 2500 Vpp, A driver circuit for ion recording is required that is capable of applying an I Mtlz-like voltage waveform.

FIG. 27 is a block diagram of such an ion recording head drive circuit and its peripheral parts. In the figure, a code (1) output from an image generating section 16 such as a host computer is input to a character generator 17 and converted into a video signal.

According to this video signal, the deskew circuit 18 selects which electrode should generate ions, and outputs a 5-bit parallel signal representing the corresponding line electrode 12 at a timing corresponding to the video signal.

Based on this 5-bit parallel signal, the decoder 20 in the line drive circuit 19 decodes the line electrodes 12 (12, . . .
12°. ) corresponding to the oscillation circuit 21 (2L~2+20
) input the enable signal. Then, by this enable signal, 2500 Vpp is applied to the line electrode 12.
A burst voltage of I Mllz is applied for ion generation. Further, from the deskew circuit 18,
A signal is similarly output to the finger drive circuit 22 in order to apply a DC voltage to the finger electrode 13.

FIG. 28 shows the oscillation circuit 21 (
211 to 2120) shows a circuit diagram of one of the circuit sections. When the input signal LENO from the decoder 20 is input to the input terminal 23 of the oscillation circuit 21, it is transmitted to the transistor Q via the resistor R1 connected to the power supply CC (not shown), the resistor R2 of the parallel circuit, and the capacitor CI.
] will be entered. At this time, when transistor Q1 is turned on, a voltage is supplied to resistors R3 and R4, transistor Q2 is turned on, and collector current of transistor Q2 begins to flow.

Incidentally, the lie>electrode 12 connected to the transformer T1 is electrically equivalent to a substantially pure capacitor CL. Once this is done, an LC resonant circuit is formed that resonates at a frequency f=1/(2πJ1〒). However, R2 represents the secondary inductance of the transformer T. Therefore, by applying positive feedback through the capacitor C2 between the primary winding TI of the transformer T1, which is a part of this LC resonant circuit, and the emitter of the transistor Q2 and the emitter resistor R5, this circuit can be used as an oscillation circuit. It continues to work. Thereafter, when the signal LENO is no longer input to the input terminal 23, the transistor Q1 is turned off and oscillation is also stopped. These input and output signals are shown in FIG. That is, the input signal LENO is oscillating on the n-th line, but when the oscillation on the n-th line ends, oscillation starts on the (n+1)-th line next.

The reason why an oscillation circuit made up of a transistor and a transformer and resonating with the line capacitance 5i CL is used is because there was no switching element that could directly switch 2500V at IMHz. Therefore, conventionally, a transistor for 1M1lz oscillation and a transformer for boosting and resonance have become essential components.

[Problem to be solved by the invention] By the way, within one page of recording paper on which an electrostatic latent image is formed,
In order to obtain a uniform image without unevenness, uniform output (V rf) is required for all line electrodes. However, the transistors that constitute the above-mentioned oscillation circuit, especially the transistor Q2, the transformer T], the feedback capacitor C2,
Due to variations in circuit components such as emitter resistor R5, output voltage (V rr), rising edge, falling edge, output frequency,
It is difficult to make uniform the fluctuation characteristics of the output voltage (V rf) when the load fluctuates. Therefore, we decided to adjust the output voltage by inserting a variable resistor Rv into the primary side of the transformer T1, and by managing the component characteristics for other characteristics, we could achieve some degree of oscillation for each line. I try to match the circuit characteristics.

In this way, it is possible to obtain an image with a somewhat uniform density. For this reason, this variation in output is an obstacle to achieving high image quality.

In this way, conventionally, 250
Since there was no semiconductor element capable of switching at 0V and 1MHz, it was constructed with a transistor and a step-up/resonant transformer. For this reason, when an oscillation circuit that resonates with the capacitance of the line electrode is used, the following problems occur.

(1) It is difficult to speed up image formation and output.

First, is it possible to increase the frequency of the 8 voltages to increase the speed? However, increasing the frequency would reduce the efficiency, so it would be difficult. In order to increase the frequency, the line electrode capacitance is fixed when using the above resonant circuit, so the secondary inductance of the transformer must be reduced.

However, due to the limited voltage resistance of transistors,
The number of turns of the transformer, which must maintain a constant step-up ratio (primary/secondary turns ratio), cannot be easily reduced. Therefore, in order to reduce the inductance of the transformer, it is necessary to increase the magnetic resistance of the transformer core, and the efficiency decreases accordingly. Another problem is that, as shown in FIG. 29, it takes several microseconds for the output voltage to rise and fall.
For this reason, in addition to the time for ion generation, rise and fall times must be ensured, and the on-time of the output circuit and the time until the n+1th line is turned on after the nth line are not sufficient. can only be shortened. Therefore, extra time that does not contribute to ion generation is required, which is an obstacle to increasing the speed.

(2) Due to variations in the components of each oscillation circuit, especially variations in transistors, transformers, feedback capacitors, etc., the output voltage (Vrr), rise, fall, output frequency,
The output characteristics when the capacitance of the line electrode, which is the load, changes varies depending on the circuit connected to each line electrode. For this reason, the amount of ions generated for each line is not uniform, and there is a problem in that it is difficult to obtain a high quality image because it is impossible to obtain a uniform image without unevenness.

(3) In order to correct the variations in each component shown in (2) above to some extent, it is possible to improve the characteristics by adjusting the output voltage with a variable resistor or by selecting the components used. These operations require man-hours.

(4) Since a transformer is essential, it is difficult to miniaturize because hybridization, chipping, high frequency magnetic shielding, etc. are also required from the viewpoint of EMI countermeasures.

(5) When using a transformer, the core of the transformer is extremely fragile and difficult to handle, making it difficult to improve reliability.

(6) The output voltage tends to change as the temperature of the transistor increases and is unstable with respect to temperature. For this reason, the density of the image may differ between the first part and the last part outputted to the recording paper.

This invention was made in view of the above-mentioned points, and it is possible to speed up the image formation output, and also to obtain a uniform image without unevenness caused by variations in each component and to improve the image quality. It is an object of the present invention to provide an ion recording drive circuit for an image forming apparatus which is compact and has improved reliability with respect to components and temperature, without requiring extra man-hours.

[Means for Solving the Problems] That is, the present invention provides a burst-like high-frequency, high-voltage signal that is generated at a timing corresponding to image information according to human-generated image information to form an electrostatic latent image on an image carrier. drive circuit means for selectively outputting the electrostatic latent image, and a drive circuit means for forming the electrostatic latent image on the image carrier based on the high frequency high voltage signal output from the drive circuit means, the electrostatic latent image being formed in a first direction. a plurality of first electrodes, and a plurality of small holes that are formed in a second direction different from the first direction so as to face each other via a dielectric with the first electrodes, and generate ions in the vicinity thereof; In the image forming apparatus, the drive circuit means includes a high-speed high-voltage switching means for switching the high-frequency high-voltage signal at high speed; a passive element connected to the high-speed high-voltage switching means; a DC high-voltage power supply means connected to the passive element for supplying high voltage to the high-speed high-voltage switching means; signal input circuit means for supplying a time-specific frequency signal, the first electrode of said ion recording head being electrically connected directly to said drive circuit means.

[Function] In the ion recording head drive circuit of the image forming apparatus according to the present invention, according to the image information generated by the image information generating means, a burst-like high frequency high voltage signal generated at a timing corresponding to the image information is transmitted to the drive circuit means. is selectively output. In this drive circuit means, a high voltage is supplied from the DC high voltage power supply means to the high speed high voltage switching means for switching high frequency high voltage signals at high speed through the passive element. Further, a specific frequency signal is supplied to the high-speed high-voltage switching means from the signal input circuit means in a predetermined sequence for a certain period of time. a plurality of first electrodes formed in a first direction and electrically directly connected to the drive circuit means based on the high frequency high voltage signal output from the drive circuit means; This first electrode and a second electrode are formed opposite to each other via a dielectric material and are formed in a second direction different from the first direction, and have a plurality of small holes formed in the vicinity thereof for generating ions. The electrostatic latent image corresponding to the image information is formed on the image carrier by the ion recording head means.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 7 shows an image forming apparatus to which an ion recording head drive circuit of an image forming apparatus is applied according to an embodiment of the present invention. In the following embodiments, the same parts as in FIGS. 23 to 29 are given the same reference numerals.

In the same figure, an ion recording head 1 is equipped with an ion flow generation device on a dielectric drum 15 that rotates in the direction of arrow B in the figure.
1, an ion flow modulated in accordance with the image signal to be recorded is projected in a dot shape to form an electrostatic charge image. Then, the electrostatic charge image formed on the dielectric drum 15 is developed with toner by a developing device 24 to form a toner image.

Next, this toner image is transferred to the recording paper by the pressure of a pressure transfer roller 26, which is disposed below the conveyance path of the recording paper 25 and rotates in the direction of arrow C in the figure following the rotation of the dielectric drum I5. The image is transferred and fixed onto 25. Here, recording paper 2
The toner image remaining on the dielectric drum 15 without being transferred to the toner image 5 is removed by a toner removing device 27 having a cleaning blade. Thereafter, the dielectric drum 15 from which the static charge has been removed by the static eliminator 28 is ready for the formation of a new static charge image.

On the other hand, the recording paper 25 is stored in a paper feed tray 29 outside the image forming apparatus.
The paper sheets are stacked and stored in the paper feed tray 29, and are separated one by one by a separation roller 30, and transferred to the paper feed roller 31.
The image is conveyed to the transfer section by. The recording paper 25 on which the toner image has been transferred and fixed in the transfer section is conveyed by a paper discharge roller 32 and is sequentially stacked on an external paper discharge tray 33.

The pressure transfer roller 2G is pressed against the dielectric drum 15 with a large pressure of 1 ton, for example, by a spring and a cam. Further, the axis of the dielectric drum 15 and the axis of the pressure transfer roller 26 intersect at a certain angle.

Therefore, the recording paper 25 is conveyed between the dielectric drum 15 and the pressure transfer roller 2B while being skewed.

FIG. 1 shows a block diagram of a circuit for driving the ion recording head 11. As shown in FIG. The configuration of the ion recording head has been described in detail in the conventional example and FIG. 23, so the explanation will be omitted here.

In Figure 1, an image generating unit I of a host computer, etc.
The code signal outputted from 6 is inputted to galactage generator 17 and converted into a video signal. According to this video signal, the deskew circuit 18 selects the electrode that should generate ions, and selects the corresponding line electrode 12 at the timing corresponding to the video signal.
A 5-bit line selection signal LSEL consisting of 4 bits is output to the line drive circuit 34, and a finger selection signal is output to the finger drive circuit 22. The line drive circuit 34 includes the line selection signal LSEL.
At the same time, a signal LEN (pulse width 6 μsec, 12.8 μS) indicating the timing of applying voltage to the line electrode 12
eC cycle) or according to the image information signal to be output from the deskew circuit 18.

A line selection signal QLSEL is inputted to the decoder 36 from one input terminal 35 of the line drive circuit 34, and outputs 5ELI to 5EL20 based on this signal LSEL.
One of the 20 wires is selected and a logic level "high" is output. And output 5EL
I～”S E L 20 is Nantes Gate 3L-37
It is connected to one input terminal of 2o.

In addition, another input terminal 3 of the line drive circuit 34
8, the timing signal LEN is manually inputted.
This timing signal LEN is input to the synchronous clock generation section 39 and the input terminal of the inverter 40. The synchronized clock generating section 39 is constituted by, for example, a well-known phased lock loop (PLL) circuit, and generates a tarok of about IMllz synchronized with the timing signal LEN. The output of the synchronized clock generation section 39 and the output of the input gate 40 are respectively connected to the AND gate 41.
connected to the input terminal of And this and gate 4
The output of 1 is connected to the other input terminal of the above-mentioned Nandt gates 371-372°.

Nantes Gate 37. The outputs of ~372o are connected to gate drive circuits 421~422o. These gate drive circuits 421 to 4220 drive the gates of the electrostatic induction transistor switching circuits 431 to 43□0 according to the human input signals LINI to LI N20, and these switching circuits 43. ~43□. I am trying to make the circuit work. Further, these switching circuits 43□ to 43□0 are supplied with voltage from a common DC high voltage power supply 44, and each switching circuit 431 to 432o is connected to each line electrode 121 to 12 of the ion recording head 11. □. It is connected to the.

FIG. 2 shows a partial cross section of the ion recording head facing the dielectric drum and the gate drive circuit 42 in FIG.
1 shows the circuit configuration of the switching circuit 43□ and the bias power supply. Note that here, the gate drive circuit 42. Since the switching circuit 43□, other gate drive circuits, and switching circuits have similar configurations, their explanations will be omitted.

The input terminal 45 of the gate drive circuit 42 has an intermittent input signal L Iz to the Nantes gate 37□.
N or 1 can be input. This intermittent human power signal LINI is input to the base of transistor Q3 via resistor R6. The emitter of transistor Q3 is connected to the positive terminal of gate bias power supply V61 and the collector of transistor Q4.

Further, the collector of the transistor Q3 is connected to the gate bias power supply VC2 via the resistor R7 and the base and collector of the transistor Q5. The bases and emitters of the transistors Q4 and Q5 are connected to each other, and the emitters are connected to the gate of the electrostatic conduction type transistor Q6. Furthermore, the negative pole of the gate bias power supply VG1, the positive pole of the gate bias power supply Vc2, and a DC high voltage are connected to a source 44 (for example, output +2500
The negative electrodes of V) are both connected to the source of the electrostatic induction transistor Q6. The drain of this static induction transistor Q6 is connected to the DC high voltage power supply 4 through a resistor R8.
4 and to the line electrode 12+ of the ion recording head 1.

The screen electrode 14 facing the dielectric tram 15 has a screen bias s lfi V sc (output car 6
00V) is applied, and the negative pole of the reverse bias power supply Vbb is connected to the negative pole of the screen bias power supply VSC. And this reverse bias power supply V
The positive electrode of bb is connected to the source of static induction transistor Q6. Furthermore, the positive pole of the reverse bias power supply Vbb is connected to its negative pole or to the positive pole of the forward bias power supply V connected to the connection terminal a of the changeover switch 46, and the changeover switch 46
It is connected to the connection terminal. In addition, the changeover switch 46
The other connection terminal C is connected to the finger electrode 131.

The changeover switch 46 switches the connection terminal aSb according to the image data to be printed in response to a finger selection signal from the deskew circuit 18 (not shown), and switches the connection terminal aSb to the finger electrode 13. This is to switch the bias applied to the The outputs of the reverse bias power source V- and the forward bias power source v0.degree. are made variable within the range of, for example, 100 V to 300 V, thereby making it possible to adjust the ion flow rate.

By the way, the ion recording head 11 which is an ion generating means
The drive circuit for the ion recording head that selectively applies burst-like high-frequency high voltage to the plurality of line electrodes 12 is based on transistors and step-up voltages because there was no conventional circuit capable of switching 2500 V with IMH2 as described above. It used an oscillation circuit using a dual-resonant transformer.

The electrostatic induction transistor Q6 is a semiconductor element that enables switching in this state, and for example,
It has a withstand voltage of 0V or more and can perform switching at IMHz.

FIG. 3 is a sectional view showing the structure of such a static induction transistor. That is, since the gate is shorter than that of a field effect transistor, its distribution capacitance icgch is small, and the channel length is also short, so the channel resistance r is small, and therefore the time constant r,·Cgch is small.

Therefore, the switching speed can be increased.

On the other hand, it has a structure in which current flows vertically with respect to the drain electrode, source electrode, and substrate, and it is a multi-channel type that has many channels through which current flows compared to conventional field effect transistors, so it can handle large currents and small It is possible to increase the internal resistance, and since it is vertical, it is easy to increase the withstand voltage.

By using a semiconductor device such as the one shown in FIG. By applying this, ions are generated in the recording head. In order to generate this 2500 V, IMHz, one switching circuit is connected to each line electrode 12 of the ion recording head 11, so that the DC high voltage power supply 44 is common to all circuits. .

Next, the operation of this first embodiment will be explained.

0~ transmitted from the deskew circuit 18 in FIG.
The decoder 36 selects one of the outputs 5ELI to 5EL20 according to the 5-bit line selection signal LSEL consisting of
Select one. Then, Nantes Gate 37,~37□.

A logic level "high J" is input to the selected Nantes gate 37, ~37.

Open only one of the gates. At this time, the synchronous clock generation section 39 generates a clock of about IMHz that is synchronized with the timing signal LEN that is synchronized with the line selection signals LSEL 0 to 4.

When the output of the synchronized clock generator 39 and the inverted signal of the timing signal LEN are input to the AND gate 41, when the timing signal LEN is "low", t:
An IMHz clock is output from the AND gate 41 and supplied to the NAND gates 37 and 372 degrees.

By the way, since there is only one gate open by the above line selection (Eli LSELO~4), in this case 2
There are 0 gate drive circuits 42□ to 42□. Only one of the gate drive circuits is supplied with an input signal.

FIG. 4 is a timing chart showing each of these signals and outputs.

The timing signal LEN has a pulse width of approximately 6 μsec and a pulse width of 1
This signal has a period of 2.8 μse.

For example, all line selection signals LSELO~4 are "low"
At this time, only the Nant gate 371 is selected by the decoder 36 and opened. Here 1. IMHz intermittent signal synchronized with timing signal LEN (output of AND gate 41)
Or, the input signal LIN is applied only to the gate drive circuit 421.
It is entered as I. Similarly, line selection signal LS
When ELO or "high" and LSELI ~ 4 or "low",
The gate is opened only to the gate drive circuit 422. In this way, from the gate drive circuit 421 to the gate drive circuit 422o, the human input signals LIN1 to LIN1 to
20 is applied. And gate drive circuit 422
After the input signal LIN20 is input to ° (manual signal LI
256 μsec after NI was input manually), line selection No. 16 LSELO~4 are all in the "high" state for 254 u 5eeO. At this time, decoder 3
6 is selected (all outputs of r1 No. 5ELI to 20 are set to "low", and all Nantes gates 371 to 37°0 are closed. After this (5 after starting to output the input signal LINI)
After 10 μSeC), line selection signals LSEL1 to LSEL4 are applied again.
all return to the "low" state.

Thereafter, the above-mentioned operation is repeated.

By the way, when the line selection signals LSELO~4 are all in the "low" state, when the input signal LINI is input to the input terminal 45 shown in FIG. is applied to As a result, the transistor Q4 performs a switching operation, and the gate bias VG1 is applied to the bases of the transistors Q4 and Q5 in phase with a signal obtained by inverting the input signal LINI.
and VO2 are applied alternately. Thereby, transistors Q4 and Q5 operate as push-pull amplifiers. Then, at the gate of the electrostatic reading transistor Q6,
Gate bias ■ when input signal LINI is "high".

2 is applied, and when the human input signal LINI is "low", the gate bias -G is applied. The four static induction transistors Q6 operate in depletion mode, so they turn off when the input signal LINI is "high".
Turns on when the input signal LINI is "low". When the electrostatic induction transistor Q6 is off, the output of the DC high voltage power supply 44 is applied to the line electrode 121. on the other hand,
When the electrostatic induction transistor Q6 is on, the output of the DC high voltage power supply 44 is voltage-dropped by the resistor R8 and is not applied to the line electrode 12.

5(a) and 5(b) show the input signal LINI of the gate drive circuit 42 and the line voltage t>12. f: indicates the waveform of the applied voltage Vrf. In this way, by switching the DC high voltage using the electrostatic induction transistor Q6, a voltage waveform of 2500 Vpp and IMHz capable of generating ions can be obtained. Then, the output waveform of this circuit is transferred to the line electrode 121.
By applying ions to the small hole 13a near the finger electrode 13+, ions can be generated in the small hole 13a near the finger electrode 13+.

Here, if the changeover terminal C of the changeover switch 46 is switched to the connection terminal side, the small hole 13a and the screen electrode 14
An ion flow blocking electric field is formed within 14a. Therefore, the ion flow does not pass through the small holes 14a and reach the dielectric drum 15. On the other hand, when the changeover terminal C of the changeover switch is switched to the connection terminal a side, the blocking electric field disappears, so that the ion flow (negative ions) reaches the dielectric drum 15. Therefore, it becomes possible to control the ion flow.

With the circuit configured in this way, it is possible to supply a stable and equal burst-like high frequency high voltage to any line electrode in the ion recording head, outputting an even and high quality image. be able to. This is the output voltage or the output of a DC high voltage power supply, and the output frequency is uniquely determined by the frequency of the input signal to the electrostatic induction transistor switching circuit. For this reason, the rise and fall of the output waveform are sufficiently fast, similar to the switching speed of the electrostatic induction transistor, so as shown in Figure 5(a),
It ends in a very short time. Therefore, variations in output waveforms for each switching circuit are almost eliminated. Therefore, there is no need for output adjustment parts or adjustment man-hours for each switching circuit, and there is no need for a step-up transformer, making it possible to reduce the size and improve reliability.

Furthermore, unlike self-oscillation (resonance) type circuits, static induction transistors are used for switching in the saturation region, so there is no significant output deviation due to movement of the operating point as the temperature of the semiconductor device increases. It becomes small and stable.

By the way, in order to increase the speed of printing in such an image forming apparatus, it is necessary to generate the same amount of ions in a shorter time than before the speed increase. Therefore, in order to increase the speed, it is necessary to (1) increase the output frequency, or (2) shorten the output voltage rise and fall times (margin time) that do not contribute to ion generation. Increasing the output frequency in the above item (2) can be easily achieved by increasing the frequency of the input signal to the switching circuit. On the other hand, according to the above-described first embodiment, shortening the margin time (2) is achieved by reducing the rise and fall times to approximately zero. Here, in the conventional self-oscillation method, as shown in FIG. 29, the rise and fall times require 6 μCC. Therefore, in order to prevent crosstalk, the voltage is applied to the (n+1)th line electrode after 12.8 μsec has elapsed since the start of applying the voltage to the nth line electrode. That is, at least 12.8 μsec per line.

(However, when the ion generation time was 6 μec). On the other hand, in this embodiment, as mentioned above, the margin time could be shortened and the rise and fall times could be made almost zero, so the margin time (approximately 6 μsec) was reduced compared to the conventional margin time for crosstalk prevention. becomes unnecessary. In other words, the 6th
As shown in the figure, the voltage is applied to the n+1 line electrode 6 times after starting to apply the voltage to the n-th line electrode.
It is fine after 1 μsec has elapsed. In other words, the time required for ion generation per line is only 6 μsec. Therefore, compared to the conventional self-oscillation type circuit described above, the speed can be increased by about 36%.

As described above, by using an electrostatic induction transistor in a switching circuit, it is possible to easily increase the speed of print output.

Modifications of this invention will be described below as second to eighth embodiments. Note that the same parts as in the first embodiment and the conventional example described above will be given the same reference numerals, and their explanation will be omitted to avoid duplication, and only the different parts will be explained.

FIG. 8 shows a second embodiment of the present invention, which is a modification of the circuit shown in FIG. The waveforms of the input signal LIN and the voltage Vrr applied to the line electrode 121 are shown. Gate drive circuit 42. The output of is supplied to the gate of static induction transistor Q6. In addition, a DC voltage power source 44 (Vps)
The negative electrode of the transistor Q6 is connected to the drain of the static induction transistor Q6. A resistor R8 is connected between the positive electrode of the DC voltage power supply 44 and the source of the static induction transistor Q6, and the source of the static induction transistor Q6 is connected to the line electrode 121.

In the ion recording head drive circuit having such a configuration, when an input signal LINI as shown in FIG. 9(a) is input to the gate drive circuit 42, the electrostatic induction transistor Q6 switches. As a result, Figure 9 (
250 between V bb and -Vps as shown in b)
An output voltage of 0V can be obtained.

Further, FIG. 10 shows a third embodiment of the present invention, showing a partial cross section of an ion recording head and the circuit configuration of a gate drive circuit, a switching circuit, and a bias power supply. The output of the gate drive circuit 421 is supplied to the gate of the static induction transistor Q6. Further, the gate drive circuit 42. is connected to the negative electrode of the DC voltage power supply 44 (V ps) and the source of the static induction transistor Q6. And DC voltage power supply 4
A resistor R8 is connected between the positive electrode of No. 4 and the drain of the static induction transistor Q6, and the drain of the static induction transistor Q6 is connected to the line electrode 12□.

According to the drive circuit for the ion recording head having such a configuration, when the input signal LINI shown in FIG. , the static induction transistor Q6 switches, and as shown in FIG. 11(b), V
It is possible to obtain an output voltage of 2500V between bb and -Vps.

Further, FIG. 12 is a fourth embodiment of the present invention, showing a partial cross section of an ion recording head and the circuit configuration of a gate drive circuit, a switching circuit, and a bias power supply. The gate drive circuit 421 is connected to the gate of the static induction transistor Q6, and is connected to the negative electrode of the DC voltage power supply 44 (VpS) and the static induction transistor Q6.
connected to the source. A resistor R8 is connected between the positive terminal of the DC voltage power supply 44 and the drain of the static induction transistor Q6. The line electrode 12 is connected to the positive electrode of the DC voltage power source 44.

According to the drive circuit for the ion recording head having such a configuration, the input signal LINI or the gate drive circuit 42. as shown in FIG. , the electrostatic induction transistor Q6 switches as in the second and third embodiments described above.

Then, as shown in FIG. 13(b), Vps and V
An output voltage of 2500V can be obtained between bb and bb.

In this way, even with the circuit configurations shown in the second to fourth embodiments, ions can be stably generated in the ion recording head, and a high-performance ion recording head drive circuit can be realized. can be achieved.

Next, FIG. 14 shows a fifth embodiment of the present invention. The output of the gate drive circuit 42 is supplied to the gate of the static induction transistor Q6. Also,
Gate drive circuit 42. is the DC voltage power supply 44 (V
ps) and the source of the static induction transistor Q6. A resistor R8 is connected between the positive terminal of the DC voltage power supply 44 and the drain of the static induction transistor Q6.
is connected, and the drain of the electrostatic induction transistor Q6 is connected to the line electrode 12□. Further, the reverse bias power supply V bb has its negative terminal connected to the source of the electrostatic induction transistor Q6, and its positive terminal connected to the connection terminal of the changeover switch 46 and the negative terminal of the forward bias power supply (2).

In the drive circuit of the ion recording head having such a configuration, when the input signal LINI shown in FIG. 15(a) is input to the gate drive circuit 421, the electrostatic induction transistor Q6 switches. , Figure 15(b)
As shown in , an output voltage of 2500V can be obtained between Vps and VSC. In this embodiment, unlike the first to fourth embodiments described above, the screen bias power supply VSC is used as a reference unit.

Even with such a circuit configuration, ions can be stably generated in the ion recording head.

Furthermore, since a larger bias voltage is applied in the negative direction than in the first to fourth embodiments described above, more negative ions can be generated.

FIG. 16 shows a sixth embodiment of this invention.
2 is a partial cross-sectional view of an ion recording head and a circuit configuration diagram of a gate drive circuit, a switching circuit, and a bias power supply. FIG. The output of the gate drive circuit 42 is supplied to the gate of the static induction transistor Q6.

Further, the gate drive circuit 42. is the DC voltage power supply 44
(V ps) and the source of the static induction transistor Q6. A resistor R8 is connected between the positive terminal of the DC voltage power supply 44 and the drain of the static induction transistor Q6.
6 trains are connected to the line electrode 121.

Further, the reverse bias power supply Vbb has its negative terminal connected to the source of the electrostatic induction transistor Q6, and its positive terminal connected to the connection terminal of the changeover switch 46 and the negative terminal of the forward bias power supply (2). A reference bias power source Vr, -b is connected between the source of the electrostatic conductive transistor Q6 and the positive electrode of the reverse bias power source ybb.

In the drive circuit of the ion recording head having such a configuration, an input signal LINI as shown in FIG. 17(a) is used.
When the signal is input to the gate drive circuit 42, the electrostatic induction transistor Q6 switches, and as shown in FIG.
), between Vps and V, , j: 250
It is possible to obtain an output voltage of 0 V. In this embodiment, an independent reference bias power supply V, (-
B is added, allowing the output voltage to be freely set to a desired bias. Thereby, desired polar ions can be stably generated.

FIG. 18 shows a seventh embodiment of the invention.

The gate drive circuit 421 is connected to the gate of the static induction transistor Q6, the negative electrode of the DC voltage power supply 44 (V ps), and the source of the static induction transistor Q6. A resistor R8 is connected between the positive terminal of the DC voltage power supply 44 and the drain of the static induction transistor Q6, and the drain of the static induction transistor Q6 is connected to the line electrode 12 through the coupling capacitor CA. It is connected to the. The reverse bias power supply V bb has its positive pole connected to the source of the static induction transistor Q6, and its negative pole connected to the negative poles of the screen bias power supplies V, c.

In the drive circuit for the ion recording head having such a configuration, the input signal LIN1 as shown in FIG. 19(a) is input to the gate drive circuit 42. When input to , the static induction transistor Q6 switches. according to this,
Since the switching circuit having the static induction transistor Q6 and the line electrode IL are coupled by the coupling capacitor CA, only the alternating current component is connected to the line around vbb, as shown in FIG. 19(b). Electrode 121
will be applied. This allows stable ions to be generated within the ion recording head.

FIG. 20 shows an eighth embodiment of the invention. In the figure, the gate drive circuit 42 connects the gate of the static induction transistor Q6 and the DC voltage power supply 44.
(Vps) and the source of the static induction transistor Q6. Then, a DC voltage power supply 44 (125
0V) is connected to the drain of the electrostatic induction transistor Q6 via the coil LC, and is also connected to the connection terminal of the changeover switch 46. Further, the drain of the static induction transistor Q6 is connected to the line electrode 12+
is connected to. The reverse bias power supply Vhb has its positive terminal connected to the connection terminal of the changeover switch 46 and the forward bias voltage J·λ.
(2), and its negative electrode is connected to the negative electrode of the screen bias power supply VSC.

By the way, since the line electrode I2 faces the finger electrode 13 and the screen electrode 14 via the insulating layer, it is electrically considered to be a substantially pure capacitor Cl. Therefore, if we show the equivalent circuit of the circuit shown in FIG.
It will look like Figure 22. Here, let the inductance of the coil LC be LC, and the line electrode 12. When the frequency of the voltage to be applied is f, set the coil inductance c so that the following formula holds, and connect the coil with capacitor C4. Make it resonate between the tonneaus. For example, if the desired frequency is IMHz and the line electrode capacitance is 100 pF, then from the above equation, Lc
=250 μH.

In the drive circuit of the ion recording head having such a configuration, the human input signal LINI(
When an intermittent IMHz signal is applied to the gate drive circuit 421, the electrostatic induction transistor Q6 switches. As a result, a voltage is supplied to the parallel resonant circuit composed of the coil Lc and the line electrode capacitance, and resonance is started. This causes line electrode 12.2, as shown in FIG. is a DC high voltage power supply 44 (1
250V) twice the amplitude (2XVps-Vpp-250
0V) is obtained. Thereafter, when the input signal LINI disappears, the switching of the electrostatic induction transistor Q6 ends and the output ends.

By the way, as is clear from FIG. 21(b), the output voltage of the DC high voltage power supply 44 may be 1/2 of the voltage (maximum value) applied to the line electrode 121. For example, when it is desired to apply 2500 Vpp to the line electrode 121, the output of the DC high voltage power supply 44 only needs to be 1250 V, which is half of that of the first to seventh embodiments described above. Also, during resonance, L as seen from the DC high voltage power supply 44
Since the impedance of the parallel resonant circuit of C%CL is very large, almost no current flows from the high DC power supply 44.

Therefore, in this eighth embodiment, the output voltage of the DC high voltage power supply can be made relatively small, and the current capacity of the power supply can also be set small, so that the power of the DC high voltage power supply can be made relatively small. Capacity can be reduced. Therefore, it is very important to miniaturize power supplies and reduce costs.
−+ effect. Furthermore, since the direct current high voltage is switched by a direct electrostatic induction transistor, the rise and fall times of the output can be greatly shortened.

In the above embodiment, the inductance in the resonant circuit is assumed to be only the inductance (L C) of the vibration coil, and the capacitance is assumed to be only the line electrode capacitance ff1 (Ct,). In other words, the 7f-free capacitance, stray inductance, and capacitance of static induction transistors that exist in the actual circuit are ignored. However, in actual circuits, it goes without saying that these stray capacitances must also be taken into account.

[Effects of the Invention] As described above, according to the present invention, by switching the DC high voltage power supply using a high-voltage, high-speed switching semiconductor element, it is possible to increase the speed of image formation output, and to achieve uniform output. Since the voltage is applied to the line electrodes as well, it is possible to obtain a uniform image without unevenness due to variations in each component, resulting in high image quality, and there is no need to adjust each component, which eliminates the need for extra man-hours. It is possible to provide an ion recording head drive circuit for an excitation forming device that is smaller in size and has improved reliability with respect to components and temperature.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an ion recording head drive circuit of an image forming apparatus according to an embodiment of the present invention, and FIG. 2 shows a partial cross section of the ion recording head facing a dielectric drum, and FIG. Figure 3 is a cross-sectional view showing the configuration of the static induction transistor in Figure 2, and Figure 4 is a diagram showing the circuit configuration of the gate drive circuit, switching circuit, and bias power supply. Selection signal LEN in the figure,
Line selection signal LSELO~4, synchronous clock main component output, AND gate output, input signal LINI~LIN20
and a timing chart showing each output waveform of the line electrodes 1 to 20; FIGS. 5(a) and 5(b) are waveform diagrams of the input signal LINI of the gate drive circuit of FIG. 2 and the voltage Vrf applied to the line electrode; Figure 6 shows lines 1 to 2.
A waveform diagram showing the timing of the voltage applied to the 0 line,
FIG. 7 is a schematic cross-sectional view showing an image forming apparatus to which an ion recording head drive circuit of an image forming apparatus is applied according to an embodiment of the present invention, and FIG. 8 is a gate drive circuit according to a second embodiment of the present invention. , FIGS. 9(a) and (b) are waveform diagrams of the input signal LINI of the gate drive circuit of FIG. 8 and the voltage Vrr applied to the line electrode, FIG. 10 is a diagram showing the circuit configuration of a gate drive circuit, a switching circuit, and a bias power supply in a third embodiment of the present invention, and FIG. 11 (
a) and (b) are the input signal LINI of the gate drive circuit in FIG. 10 and the voltage Vrf applied to the line electrode.
FIG. 12 is a diagram showing the circuit configuration of the gate drive circuit, switching circuit, and bias power supply in the fourth embodiment of the present invention, and FIGS. 13(a) and (b) are the waveform diagrams of the first embodiment
Figure 2 shows the waveform diagram of the human input signal LINI of the gate drive circuit and the voltage Vrr applied to the line electrode, and Figure 14 shows the circuit configuration of the gate drive circuit, switching circuit, and bias power supply in a fifth embodiment of the present invention. Figure 1
5(a) and (b) are waveform diagrams of the input signal LINI of the gate drive circuit in FIG. A4 and the voltage Vrr applied to the line electrode, and FIG. 16 is a waveform diagram of the gate drive circuit in the sixth embodiment of the present invention. 17(a) and (b) are waveform diagrams of the input signal LINI of the gate drive circuit of FIG. 16 and the voltage Vrf applied to the line electrode. , 18th
The figure shows the circuit configuration of a gate drive circuit, a switching circuit, and a bias power supply in a seventh embodiment of the present invention, and FIGS. 19(a) and (b) show input signals of the gate drive circuit of FIG. 18. A waveform diagram of the voltage Vrf applied to LINI and the line electrode, FIG. 20 is a diagram showing the circuit configuration of the gate drive circuit, switching circuit, and bias power supply in the eighth embodiment of the present invention, and FIG. 21(a) as well as(
b) is the input signal LI of the gate drive circuit in FIG.
Waveform diagram of voltage Vrf applied to NI and line electrodes,
FIG. 22 shows the equivalent circuit of FIG. 20, FIGS. 23 to 29 show the ion recording head drive circuit of a conventional image forming apparatus, and FIG. 23 shows the ion recording head drive circuit of a conventional image forming apparatus. FIG. 24 is a diagrammatic plan view showing the configuration of the head; FIG. 24 is a partial cross-section of the ion recording head facing the dielectric drum in a conventional example; FIG. 25 is a diagram schematically showing the relationship between the ion flow emission position formed on the ion recording head and the dot pattern formed on the recording paper, and FIG. Timing chart, Figure 27 is a block configuration diagram showing the gate drive circuit, switching circuit and bias power supply circuit in Figure 24, Figure 28 is one of the oscillation circuits in the line drive circuit in Figure 27. Circuit diagram showing minutes, 2nd
FIG. 9 is a timing chart of input/output signals of the line drive circuit of FIG. 27. 11... Ion recording head, 12.121.122,
...1 '220-line electrode, 13.13.132
・"13124...Finger electrode, 14...Screen electrode, 15...Dielectric drum, 16...Image forming section, 17...Character generator, 18.
... Deskew circuit, 22 ... Finger drive circuit, 34 ... Line drive circuit, 36 ... Decoder, 371.372, ..., 37□. ... Nant gate, 39 ... Synchronous clock generation section, 40 ... Inverter, 41 ... AND gate, 421 422, ...
・・42゜0・・・Gate drive circuit, 43□ 43
2,...432o...Switching circuit, 44...
・DC high voltage power supply. Applicant's representative Patent attorney Atsushi Tsuboi (a) Input signal LrN1 (a) Input 71r = No. LIN1 ↓ 14th (a) Input signal LrN1 (a) Input signal No. 8 LIN1 No. 1 Prisoner's Figure Procedural Amendment 2.9r+6 2008 2.9r+6 Indication of the case of Toshi Uematsu, Director General of the Japan National License Agency Patent Application No. 149090 2, Title of Invention Person who corrects ion recording head drive circuit 3° of image forming apparatus Relationship with the incident

Claims (4)

[Claims] (1) drive circuit means for selectively outputting a burst-like high-frequency high-voltage signal generated at a timing corresponding to the image information in accordance with input image information to form an electrostatic latent image on the image carrier; The drive circuit means forms the electrostatic latent image on the image carrier based on the high frequency high voltage signal outputted from the drive circuit means, and includes a plurality of first electrodes formed in a first direction and a plurality of first electrodes formed in a first direction. and a second electrode, which is formed in a second direction different from the first direction, facing each other via a dielectric material, and in which a plurality of small holes for generating ions are formed in the vicinity of the second electrode. In the image forming apparatus, the drive circuit means includes a high-speed high-voltage switching means for switching the high-frequency high-voltage signal at high speed, and a passive element connected to the high-speed high-voltage switching means. , DC high voltage power supply means connected to the passive element and supplying a high voltage to the high speed high voltage switching means, and signal input circuit means supplying a specific frequency signal for a certain period of time in a predetermined sequence to the high speed high voltage switching means. An ion recording head drive circuit for an image forming apparatus, characterized in that the first electrode of the ion recording head is directly electrically connected to the drive circuit means. (2) The ion recording head drive circuit for an image forming apparatus according to claim 1, wherein the passive element includes at least one of a resistor and a coil. (3) The ion recording head drive circuit for an image forming apparatus according to claim 1, further comprising a bias power source for superimposing a predetermined bias voltage on the output of the high-speed high-voltage switching means. (4) An ion recording head drive circuit for an image forming apparatus according to claim 1, wherein said drive circuit means has a capacitor connected between said high speed high voltage switching means and said ion recording head means.