JPH0441665U - - Google Patents
Info
- Publication number
- JPH0441665U JPH0441665U JP8323790U JP8323790U JPH0441665U JP H0441665 U JPH0441665 U JP H0441665U JP 8323790 U JP8323790 U JP 8323790U JP 8323790 U JP8323790 U JP 8323790U JP H0441665 U JPH0441665 U JP H0441665U
- Authority
- JP
- Japan
- Prior art keywords
- storage chamber
- circuit board
- test terminals
- partition wall
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005192 partition Methods 0.000 claims description 3
Landscapes
- Measuring Leads Or Probes (AREA)
- Multi-Conductor Connections (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8323790U JPH0441665U (nl) | 1990-08-08 | 1990-08-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8323790U JPH0441665U (nl) | 1990-08-08 | 1990-08-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0441665U true JPH0441665U (nl) | 1992-04-08 |
Family
ID=31630735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8323790U Pending JPH0441665U (nl) | 1990-08-08 | 1990-08-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0441665U (nl) |
-
1990
- 1990-08-08 JP JP8323790U patent/JPH0441665U/ja active Pending