JPH0441520Y2 - - Google Patents

Description

[Detailed Description of the Invention] <<Industrial Application Field>> The present invention relates to improvement of the dynamic characteristics of a sample-and-hold circuit.

<<Prior Art>> FIG. 3 is a block diagram showing an example of a conventional sample-and-hold circuit. With the input signal being applied to the input terminal 1, the sample and hold signal (hereinafter referred to as S/H signal) applied to the terminal 7 becomes the sample mode, the switch _S1 is turned on at the output of the control circuit 2, Capacitance C _H is resistance
It is charged to the voltage determined by R ₁ and resistor R ₂ . S/
When the H signal goes into hold mode, switch S ₁
is turned off, resistor R ₁ and resistor R ₂ are disconnected from the inverting input terminal, and the charge on capacitance C _H remains unchanged, so the output from terminal 4 remains unchanged.

<<Problems to be solved by the invention>> However, since the above circuit configuration is a first-order circuit configuration, the settling time (acquisition time) is long. In this case, there is a relationship between resolution n (bits) and settling time t as e×p(-t/τ)=1/2 ⁿ⁺¹ ...(1), and from this, t≒0.693(n+1)τ ...(2) becomes. However, τ=RC, R is the value of resistance _R2 .

Another problem is that the frequency band is narrow. The −3 dB frequency _c1 in this case is _c1 = 1/2πCR (3).

Here, there are limits to reducing CR due to constraints on element characteristics (on-resistance of FET switches, bias current of operational amplifiers, etc.).

The present invention was devised to solve the above-mentioned problems, and its purpose is to realize a sample-and-hold circuit with improved dynamic characteristics, such as shortening acquisition time and improving frequency characteristics.

<Means for Solving the Problems> The sample-and-hold circuit according to the present invention includes an input circuit to which an input signal is connected to one end, a switch to which the other end of the input circuit is connected, and a switch to which the other end of the input circuit is connected. an operational amplifier having one end connected to its inverting input terminal, a capacitance having both ends connected to the output terminal and the inverting input terminal of the operational amplifier, respectively, and a capacitance having the other end connected to one end of the input circuit and the other end connecting the operational amplifier to the inverting input terminal; and a feedback circuit connected to an output terminal of the device, and the input circuit and the feedback circuit have an inductance.

"Example" The present invention will be explained in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of a sample and hold circuit according to the present invention. 1 is an input terminal to which an analog input signal is applied, 5 is an input circuit whose one end is connected to this input terminal 1, L ₁ , R ₁
are an inductance and a resistor that constitute this input circuit 5 and are connected in series, _S1 is a first switch to which the other end of the input circuit 5 is connected, and _S2 is a first switch to which the other end of the input circuit 5 is connected. A second switch 3 is connected to one end of the switch _S1 and the other end is connected to common, and 3 is a low input current switch (here, a JFET input) and high speed operational amplifier,
C _H is a hold capacitor whose both ends are connected to the inverting input terminal and output terminal of this operational amplifier 3;
6 is a feedback circuit whose one end is connected to the other end of the input terminal 5 and the other end is connected to the output terminal of the operational amplifier 3; R ₂ and L ₂ are connected in series to form the feedback circuit 6; A resistor and an inductance, 7 a S/H signal input terminal to which an S/H signal is applied, and 20 a control circuit connected to this S/H signal input terminal 7 to control the switches _S1 and _S2 . For example here as switches S ₁ and S ₂
It uses DMOS FET.

The operation of the sample and hold circuit configured as above will be explained below. Since the operation is similar to that of the circuit shown in FIG. 3, only the differences will be described. Switch _S2 is on in hold mode when switch _S1 is off, improving field-through attenuation by preventing the input signal from appearing at the inverting input terminal (summing point). The control circuit 20 also has a function of converting a TTL level S/H signal input into a FET drive voltage. Also, between circuit constants R (values of resistors R ₁ and R ₂ ), L (values of inductance L ₁ and L ₂ ), and C (value of capacitance C _H ), switch S ₁ is on (S ₂ is off). ), the system is critically damped, so there is the following relationship: R ² -4L/C=0...(4) (The characteristic equation is a real equal root). That is, L=R ² C/4...(5) A supplementary explanation of the above will be given.

In FIG. 1, the voltage of the analog input signal applied to input terminal 1 is _Vio , and the output voltage of output terminal 4 is _Vput . When switch S ₁ is on and switch S ₂ is off, V _io of operational amplifier 3 and V _put have the following relationship.

V _put =−(R ₂ +SL ₂ )1/SC/R ₁ +SL ₁ ·V _io (a) Note that s=jω.

Here, if L ₁ /R ₁ =L ₂ /R ₂ =A, equation (A) can be transformed as follows.

V _put = −R ₂ (1+SA) 1/SC/R ₁ (1+SA)・V _io
=-R ₂ /R ₁・1/1+SCR ₂ +S ² CAR ₂・V _io =−R ₂ /R ₁・1/CL ₂・1/(S ² +R ₂ /L ₂・
S+1/CL ₂ )・V _io (b) Here, the quadratic expression of s that appears in the denominator of equation (b) s ² + (R ₂ /L ₂ )s+(1/C・L ₂ )=0 When looking for the roots of becomes. Here, when the radical is 0, critical braking occurs and the response is fastest.

That is, it can be determined so that the relationship 1/4(R ₂ /L ₂ ) ² −1/CL ₂ =0 (d) holds true. The above equation (4) is equivalent to setting L ₂ =L and R ₂ =R in equation (d). At this time, R ₁ and L ₁ are
It is sufficient if this ratio satisfies L ₁ /R ₁ =L/R.

The relationship between resolution n (bits) and settling time (acquisition time) of the circuit shown in Figure 1 is (1+t/τ) e x p (-t/τ) = 1/2 ⁿ⁺¹
...(6) becomes. However, τ=√. FIG. 2 is a characteristic curve diagram comparing the settling time of the circuit of FIG. 1 based on equation (6) with that of the circuit of FIG. 3 based on equation (2), normalized by RC. As is clear from the figure, the settling time a of the apparatus shown in FIG. 1 is about 2/3 shorter than the settling time b of the apparatus shown in FIG.

Also, the -3dB frequency _c2 of the circuit in Figure 1 is calculated as _c2 = 1/2π√ ...(7) Using equation (5), _c2 = 1/2π√ ^{2 2} 4 = 1/πCR = 2 _c1 ...(8) In other words, the bandwidth is doubled compared to the device shown in FIG.

<<Effects of the Invention>> As described above, according to the present invention, a sample-and-hold circuit with improved dynamic characteristics such as shortened acquisition time and improved frequency characteristics can be realized with a simple configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the sample-and-hold circuit according to the present invention, Fig. 2 is a characteristic curve diagram of the circuit shown in Fig. 1, and Fig. 3 is a block diagram showing a conventional example of the sample-and-hold circuit. It is a diagram. 3...Operation amplifier, 5...Input circuit, 6...Feedback circuit, _S1 ...Switch, _CH ...Capacitance, _L1 , _L2 ...Inductance.

Claims (1)

[Claims for Utility Model Registration] (1) An input circuit to which an input signal is connected at one end;
A switch to which the other end of this input circuit is connected to one end, an operational amplifier to which the other end of this switch is connected to its inverting input terminal, and a capacitance whose both ends are connected to the output terminal and inverting input terminal of this operational amplifier, respectively. and a feedback circuit to which the other end of the input circuit is connected to one end and the other end is connected to the output terminal of the arithmetic device, the input circuit and the feedback circuit having inductance. . (2) The sample-and-hold circuit according to claim 1 of the utility model registration, wherein the circuit constants are determined so as to constitute a secondary system that provides critical braking when the switch is on.