JPH0441376B2 - - Google Patents

Description

Claim 1: at least one sorting module 700 receiving items provided in series; each module operative to determine the order in which the items are output by comparing the values of pairs of items; a detector circuit for detecting whether one of the items given in the paired order is a unique spacer item; 704, and a first circuit 711-714, 705 responsive to detecting a unique spacer item to output pairs of items including the unique spacer item in the order in which the pairs of items were received by the module. Apparatus for rearranging items in a desired order, characterized in that:

2. Device according to claim 1, characterized in that the items are alphanumeric symbols to be sorted according to a predetermined relationship.

3. Apparatus according to claim 1 for rearranging items into a desired order, characterized in that the items are multi-bit words to be sorted according to their numerical values.

4. A device for rearranging items in a desired order, wherein the items are alphabetic symbols to be sorted in alphabetical order.

5. Apparatus according to claim 1, characterized in that the items are key values with associated records, for reordering items in a desired order.

6. The apparatus of claim 5, wherein the apparatus further comprises a slave circuit 750 for rearranging the records in the same order as the associated keys. Device.

7. The apparatus of claim 1, further comprising: an array of N serially connected modules configured to sort batches of up to N items, each batch having a Apparatus for rearranging items into a desired order, characterized in that they are separated by at least one unique spacer item.

8. Apparatus according to claim 7 for rearranging items in a desired order, characterized in that the items are key values with associated records.

9. The apparatus of claim 8, further comprising: a bank of N serially connected slave circuits for rearranging the records in the same order as the associated keys. A device that rearranges items in a desired order.

10. In the device according to claim 9, the record is information in a time slot of a time division multiplexed signal, and the device further comprises: An apparatus for rearranging items in a desired order, comprising an assignment circuit 1104 for assigning keys to items.

11. The device according to claim 10, characterized in that the time slots occur forming frames, and the first key of each frame of the time division multiplexed signal is a unique spacer item. Device to rearrange into desired order.

BACKGROUND OF THE INVENTION The present invention includes at least one sorting module that receives items provided in sequence, and each module that normally operates to determine the order in which items are output by comparing the values of pairs of items. and a comparison circuit for rearranging items in a desired order.

"Almost every important point in programming involves sorting or exploration."
(DE Knuth, Computer Programming Technology -
DEKnuth）The Art of
Computer programming, Vol. Addition
(Wesley, 1973), this problem has been widely studied by both computer scientists and electronics hardware designers, and has been extensively studied by both computer scientists and electronics hardware designers, using various techniques such as selection sort, heap sort, insertion sort, and arge sort. Methods have been developed in the literature. Yet another technique, called "bubble sorting," is well known and is known by several names, including interchain disorting, single chain disorting, and subduction sorting. Although the terminology varies widely, it is generally agreed that the essence of bubble sort is to swap adjacent items within the chunks being sorted. During each permutation, the values of the items are compared and
Items are rearranged as necessary so that the items are given a predetermined relationship, for example, the smallest item is given first or the largest item is given first. Permutations are typically performed sequentially, typically repeatedly scanning all items in a chunk until no further permutations are needed, at which point it is determined that the entire chunk has been sorted. Become. Most of the bubble sort methods have been implemented in software (e.g. Popular Computing Vol.8,
No.11November1980 “Bubble Sorting”P,
(See 2-10) Therefore, since most general-purpose computers have only one processor in particular, they are limited to executing a series of sequential operations. To overcome the resulting processing speed limitations,
Various hardware implementations have been devised using conventional integrated circuit techniques and using magnetic bubble return devices. An example of the latter is DTLee et al.
IEEE Trans.on Computers Vol.C-30 entitled “On-Chip Compare/Steer Bubble Sorter”
No. 6 June 1981, PP. 396-405 (see especially Figure 6), and the implementation method using IC is shown in P.
“The DIMOND;A” by G. Jansen et al.
Component for the Modulator Construction
of Switching Networks”IEEE Trans on
Computers VoL.C−29, No.120ct, 1980 pp.884
-889 (see especially Figure 9).

The effectiveness of such prior art bubble sort devices can be measured on a number of factors, such as size, achievable throughput, time delay, and storage requirements. This device is limited in the number of items that can be sorted in each chunk, and the design is not compatible with modular construction using VLSI technology. Many of the known sorting devices that are successful in meeting some of the above criteria are, however, expensive or difficult to implement.

SUMMARY OF THE INVENTION In accordance with the present invention, this problem is solved by a module that includes a detection circuit for detecting whether an item provided sequentially in a pair is a unique spacer item, and a detection circuit responsive to the detection of a unique spacer item. a first circuit for outputting pairs of items including unique spacer items in the same order in which the pairs of items were received by the module; It will be resolved.

The invention includes a chain of sorting modules all clocked synchronously. The items to be sorted occur in groups, and each item typically has a value that determines the order in which it should be placed relative to other items in the group. With each clock pulse, an item is applied to the first module and each module with two items compares the values of the items and assigns one of the items to the next module according to the type of sort desired. is configured to forward to. Items can be sorted numerically, alphabetically, or according to any other predetermined relationship. Items that do not pass are saved and used in the next comparison.

In accordance with the invention, each module is configured to identify a special "spacer" item that precedes or distinguishes one batch of items from the next. When a spacer item is received by the sorting module, that spacer item and the other items it contained are output (on the next two clock pulses) in the same order in which they were received. As a result, N
Clusters of items can be efficiently sorted as long as the items in each cluster are separated by spacer items. This results in increased throughput and makes the configuration more flexible than conventional valve sorters.

A similar system can be used to sort records containing keys associated with data. In this configuration, a key is provided to a sorting module while corresponding data is rearranged in a series of slave modules.

Efficient sorting made possible by the present invention also allows labeling to be done in a desired manner;
By manipulating the record key, it can be used to perform sorting. As an example, the order of the items can be reversed by assigning keys to the items in decreasing order. By sorting these records in the direction of increasing keys, items can be generated in reverse chronological order.

Its particular application is the interchanging of time slots in time division multiplexed signals. For example, each time slot of a time division multiplexed signal can be viewed as a data portion of a record. By associating a key with each time slot's data, the slot order can be easily changed by simply processing the records using the sorting system of the present invention.

[Brief explanation of drawings]

These features and advantages of the invention will be more fully realized by studying the following detailed description in conjunction with the accompanying drawings.

Figures 1 to 3 are diagrams illustrating a method for sorting a series of items using a prior art bubble sort technique; Figures 4 to 6 are diagrams showing how to sort two groups of items using bubble sort according to the present invention; 7 and 8 are block diagrams of embodiments of other module configurations for sorting records constructed in accordance with the present invention; FIG. 9 is a diagram illustrating the sorting method of FIG. Fig. 10 is a conventional time slot switching device; Fig. 11 is for switching time slots of a time division multiplexed (TDM) signal. Figure 7 or 8 of
A diagram illustrating the use of a serial chain of record sorting modules as shown in FIG. FIG. 3 is a diagram illustrating the use of a chain of teaching modules;

DETAILED DESCRIPTION FIGS. 1-3 are graphs illustrating the beginning, intermediate and final cycles of a typical valve sort operation. In these three figures, the same numbers are used to refer to the same elements. As shown in Figure 1, the numbers 8, 0, 1, 9, 7, 5, 3,
Let a sequence of 10 items with values 6, 4, and 8 be sorted, and these items have individual recording positions 101-18 to 101-10 at time t=0.
It is preloaded into a 10-position shift register 101. A clock pulse φ on each successive line 102 causes the contents of register 101 to move one position to the right such that the item contained in position 101-1 is equal to or greater than 10 sorting modules 111.
-1 to 111-10 serial chain inputs.

Each sorting module stores two given items in the recording elements shown above and below, compares the values of the stored items, and selects one item according to the type of sorting desired. I'm starting to do that. The following example describes a configuration in which the order is from lowest to highest. Each module provides selected items at its output, which are either coupled to the next sorting module or, in the case of the last module, provided to the utilization device. At the same time, each module accepts the input of the next item from the previous module, or from the register 101 in the case of the first module. Typically, the modules operate synchronously under the control of clock pulses from a clock source (not shown). The output of the last module 111-10 is in register 1
21, which (as well as register 101) has ten storage locations 121-1.
121-10 and is clocked by the pulse on line 102.

As shown in FIG. 1, all of the sorting modules 111-1 to 111-10 operate at time t=
Initialized with 0, each will contain two items with a "very small" value, denoted by the letter "S". By definition, the value "S" is less than any expected value that would be expected to appear in the batch of items being sorted. Initialization can be accomplished in a variety of ways, but is necessary in prior art devices for the purposes described below. At time t=0, after one clock pulse φ has occurred, the contents of register 101 are shifted one position to the right, and the entry with the value "8" from memory location 101-1 is transferred to sorting module 111. -1 is stored. All modules 111-1 to 1
Since 11-10 contains items with the same value S before the first clock pulse occurs, the contents of one storage location of each module (the upper half in the graph) are shifted and the first clock pulse At the end of the cycle, the item with the value "8" received from memory location 101-1 will fill the emptied memory location in module 111-1. The item with the value "S" output from the last sorting module 111-10 is discarded because it has no further useful function.

After the next clock pulse occurs (t=2), the contents of register 101 are shifted to the right again and the entry with a value of "0" from memory location 101-1 is input to sorting module 111-1. has been done. Module 111-1 simultaneously stores the value 8 of the item stored in two storage locations at the same time.
and "S" are compared, the item with the value "S" is passed through module 111-2, and the item with the value "O" is placed in the now empty (lower half) position of module 111-1. . All remaining modules work similarly. At time t = 2, all other modules contain items with value "S", so these items propagate through the empty positions (top halves) of the remaining modules, and the values ”
The second entry with "S" is discarded.

The above process is repeated for each subsequent clock pulse φ. After the third clock pulse, a comparison is made between the key values (8 and 0) of the first two entries in module 111-1. Since "0" is smaller, that item is given to the next module 111-2 in the chain. When yet another clock pulse occurs, the "0" is compared to the value of "S" in module 111-2 and, as previously stated, since the value of "S" is small, that entry is shifted. To make it easier to see the position of the item to be shifted in the graphical representations of Figures 1-3, the upper half of the module that entered the item with the smaller value (before applying the next pulse φ) or shown with shading in the corners of the lower half.

At the end of 10 clock cycles, register 10
1 will be empty and its contents will be completely stored in sorting modules 111-1 to 111-5, each of which stores two items. For the reasons given below, we will now fill the chain of the sorting module with items with large values, denoted by the symbol "L", that are greater than any possible value already in the sorting module at that time. It is important to start. To include an item with a large value (20 is fine in this example), add the item with the desired large value to the end of each group of items you want to sort, or change the position of switch 125. , the items of each batch of large values stored in the auxiliary register 130 are preferably provided to the chain of sorting modules after they have completely entered the chain.

Continuing the same example with reference to FIG.
It can be placed in 1. When 14 clock pulses occur, it can be seen in FIG. 2 that the items are in the desired sorted order. However, this item needs to be processed through the remaining modules. This is because N modules are required when sorting other groups up to N items. After 20 clock pulses have occurred, the item is ready to output module 111-10. For illustrative purposes, Figure 3 shows how the contents of the sorting module are output to register 121 during the next 10 cycles, so that after 30 cross pulses
21 contains the sorted items in the desired order, that is, in the order in which the item with the smallest value appears first. At this time, the 20 storage locations of the sorting modules 111-1 to 111-10 are filled with items with the value "L", and these items are filled with the value "S" in preparation for sorting the next batch. It may be replaced with an item.

The purpose of providing initial "S" and final "L" headers and trailers in prior art bubble sorting devices is to separate adjacent cluster items provided in a serial chain of sorting modules;
This is to prevent items from one cluster from being mixed with items from previous or subsequent clusters. For example, if the first item with the value "L" instead has a value not greater than the value of all previous items, this will cause the sorting between the 10th clock pulse and the 30th clock pulse. It appears before any of the previous items in the module, causing an error. Similarly, if the initial item with the value "S" has a value that is not less than the value of all previous items, it will be replaced by the item with the smallest value, whichever item is first in the cluster, and in this case The output sequence of the sorter will also be inappropriate. The batches originally stored in register 101 are associated with separate batches with 4 and 6 items, respectively, and a special header (“S”) is used to separate them.
value) or. The development of interference between batches can be further explained if we consider that the trailer (after "L") is not present. These 10 items (8
-0-1-9 and 7-5-3-6-4-8) are sorted, the desired result is 0-1-8-9 and 3-4-5-6-7-8 Since the distinction between items in different batches is lost, the first group that actually occurs is 0-1-3-4, and the second group is 5-6-7-8-8-9. Become.

If special items are provided as headers and trailers for each batch of n items, initializing with an item with a value of “S” and purging to remove a value with an item with a value of “L” will each take 2n clocks. Since it must be done serially over the period of a cycle, the time required for sorting doubles from 2n to 4n clock cycles. The operation of changing the previous 2n values with the value of "L" to the next 2n groups with the value of S can be performed in one clock cycle, possibly simultaneously, or else:
An additional 2n period is required. In conventional hardware bubble sorter implementations, the processing speed losses caused by the initialization and purging operations described above are relatively more significant. Specifically, if the batch of items to be sorted is large, the chain of sort modules must be large enough to handle the largest batch, and if the maximum batch size is N, then the number of N modules is provided. Even if there is a short batch, initialize all sorting modules and use 2N S and L
Initialization and purging must be done in the header/trailer items. In this case, initialization/palming requires longer time than actual sorting.

According to the invention, by inserting a spacer item with a unique value between the values of each batch of items to be sorted, each sorting module is enabled to detect the presence of the spacer. , the difficulties caused by the initialization and purging processes described above can be avoided. The spacers are shown in Figures 4 to 6.
In the figure, it is graphically indicated with a "*" mark. When a spacer is detected by a module, the module is configured to output the sorted items in the same order as they were presented during the next two clock pulses. This arrangement ensures that items from each batch do not leak into previous or subsequent batches. In the illustrated example; the 10 items with the same values as used in the examples of Figures 1-3 are the first batch with 4 items (8-0-1-9) and the 6 items (7- 5-3-6-4-8). However, the batches are separated by extra spacer items or unique keys with unique values, indicated symbolically by "*" in FIG. In this example, sorting modules 111-1 through 111-10 initially contain values P from one or more previous batches, and the most recent module 111-10 contains values P from one or more previous batches.
The input to 1-1 is a spacer item, which gives the batch of previous items the value 8-0 that is now being processed.
-1-9, which are stored in register locations 101-1 to 101-4.

After the occurrence of the first clock pulse (+=1), the item previously stored in one of the storage locations (lower half) of sorting module 111-1 is moved to the next module 111-2 and the item stored in the storage location 10
The initial item with the value (8) stored in 1-1 is replaced by it. This operation occurs because the spacer item indicated by the asterisk "*" is the last item to be included in module 111-1. When a spacer item is detected, module 111-1 operates to hold that item and pass other stored items to the next module. For this same reason, after the second clock pulse (t=2), the spacer item is not the most recent content entered by module 111-1, so module 111-1 moves it to module 111-2. . As shown in Figure 4, 4
After the clock pulse, all items in the first batch are sorted by sorting modules 111-1 and 11.
It will come in at 1-2. When the next clock pulse occurs, a spacer item following the first batch and separating it from the next batch is placed in module 1.
Enter 11-1.

Next, the operation of the sorting module in the presence of a spacer item will be explained by comparing the states of the module before and after the sixth clock pulse. If the spacer item in module 111-3 has already been in place for two clock cycles, sorting module 111-
Spacer items within 3 will move to the next module during this period. On the other hand, since the spacer item of sorting module 111-1 has just entered in the previous cycle and is therefore the newest entry, that spacer item is not moved. In summary, the sorting module of the present invention compares two sorted items on each clock cycle and presents one item to the next module according to the relationship between the values of the items. Typically, the values of the items are compared numerically, alphabetically, or according to some other desired relationship. However, when a spacer item with a unique value is detected, it is treated specially and the module performs another action. In this case, the selection of items to be transferred to the next module will follow the order in which the items are given to that module. The oldest item is independently applied to the next module without regard to its value, while the most recently applied item is held for one clock time in each module.

Continuing with Figure 5, after the twelfth clock pulse occurs, the six items of the second batch and the spacer items that distinguish this batch from the next batch are completely removed from the sorting module. will be included in the chain. Additional items may be included after this batch, but for the purposes of this example, these items are simply designated by the symbol "A."

Operation of the sorting device continues for several more cycles, and after the 20th cycle (see Figure 5), the initial items of the first batch are sorted into module 1.
It will be ready to output from 10-10. Output items may be placed in storage registers or provided to other utilization devices. However, for illustrative purposes, FIG. 6 depicts items being shifted into register 121. As can be seen in the figure, after 30 clock pulses, both batches of items are properly sorted and
To initialize with special items or to eliminate bugs with a small (S) or large (L) key, as was necessary in the prior art devices typically shown in the example shown in the figure. It turns out there is no need for wasted time.

A block diagram of one embodiment of a record sorting module according to the principles of the present invention is shown in FIG.
Basically, each record sorting module includes a sorting circuit that sorts the keys associated with each record in the manner described above, and a slave circuit that rearranges the data of each record in the same order as the corresponding keys. It consists of 750. The sorting circuit 700 receives the keys associated with each record, compares the keys in the manner described above, and performs sorting by selecting and outputting one key according to its relative value and the order of input of the keys. Execute. The slave circuit 750 receives the data of the record having the corresponding key, and when the corresponding key is selected in the sorting circuit, selects and outputs the data of one record.

To perform key sorting, the keys associated with a record are entered on line 740 and the next occurrence of a clock pulse φ generated from a clock source, not shown, causes the two key registers 7
01 or 702 or the other. The particular one of the registers that receives a key is determined by which of the keys stored in these registers is selected for presentation to the sorting circuit of the next module in the chain.
This selection is typically made by comparing the values of keys stored in registers 701 and 702. These values are for simplicity in the explanation below.
They are named "A" and "B" respectively. However, if one of the stored keys has a unique value that is recognized as a spacer item, that value is ignored and the key is stored in registers 701 and 701.
02 are placed on the output according to the same chronological order as entered. Selection based on the value of a key receives inputs (i.e. A and B) from both registers 701, 702, and AB when it is desired to sort the items in numerical order from lowest to highest, for example. This is done by comparator 703 which operates to produce a high level output on line 707, if any. If the reverse numerical order is desired, comparator 703 can be easily modified to produce a high level output for A and B.

If the key (A) stored in register 701 is smaller than the key (B) in register 702, a high level output from comparator 703 passes through AND gate 711 and OR gate 712, and register 701 is activated. The currently stored key (A) applied to input 721 causes it to be output on line 731, while the new key (on input line 740) is placed in the register. By inverting the high level output of OR gate 712 using inverter 716, input 722 of register 702 is not activated during AB. Key A is coupled to output 710 of sorting circuit 700 via multiplexer switch 705, which also receives a position control input from OR gate 712. As shown in FIG. 7, switch 705 couples value A to output 710 when the output of OR gate 712 is high. Alternatively, when the key of register 701 is greater than the key of register 702 (A>B),
The forces of AND gate 711 and OR gate 712 are at a low level, and inverter 716
2 is energized (via line 722) to provide the key stored on it to switch 705 so that it will accept the next key on line 740. Key B is coupled to output 710 via toggled switch 705.

The sorting circuit of FIG. 7 also includes a spacer item detector 704, which is connected to both registers 70.
1 and 702 to monitor the presence of a unique spacer item in either storage location. When detected, the output of the detector goes high, disabling AND gate 711 via inverter 714 and energizing AND gate 713 to OR gate the signal derived from the inverted output () of flip-flop 706. Pass to 712. Flip-flop 706 is OR gate 712
It operates as a 1-bit memory that receives the output of the clock at its data (D) input and stores that value until the next clock pulse φ is applied to its clock input. For example, if the spacer item is in register 70
If it is the most recent input of 1, the input is allowed.
The high output of OR gate 712 causes the output of flip-flop 706 to go low, which causes AND gate 713 and OR gate 712 to go low when the next clock pulse occurs. As a result of this, multiplexer 705
The next item given to is independent of value comparison,
It will come from register 702. Since the spacer item remains in register 701, detector 7
The output of 04 remains at high level, and AND gate 7
13 remains energized at the beginning of the next cycle. However, the low output of OR gate 712 causes the flip-flop output to go high on the next clock pulse φ. The resulting high level outputs of AND gate 713 and OR gate 712 output the spacer key from register 701 and the desired two
Complete the operation of the cycle. In summary, in normal operation, sorting circuit 700 selects the key to be applied to the next module as a function of the relative value of the key. However, after the detection of the spacer item, the keys of the sorting module are read in the order in which they are given.

Each of the record sorting modules 111-1 through 111-10 of FIGS. 4-6 includes the circuitry of FIG. 7 that arranges the data of each record in the same order as the corresponding keys associated with that record. 750
Contains slave circuits such as To this end, circuit 750 includes data registers 751 and 752, each capable of sorting the data of records received at data input 760. The output of the OR gate 712 is the register 70
1 directly and also energizes resistor 702 via inverter 716, which also energizes the energize input directly to register 751 and also to inverter 702.
56 to register 752. By subordinating these registers to the registers of sorting circuit 700, data is placed into the appropriate register when the next flock pulse φ occurs. Slave circuit 750 also includes a multiplexer switch 755 similar to multiplexer 755.
, which is also responsive to OR gate 712 to couple the output of the selected one of registers 751 or 752 to data output 770 .

Depending on the nature of the items to be sorted, the sorting module of the invention can be configured in various ways by those skilled in the art. Typically, the items are multi-bit words, with the sign bit provided in registers 701 and 702, and comparator 703 numerically comparing the values to identify the sign bit. However, in some cases, it may be desirable to perform sorting using only absolute values. The items may also be words sorted alphabetically, or alphanumeric symbols sorted according to other predetermined relationships. A spacer item is a unique (usually multi-bit) word for this purpose,
Detector 704 is a logic circuit configured to compare each input to a pre-stored set of spacer items. When records are sorted,
Registers 751 and 752 are larger registers than registers 701 and 702, depending on the amount of data each contains.

Another embodiment of a record sorting module constructed in accordance with the principles of the present invention is shown in FIG. Similar to the configuration described above, the sorting circuit 8
00 and slave circuit 850 are provided for sorting the keys and corresponding data of batches of records, respectively. Sorting circuit 800 includes first and second key storage registers 801 and 8
02, but each key applied to input line 840 is always entered into first register 801 on each clock pulse φ. Registers 801 and 8
The keys stored in 02 are compared in a comparator 803, and assuming that numerical sorting from low to high is desired, when the value (A) in register 801 exceeds the value in register 802 (B), It is designed to produce a high level of output. In the case of sorting from high to low, the output of comparator 803 goes high when AB.

If the output of comparator 803 is high level, OR
The high output of gate 806 causes multiplexer 805 to provide the key in register 802 to output line 810. AND gate 807 is activated to provide a clock pulse φ to register 802 so that the key stored therein is actually output and
It is replaced by the key stored in register 801. On the other hand, if the output of comparator 803 is low and no spacer item is present, the output of OR gate 806 will also be low. In this case,
Switch 805 is switched to couple the key (A) stored in register 801 directly to multiplexer 805 . At this time, AND gate 807
is deactivated, so the keys in register 802 are not disturbed. In summary, sorting circuit 800 compares the value of each key stored in register 801 with the value of the previous key input stored in register 802. If a certain pre-lowered relationship is satisfied (eg, the most recent input is less than the previous input), then the newly received key is provided to the output 810 of the sorting circuit. If this relationship is not satisfied (eg, if the recent input is greater), the previously received key in register 802 is connected to output 810 and replaced by the recent input. If a spacer item is detected, the high level outputs from detection switches 804a and 804b are
The combination via OR gate 806 ensures that multiplexer 805 remains in the position shown in FIG. This condition is in register 802
The key that has been stored for a long time will be output.
The key associated with the spacer item is transferred to register 802 and output on the next occurrence of clock pulse φ. This will preserve the order of the keys when a spacer key is detected.

Similar to the configuration in FIG. 7, in the configuration in FIG. 8, a slave circuit 8 sorts the data or records of each item according to the key associated with that item.
Contains 50. Circuit 850 connects the first and second
register 851 receives an input word from line 860 and provides its contents via multiplexer 855 to output line 870 when switch 855 is in the down position at AB. When A>B or a spacer key is detected, the output of OR gate 806 goes high, multiplexer 855 is in the upper position as shown in FIG. 8, and the information held in register 852 is It is output and replaced by the data in register 851 when clocked through AND gate 857.

A part of the sorting module circuit shown in FIG. 8 is changed to receive the output of the detector 804a instead of the spacer detector 804b and output a high level at the next clock pulse φ, as shown in FIG. It is also possible to replace it with a delay circuit 901 that generates . This simplification means that when a spacer key is detected in register 801 (by detector 804a), it will also be detected by register 802 one cycle later (by detector 804b). It is recognized that

There are many uses of the sorting device technique described above. An example is a time slot shuffling device that can rearrange a sequence of time division multiplexed data signals. The traditional time slot changer is the 10th
As shown in the figure. Series of 100 time slots
Data of 0 is sequentially stored in a double buffer memory including buffers 1001 and 1002.
While one of the buffers is being stored, data from the other is being processed. Similarly, Batsuhua 10
05 and 1006 are configured as a double buffer, so that when buffer 1006 is being read, buffer 1005 is being written to, and vice versa. memory 100
4 is configured to give instructions to the processing unit 1003 of the desired replacement device. For example, data in timeslot E may be destined for timeslot B, and so on. The processing unit 1003 has a buffer 1001 or 10
02 time slot E is extracted and transferred to the buffer 100 corresponding to time slot B.
Place it in position 5 or 1006. The data from all time slots stored in buffer 1001 or 1002 is transferred to buffer 100.
5 or 1006, the desired time slot sequence 1007 is obtained.
However, this prior art replacement technique requires a significant amount of hardware and a relatively long processing time. Each time slot exchange involves one read from the memory, one read from the buffer,
Requires one-time writing to buffer. Therefore, 2N cycles of processing are required for N timestamps. As a result, the input/output buffers can only be replaced every 3N cycles. The overall delay of such a time slot switching device is
It becomes 9N cycle. The new time slot is 3
It can only be applied to the time slot switching device on a cycle-by-cycle basis.

A time slot replacement device that uses the sorting method of the present invention to significantly improve processing time is:
It is shown in FIG. 11 in block diagram form. The replacement device is realized using a record sorting module as shown in FIG. 7 or 8. In this configuration, the data to be sorted is the contents of the time slots within each frame of the time division multiplexed signal. The associated keys are assigned to key assignment circuit 1104 to indicate the desired time slot position.
added to the data by As an example, the first
The signals are applied to data line 1101 in a frame having five time slots A-E as shown in FIG. To change the time slot order to a desired order, such as (C-A-D-E-B), key assignment circuit 1104 assigns a key to each time slot. In the example of FIG. 11, it is desired to transfer the data of slot C from the fourth position to the first position, so the value "1" is assigned to it. Similarly, since the data in slot B is moved from the second position to the fifth position, it is assigned a key value of "5". Unique spacer key 11
03 is added by the generator 1105 to the beginning of a frame consisting of five records.

Time slot replacement is performed using N record sorting module 1 (key and data).
120-1, 1120-2, . . . 1120-N. As mentioned earlier, this includes a sorter circuit and a slave circuit, and the seventh
It is constructed as shown in FIG.
The keys are sorted as they are transferred from one module's sorting circuit to the next module's sorting circuit, while the data is sorted in a corresponding order by the slave circuit. The value of N is chosen to be the largest expected batch size of records. (5 slots in this case). The output from the last sorting circuit in the chain of modules is the original data sorted in the desired order.
This data may be placed in register 1110, or may be provided to the next processing circuit, discarding the key, if desired.

The time slot shuffling device described above has a delay time of 3N, which means that the information from up to three previous frames must be processed before outputting the information from the current frame, and in each cycle a new time slot is inserted. Indicates that it must be processed.
As a result, the delay time is reduced to 1/3 compared to the traditional time slot switching device shown in Figure 10.
Throughput is improved three times.

A chain of record sorting modules of the type shown in FIGS. 7 and 8 may also be used to rearrange the time slots of each frame of a time division multiplexed signal in order to utilize free time slots.

Frames 1201 and 1211 contain the time slots of first and second time division multiplexed signals. Keys 1 through M are assigned to M slots in each frame such that the frames are merged after relocation. Specifically, the keys that fill the time slots of one signal are uniquely selected from the keys assigned to empty time slots of the other signal. The keys associated with the remaining time slots of each frame are allocated as needed from the remaining unused keys of the original M keys. The keys assigned to each frame are then sorted separately and the associated timeslot data is also rearranged accordingly. The new frames thus generated are merged to produce a final sequence with fewer free time slots. This approach can be applied as long as the total number of occupied slots in both frames is less than the number of slots in each frame. In the example shown in FIG. 12, keys 1, 3, and 5 are assigned to empty slots 1, 3, and 4 in frame 1201, and keys 1, 3, and 5 are assigned to empty slots 1, 2, and 3 in frame 1211. the same set (1, 3, 5) assigned to
A uniquely selected key is assigned. The remaining keys are the sequence 1202,1 shown in this example.
The remaining slots in frames 1201 and 1211 in 212 are allocated.

The records thus formed (key, plus, time slot data) are rearranged separately by record sorting modules 1203 and 1213, resulting in new frames 1204 and 1214, respectively. These frames can be merged by a frame multiplexer 1220 or other similar combinational circuit,
A combined output frame 1230 can be formed;
This advantageously excludes excess free time slots.

The configuration of the sorting module of the present invention is
It can be easily implemented using VLSI technology, and the modularity of the design allows for various efficiencies.

Various adaptations and modifications of the invention can be made by those skilled in the art without departing from the spirit and scope of the invention.
Accordingly, the invention is limited only by the scope of the appended claims. For example, although the sorting module is illustrated as receiving clock pulses from a single clock source, it is possible to interconnect the modules in series with respect to timing, such that each module receives timing pulses from the previous module. You may also do this. Furthermore, since sorting and permuting are very similar, sorting chains can also be used to perform permutations by changing the labels of key values.