JPH0440948B2 - - Google Patents

Info

Publication number
JPH0440948B2
JPH0440948B2 JP58069366A JP6936683A JPH0440948B2 JP H0440948 B2 JPH0440948 B2 JP H0440948B2 JP 58069366 A JP58069366 A JP 58069366A JP 6936683 A JP6936683 A JP 6936683A JP H0440948 B2 JPH0440948 B2 JP H0440948B2
Authority
JP
Japan
Prior art keywords
output
diodes
point
capacitor
tap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58069366A
Other languages
Japanese (ja)
Other versions
JPS59194667A (en
Inventor
Yoshio Takamura
Hiroshi Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP6936683A priority Critical patent/JPS59194667A/en
Publication of JPS59194667A publication Critical patent/JPS59194667A/en
Publication of JPH0440948B2 publication Critical patent/JPH0440948B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
    • H02M7/10Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode arranged for operation in series, e.g. for multiplication of voltage

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、任意の出力電圧を設定し得る多倍圧
整流回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplier rectifier circuit capable of setting an arbitrary output voltage.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に、多倍圧整流回路に於ては、この回路に
入力される交流電圧に関し、原理的にはその整流
倍にしか出力電圧を設定し得ないものであつた。
In general, in a multi-voltage rectifier circuit, with respect to the AC voltage input to the circuit, the output voltage can, in principle, be set only to the rectification times that of the AC voltage.

〔発明の目的〕[Purpose of the invention]

この発明は上記の事情に鑑みてなされたもの
で、任意の出力電圧が設定でき、且つ複数出力を
得る場合もその出力電圧間の比率を任意に設定で
きる多倍圧整流回路を提供することを目的とす
る。
This invention has been made in view of the above circumstances, and an object of the present invention is to provide a multiplier rectifier circuit that can set an arbitrary output voltage and, even when obtaining multiple outputs, can arbitrarily set the ratio between the output voltages. purpose.

〔発明の概要〕[Summary of the invention]

この発明は多倍圧整流回路と組合わされるトラ
ンスの出力巻線に複数個の中間タツプを設け、そ
の一つの中間タツプを基準電位点に接続し、これ
によつて得られる異る電圧を組合せ任意の出力電
圧を設定しようとするものである。
This invention provides a plurality of intermediate taps on the output winding of a transformer combined with a multiplier rectifier circuit, connects one of the intermediate taps to a reference potential point, and combines different voltages obtained thereby. The purpose is to set an arbitrary output voltage.

〔発明の実施例〕[Embodiments of the invention]

以下この発明の実施例を図面を参照して説明す
る。第1図は本発明の動作原理を説明する実施例
であり、トランスTの1次巻線の両端間には矩形
波の交流電圧発生源Eが接続される。前記トラン
スTの2次巻線には出力端子a,d及び中間タツ
プb,cが設けられる。この中間タツプCは接地
Gされると共に直列接続された複数個のダイオー
ドD1,D2,D3,D4のアード側eが接続され、こ
のダイオードD1〜D4のカソード側iは出力端A
に接続される。前記ダイオードD3〜D4の接続点
hと出力端子aとの間にはコンデンサC1が接続
され、前記ダイオードD1,D2の接続点fと中間
タツプbとの間にはコンデンサC2が接続される。
前記ダイオードD4のカソード側iとダイオード
D1のアノード側eとの間にはコンデンサC3が接
続され、前記ダイオードD2,D3の接続点gと出
力端子dとの間にはコンデンサC4が接続される。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment for explaining the operating principle of the present invention, in which a rectangular wave alternating current voltage source E is connected between both ends of the primary winding of a transformer T. The secondary winding of the transformer T is provided with output terminals a, d and intermediate taps b, c. This intermediate tap C is grounded and connected to the terminals e of a plurality of series-connected diodes D 1 , D 2 , D 3 , D 4 , and the cathodes i of these diodes D 1 to D 4 are connected to the output terminal. End A
connected to. A capacitor C 1 is connected between the connection point h of the diodes D 3 to D 4 and the output terminal a, and a capacitor C 2 is connected between the connection point f of the diodes D 1 and D 2 and the intermediate tap b. is connected.
The cathode side i of the diode D4 and the diode
A capacitor C 3 is connected between D 1 and the anode side e, and a capacitor C 4 is connected between the connection point g of the diodes D 2 and D 3 and the output terminal d.

即ち、接地電位に対し、a点は490V、b点は
320V、d点は500Vの矩形波の交流電圧が発生し
ているとする。先ずa点が負の半サイクルでは、
コンデンサC2はダイオードD1を通じて1点が正
の向きに320Vに充電され、次いでa点が正のサ
イクルにはコンデンサC4がダイオードD2を通じ
てコンデンサC2に充電されている320Vに、トラ
ンスTの2次出力b,d間電圧820Vが加算され
た1140Vまでg点が正の向きに充電され、次いで
再びa点が負の半サイクルになればコンデンサ
C1はコンデンサC4に充電されている1140Vに、ト
ランスTの2次出力a,b間電圧990Vが加算さ
れた2130VまでダイオードD3を通してh点が正の
向きに充電され、更に次のa点が正のサイクルに
なると、コンデンサC3はダイオードD4を通して
i点が正の向きに、コンデンサC1に充電されて
いる2130VにトランスTの2次出力e,a間電圧
490Vが加算された2620Vまで充電され、これが
この倍電圧整流回路の出力電圧となる。このよう
にトランスTの2次出力巻線に適当な中間タツプ
を設け、これを組合せることによつて微妙な電圧
設定が可能であることがわかる。この各出力端に
1個又は複数個のコンデンサを直列もしくは並列
に接続し、これを適宜組合わせれば任意の1個以
上の出力電圧を設定することができる。
That is, with respect to the ground potential, point a is 490V, point b is
It is assumed that a rectangular wave AC voltage of 320V and 500V is generated at point d. First, in the half cycle where point a is negative,
The capacitor C 2 is charged to 320V through the diode D 1 in the positive direction at one point, and then in the cycle where point a is positive, the capacitor C 4 is charged to 320V through the diode D 2 to the transformer T. If point g is charged in the positive direction to 1140V, which is the sum of the voltage 820V between the secondary outputs b and d of
C1 is charged to 2130V, which is the sum of the 1140V charged in the capacitor C4 and the 990V voltage between the secondary outputs a and b of the transformer T, through the diode D3 at point h, and then the next a When the point becomes a positive cycle, the capacitor C 3 connects the voltage between the secondary output e and a of the transformer T to the 2130V charged in the capacitor C 1 through the diode D 4 so that the i point is in the positive direction.
The battery is charged to 2620V, which is the sum of 490V, and this becomes the output voltage of this voltage doubler rectifier circuit. It can be seen that by providing an appropriate intermediate tap on the secondary output winding of the transformer T and combining these taps, delicate voltage settings are possible. By connecting one or more capacitors in series or parallel to each of these output terminals and appropriately combining them, one or more arbitrary output voltages can be set.

第2図はこの組合せの実施例である。即ち、ト
ランスTの1次巻線の両端間には矩形波の交流電
圧発生源Eが接続される。前記トランスTの2次
巻線には出力端子a,e及び中間タツプb,c,
dが設けられる。この中間タツプC点は接地Gさ
れると共に直列接続された複数個のダイオード
D11,D12,D13,D14,D15,D16,D17,D18
D19,D20,D21のアノード側fが接続され、この
ダイオードD11〜D21のカソード側qは出力側C
に接続される。前記ダイオードD18,D19の接続
点nと出力端子aとの間にはコンデンサC11が接
続され、前記接続点nとダイオードD20,D21
接続点Pとの間にはコンデンサC12が接続される。
前記ダイオードD12,D13の接続点hと中間タツ
プb点との間にはコンデンサC21が接続され、前
記b点とダイオードD15,D16の接続点Kとの間
にはコンデンサC22が接続される。前記ダイオー
ドD13,D14の接続点iと前記f点との間にはコ
ンデンサC31が接続され、前記i点とダイオード
D16,D17の接続点lとの間にはコンデンサC32
接続され、前記l点と前記q点との間にはコンデ
ンサC33が接続される。前記ダイオードD14,D15
の接続点jと前記d点との間にはコンデンサC41
が接続され、前記j点とダイオードD17,D18
接続点mとの間にはコンデンサC42が接続され前
記m点とダイオードD19,D20の接続点oとの間
にはコンデンサC43が接続される。前記ダイオー
ドD11,D12の接続点gと前記出力端子e点との
間にはコンデンサC51が接続される。前記i点に
は出力端Aが接続され、前記l点には出力端Bが
接続される。
FIG. 2 shows an example of this combination. That is, a rectangular wave AC voltage generation source E is connected between both ends of the primary winding of the transformer T. The secondary winding of the transformer T has output terminals a, e and intermediate taps b, c,
d is provided. This intermediate tap point C is grounded and connected in series with multiple diodes.
D 11 , D 12 , D 13 , D 14 , D 15 , D 16 , D 17 , D 18 ,
The anode side f of D 19 , D 20 , D 21 is connected, and the cathode side q of these diodes D 11 to D 21 is connected to the output side C
connected to. A capacitor C 11 is connected between the connection point n of the diodes D 18 and D 19 and the output terminal a, and a capacitor C 12 is connected between the connection point n and the connection point P of the diodes D 20 and D 21 . is connected.
A capacitor C 21 is connected between the connection point h of the diodes D 12 and D 13 and the intermediate tap point b, and a capacitor C 22 is connected between the connection point K of the diodes D 15 and D 16 . is connected. A capacitor C31 is connected between the connection point i of the diodes D13 and D14 and the point f, and a capacitor C31 is connected between the point i and the diode
A capacitor C 32 is connected between the connecting point l of D 16 and D 17 , and a capacitor C 33 is connected between the l point and the q point. The diodes D 14 , D 15
A capacitor C 41 is connected between the connection point j and the point d.
A capacitor C 42 is connected between the point j and the connection point m between the diodes D 17 and D 18 , and a capacitor C 42 is connected between the point m and the connection point o between the diodes D 19 and D 20 . 43 are connected. A capacitor C 51 is connected between the connection point g of the diodes D 11 and D 12 and the output terminal e point. The output end A is connected to the i point, and the output end B is connected to the l point.

即ち、トランスTの中間タツプC点を接地Gと
した場合、トランスTの出力端a,b,d,eの
各点にはそれぞれC点に対し415V,320V,
200V,500Vの矩形波交流電圧が発生していると
する。先ず、この回路の出力端G,A間について
考察すると、トランスTの出力端b,eとダイオ
ードD11,D12,D13およびコンデンサC21,C31
C51によつて1段の倍電圧整流回路が構成されて
いることが解る。従つて、本回路の出力端G,A
間にはトランスTの出力端b,e間電圧820Vの
倍の電圧1640Vが発生することになる。同様に本
回路の出力端A,B間に関してはトランスTの出
力端b,d、ダイオードD14,D15,D16およびコ
ンデンサC22,C32,C41によつて1段の倍電圧整
流回路が構成されているので、この出力端A,B
間にはトランスTの出力端b,d間電圧520Vの
倍の電圧1040Vが発生し、出力端Bには接地電位
Gに対し5140Vが発生する。
In other words, if the intermediate tap C point of the transformer T is grounded G, the output terminals a, b, d, and e of the transformer T have voltages of 415V, 320V, and 320V, respectively, relative to point C.
Assume that square wave AC voltages of 200V and 500V are generated. First, considering the output terminals G and A of this circuit, the output terminals b and e of the transformer T, the diodes D 11 , D 12 , D 13 and the capacitors C 21 , C 31 ,
It can be seen that a one-stage voltage doubler rectifier circuit is constructed by C51 . Therefore, the output terminals G and A of this circuit
A voltage of 1640V, which is twice the voltage of 820V between output terminals b and e of the transformer T, is generated between them. Similarly, between output terminals A and B of this circuit, one-stage voltage double rectification is performed by output terminals b and d of transformer T, diodes D 14 , D 15 , D 16 and capacitors C 22 , C 32 , and C 41. Since the circuit is configured, these output terminals A and B
A voltage of 1040V, which is twice the voltage 520V between the output terminals b and d of the transformer T, is generated therebetween, and a voltage of 5140V is generated at the output terminal B with respect to the ground potential G.

以上の如く、従来は複数トランス、複数整流回
路の組合せによつてしか実現できなかた任意の複
数出力も、適当な中間タツプを設定した1個のト
ランスとの組合せにより容易に構成可能となつ
た。
As described above, arbitrary multiple outputs, which could conventionally be realized only by a combination of multiple transformers and multiple rectifier circuits, can now be easily configured by combining with one transformer with an appropriate intermediate tap.

又、トランスTの中間タツプCとダイオード群
との接続は必ずしもC点に限らず、出力コンデン
サC31,C32,C33とダイオードとの接点ならば任
意に選べる。この場合、接地点をどこに選ぶかに
よつてトランスTの1次、2次間耐電圧或いはト
ランスTの出力端に直接接続されているコンデン
サ(第2図の場合、C11,C21,C22,C41,C51
の耐電圧要求に変更を要するが動作的には全く同
様であり、又回路の出力端間電圧も同一に保たれ
る。
Further, the connection between the intermediate tap C of the transformer T and the group of diodes is not necessarily limited to the point C, but can be arbitrarily selected as long as it is the contact point between the output capacitors C 31 , C 32 , C 33 and the diodes. In this case, depending on where the grounding point is selected, the withstand voltage between the primary and secondary of the transformer T or the capacitors directly connected to the output terminal of the transformer T (in the case of Fig. 2, C 11 , C 21 , C 22 , C41 , C51 )
Although the withstand voltage requirement of the circuit is changed, the operation is exactly the same, and the voltage between the output terminals of the circuit is also kept the same.

以上の説明から明らかなように、上記構成によ
る多倍圧整流回路は、トランスTの出力巻線に設
けられた中間タツプb,cの一つを多倍圧整流回
路の基準電位点(図ではアース)とし、その一方
側のタツプa,bに接続されるコンデンサC1,
C2(C11,C12,C21,C22)と他方
側のタツプdに接続されるコンデンサC4(C4
1〜C43,C51)が交互に充放電状態となつ
て出力コンデンサC3(C31〜C33)を充電
するため、全波整流出力となる。この結果、出力
巻線の一方端を基準電位点に接続して半波整流出
力とする回路構成の場合に比較して、リプル電圧
を抑圧し、かつ負荷答性を向上させることができ
る。
As is clear from the above explanation, the multi-voltage rectifier circuit with the above configuration connects one of intermediate taps b and c provided on the output winding of the transformer T to the reference potential point of the multi-voltage rectifier circuit (in the figure). capacitor C1, which is connected to taps a and b on one side.
C2 (C11, C12, C21, C22) and the capacitor C4 (C4
1 to C43, C51) alternately enter a charging/discharging state to charge the output capacitor C3 (C31 to C33), resulting in a full-wave rectified output. As a result, ripple voltage can be suppressed and load response can be improved compared to a circuit configuration in which one end of the output winding is connected to a reference potential point to provide a half-wave rectified output.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、多倍圧整流
回路と組合わされるトランスの出力巻線に複数個
の中間タツプを設け、その一つの中間タツプを基
準電位点に接続し、他タツプから得られる異なる
電圧を組合せることにより、任意の出力電圧を設
定することができ、かつ1つの多倍圧整流回路か
ら複数出力を得る場合もその出力電圧間の比率を
任意に設定できる多倍圧整流回路を提供すること
ができる。
As described above, according to the present invention, a plurality of intermediate taps are provided on the output winding of the transformer combined with the multiplier rectifier circuit, one of the intermediate taps is connected to the reference potential point, and the other taps are connected to the reference potential point. By combining the different voltages obtained, it is possible to set any output voltage, and even when obtaining multiple outputs from one multiplier rectifier circuit, the ratio between the output voltages can be set arbitrarily. A rectifier circuit can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2
図は本発明の他の実施例を示す回路図である。 T……トランス、D1〜D4,D11〜D21……ダイ
オード、C1〜C4,C11,C12,C21,C22,C31,〜
C33,C41〜C43,C51……コンデンサ。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing another embodiment of the present invention. T...Transformer, D1 ~ D4 , D11 ~ D21 ...Diode, C1 ~ C4 , C11, C12 , C21 , C22 , C31 , ~
C 33 , C 41 to C 43 , C 51 ... Capacitors.

Claims (1)

【特許請求の範囲】 1 出力巻線に複数個の中間タツプが設けられ、
一つの中間タツプが基準電位点に接続されて基準
タツプとなり、基準タツプより一方側のタツプが
第1の出力タツプ、他方側のタツプが第2の出力
タツプとなるトランスと、 複数個のダイオードを互いに整流の向きが同一
になる如く直列接続して構成され、前記複数個の
ダイオードのうち一つのダイオードの一方端が前
記基準タツプに接続されるダイオード回路と、 1個以上直列に接続され、一方端が前記基準電
位点に接続され、前記ダイオード回路の3個以上
のダイオードに並列接続される出力コンデンサ
と、 前記第1の出力タツプ毎に設けられ、それぞれ
1個以上直列接続され、一方端が前記第1の出力
タツプに接続される第1のコンデンサと、 前記第2の出力タツプ毎に設けられ、それぞれ
1個以上直列接続され、一方端が前記第2の出力
タツプに接続される第2のコンデンサとを具備
し、 前記第1、第2のコンデンサの各他方端を前記
ダイオード回路の各ダイオード間接続点のうち前
記出力コンデンサが接続されていない接続点に交
互に接続するようにしたことを特徴とする多倍圧
整流回路。
[Claims] 1. The output winding is provided with a plurality of intermediate taps,
One intermediate tap is connected to a reference potential point and serves as a reference tap, the tap on one side of the reference tap serves as the first output tap, and the tap on the other side serves as the second output tap. A transformer and multiple diodes are used. The plurality of diodes are connected in series so that their rectification directions are the same, and one or more diodes are connected in series with a diode circuit in which one end of one of the plurality of diodes is connected to the reference tap. an output capacitor whose end is connected to the reference potential point and which is connected in parallel to three or more diodes of the diode circuit; a first capacitor connected to the first output tap; and a second capacitor provided for each second output tap, one or more of which are connected in series, and one end of which is connected to the second output tap. and a capacitor, the other end of each of the first and second capacitors being alternately connected to a connection point to which the output capacitor is not connected among the connection points between the diodes of the diode circuit. A multi-voltage rectifier circuit featuring:
JP6936683A 1983-04-20 1983-04-20 Voltage multiplying rectifier circuit Granted JPS59194667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6936683A JPS59194667A (en) 1983-04-20 1983-04-20 Voltage multiplying rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6936683A JPS59194667A (en) 1983-04-20 1983-04-20 Voltage multiplying rectifier circuit

Publications (2)

Publication Number Publication Date
JPS59194667A JPS59194667A (en) 1984-11-05
JPH0440948B2 true JPH0440948B2 (en) 1992-07-06

Family

ID=13400482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6936683A Granted JPS59194667A (en) 1983-04-20 1983-04-20 Voltage multiplying rectifier circuit

Country Status (1)

Country Link
JP (1) JPS59194667A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6185070A (en) * 1984-09-28 1986-04-30 Toshiba Corp Multioutput double voltage rectifier
EP1199788A1 (en) * 2000-10-17 2002-04-24 STMicroelectronics S.r.l. Inductive DC-to-DC switching converter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51620A (en) * 1974-06-21 1976-01-06 Toko Inc DENGEN KAIRO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51620A (en) * 1974-06-21 1976-01-06 Toko Inc DENGEN KAIRO

Also Published As

Publication number Publication date
JPS59194667A (en) 1984-11-05

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