JPH0439091U - - Google Patents
Info
- Publication number
- JPH0439091U JPH0439091U JP7985990U JP7985990U JPH0439091U JP H0439091 U JPH0439091 U JP H0439091U JP 7985990 U JP7985990 U JP 7985990U JP 7985990 U JP7985990 U JP 7985990U JP H0439091 U JPH0439091 U JP H0439091U
- Authority
- JP
- Japan
- Prior art keywords
- switching element
- circuit
- switching
- inductor
- antiparallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 9
Landscapes
- Circuit Arrangements For Discharge Lamps (AREA)
- Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)
Description
第１図はこの考案の第１の実施例のインバータ
装置の構成を示す回路図、第２図は第１図のイン
バータ装置の各部の動作波形図、第３図はこの考
案の第２の実施例の構成を示す回路図、第４図は
この考案の第３の実施例の構成を示す回路図、第
５図は従来のインバータ装置の構成を示す回路図
、第６図は第５図の回路の具体構成を示す回路図
、第７図は第６図の各部の動作波形図、第８図は
同じく欠点を説明するための各部の動作波形図で
ある。
Ｑ１，Ｑ２……スイツチング素子、Ｚ……負荷
回路、ｌ……負荷、Ｌ１……インダクタ、Ｃ１…
…コンデンサ、Ｃ０……結合用コンデンサ、Ｘ１
……スイツチング素子制御手段、ＦＢ２……帰還
手段。
Fig. 1 is a circuit diagram showing the configuration of an inverter device according to a first embodiment of this invention, Fig. 2 is an operation waveform diagram of each part of the inverter device shown in Fig. 1, and Fig. 3 is a circuit diagram showing a configuration of an inverter device according to a first embodiment of this invention. FIG. 4 is a circuit diagram showing the configuration of a third embodiment of this invention, FIG. 5 is a circuit diagram showing the configuration of a conventional inverter device, and FIG. 6 is a circuit diagram showing the configuration of a conventional inverter device. FIG. 7 is a circuit diagram showing a specific configuration of the circuit, FIG. 7 is an operation waveform diagram of each part of FIG. 6, and FIG. 8 is an operation waveform diagram of each part for explaining the drawbacks. Q 1 , Q 2 ... switching element, Z ... load circuit, l ... load, L 1 ... inductor, C 1 ...
...Capacitor, C 0 ...Coupling capacitor, X 1
... Switching element control means, FB 2 ... Feedback means.
Claims (1)
チング素子の直列回路を接続し、前記第１および
第２のスイツチング素子に第１および第２のダイ
オードをそれぞれ逆並列接続し、前記第１のスイ
ツチング素子の両端子間にインダクタおよび負荷
の直列回路を含む負荷回路を結合用コンデンサを
介して接続し、前記インダクタの両端電圧を前記
第１のスイツチング素子の制御端子に帰還して所
定周期で前記第１のスイツチング素子をオンオフ
させる帰還手段を設け、前記第１のスイツチング
素子のオフを検出して起動するタイマ回路のタイ
マ動作期間中前記第２のスイツチング素子をオン
にするとともに前記タイマ回路のタイマ動作終了
後に前記第１のスイツチング素子をオフにするス
イツチング素子制御手段を設けたインバータ装置
。 A series circuit of first and second switching elements is connected between both terminals of a DC power supply, first and second diodes are respectively connected in antiparallel to the first and second switching elements, and the first and second switching elements are connected in antiparallel. A load circuit including a series circuit of an inductor and a load is connected between both terminals of the switching element via a coupling capacitor, and the voltage across the inductor is fed back to the control terminal of the first switching element to Feedback means for turning on and off the first switching element is provided, and the feedback means turns on the second switching element during the timer operation period of the timer circuit that detects the off state of the first switching element and starts the timer circuit. An inverter device comprising switching element control means for turning off the first switching element after the operation is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7985990U JP2547323Y2 (en) | 1990-07-25 | 1990-07-25 | Inverter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7985990U JP2547323Y2 (en) | 1990-07-25 | 1990-07-25 | Inverter device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0439091U true JPH0439091U (en) | 1992-04-02 |
| JP2547323Y2 JP2547323Y2 (en) | 1997-09-10 |
Family
ID=31624405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7985990U Expired - Lifetime JP2547323Y2 (en) | 1990-07-25 | 1990-07-25 | Inverter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2547323Y2 (en) |
-
1990
- 1990-07-25 JP JP7985990U patent/JP2547323Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2547323Y2 (en) | 1997-09-10 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |