JPH0439036U - - Google Patents

Info

Publication number
JPH0439036U
JPH0439036U JP8127390U JP8127390U JPH0439036U JP H0439036 U JPH0439036 U JP H0439036U JP 8127390 U JP8127390 U JP 8127390U JP 8127390 U JP8127390 U JP 8127390U JP H0439036 U JPH0439036 U JP H0439036U
Authority
JP
Japan
Prior art keywords
resistor
startup
inrush current
transistor switch
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8127390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8127390U priority Critical patent/JPH0439036U/ja
Publication of JPH0439036U publication Critical patent/JPH0439036U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路構成図、
第2図は従来技術の回路図である。 1……スイツチ、2……ヒユーズ、3……抵抗
器、4……コンデンサ、5……パワーMOSFE
T、6……変圧器、7,8……ダイオード、9…
…チヨークコイル、10……コンデンサ、11…
…パワーMOSFET、12,13……抵抗器、
14,15……ダイオード、16……コンデンサ
、17……ダイオード、18,19……抵抗器、
20……トランジスタ、21,22……抵抗器、
23……トランジスタ、24,25……抵抗器、
26……トランジスタ、11′……リレー、12
′……リレー11′のメイク接点、13′……リ
レー11′のブレイク接点。
FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is a circuit diagram of the prior art. 1...Switch, 2...Fuse, 3...Resistor, 4...Capacitor, 5...Power MOSFE
T, 6...Transformer, 7, 8...Diode, 9...
...Chiyoke coil, 10...Capacitor, 11...
...Power MOSFET, 12, 13...Resistor,
14, 15... Diode, 16... Capacitor, 17... Diode, 18, 19... Resistor,
20...transistor, 21,22...resistor,
23...transistor, 24,25...resistor,
26...Transistor, 11'...Relay, 12
'...Make contact of relay 11', 13'...Break contact of relay 11'.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 起動時に入力に流れる突入電流を制限する抵抗
器と、起動時にこの抵抗器を短絡するパワーMO
SFETスイツチと、異常時に外部へアラーム信
号を送出するトランジスタスイツチを備えること
を特徴とするトランジスタスイツチによる突入電
流制限/アラームシステム。
A resistor that limits the inrush current flowing to the input at startup, and a power MO that shorts this resistor at startup.
An inrush current limiting/alarm system using a transistor switch, characterized by comprising an SFET switch and a transistor switch that sends an alarm signal to the outside in the event of an abnormality.
JP8127390U 1990-07-31 1990-07-31 Pending JPH0439036U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8127390U JPH0439036U (en) 1990-07-31 1990-07-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8127390U JPH0439036U (en) 1990-07-31 1990-07-31

Publications (1)

Publication Number Publication Date
JPH0439036U true JPH0439036U (en) 1992-04-02

Family

ID=31627069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8127390U Pending JPH0439036U (en) 1990-07-31 1990-07-31

Country Status (1)

Country Link
JP (1) JPH0439036U (en)

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