JPH0438868A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To equalize time lag required until a control signal enters a transistor gate by installing wirings where a control signal line designed to transmit a control signal and a contact section of a gate electrode wiring for a transistor are interconnected with each other symmetrically at an equal space from each transistor. CONSTITUTION:Two aluminum wirings 3-1, and 3-2, which transmit a control signal are laid out on both ends while transistors M1 installed to a pair of digit lines D1 are paired in both sides. The length of electrode wirings 4, which are laid out from the aluminum electrode wirings 3-1 and 3-2 to the paired transistors M1, are designed in the same shape respectively. Therefore, both the transistors M1 undergo the same effect from a coupling capacity C1, which equalizes the wiring resistors so that R2 may be identical to R1, and further equalizes time lag so that the following equation may be obtained: tau A=C1R1= C1R2=tau B. Therefore, this eliminates any potentiality, thereby preventing a drop in the sensitivity of a sense amplifier.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

In conventional semiconductor memory devices, especially DRAMs, as memory cells become smaller, the transistors that make up the transfer gates provided on a pair of digit lines cannot be arranged vertically at the same position. , two transistors Ml.

The structure is such that the Ml are arranged side by side, and on the left side, an aluminum wiring 3 is placed vertically to send a control signal of the transfer gate, and a gate electrode wiring 4 is connected from the aluminum wiring 3 to the transistor to send a signal to the transistor gate. Ta.

FIG. 5 shows a circuit diagram corresponding to the schematic plan view of FIG. The control signal line 3 intersects perpendicularly with the control signal line 3 and sends a control signal to the transistor gates (Ml, Ml). Gate signal line and digit line D1. D
There is a coupling capacitance C1 between the control signal line and the gate signal line, and the contact point between the control signal line and the gate signal line is connected to C and the digit line "".
Assuming that the contact point between the gate wiring (the gate is an extension of the pole) of the transistor Ml connected to the gate signal line is A, a wiring resistance R1 exists between the contact point C and the contact point A. or,
A wiring resistance R2 exists between a contact point B and a contact point A between the gate wiring of the transistor M1 connected to the digit line D1 and the gate signal line. In the transistors M1, M1, coupling capacitances C2A, C2B, C3A, and C3B exist between the gates and the impurity diffusion layers due to overlap.

In such a circuit diagram, when a control signal is transmitted,
The transistors constituting the transfer gate are turned off, and the digit line pair DI.

DI- is electrically cut off before and after the transistor. In this state, the sense amplifier SA amplifies the data, but
Since the digit line is cut by a transistor, amplification becomes faster.

In Figure 5, the control signal is transmitted through contact C, and the control signal is transmitted through contact A.
The delay time until the control signal reaches the contact point C is determined by τA=CI R1, and the delay time until the control signal reaches the contact point B is determined by τB=CI (R1→−R2>).In this way, In the conventional configuration, the delay time until the gate signal is transmitted in the two transistors provided in the digit line pair is different from each other.

[Problem to be solved by the invention]

In the conventional semiconductor memory device described above, the lengths of the gate electrode wires for transmitting control signals are different in the transistors forming the transfer gate provided on the pair of digit lines D-, so that the digit line DI There is a difference in the delay time until a signal is transmitted to the transistor M1 of the transistors M1 and D1'. FIG. 4 shows the voltage waveform of the digit line in a conventional layout. When a control signal is transmitted from the control signal line to the gate electrode wiring (timing t1), the digit Line voltage drops slightly. The slope of this voltage drop is the coupling capacitance C
1 and continues to fall until the control signal is transmitted to the transistor (timing t1 or t2). Therefore, if the delay times are different, a potential difference as shown in FIG. 4 is generated.

FIGS. 4(d) and 4(e) show the voltage waveforms of the digit lines at points after passing through the transistors. The voltage of F is C1 from timing tl to timing t2, which is τA.
It continues to decrease due to the coupling caused by C2A, and from t2 until t4 when the gate voltage of Ml reaches the threshold value Vd,
The reduction due to C2B is added. At T4) viT is turned off, and the decrease due to C1 and C2A ends.

Similarly, the voltage of DI continues to decrease due to 01 until t3, when τB has elapsed from tl, and the decrease due to C3A and C3B is added until t5. There is no difference between △V1 and △Vl for Via (
The final voltage of DI when τA=τB), the margin of the sense amplifier is reduced by Δ■ of the difference between Via and Vlb. The longer the baby grows, the lower the pressure detection sensitivity will be.

As described above, there is a drawback that the sensitivity of the sense amplifier decreases due to the difference in time during which a control signal is transmitted to the two MOS transistors inserted between the sense amplifier and the digit line.

[Means to solve the problem]

The present invention provides a semiconductor memory device having a first MIS transistor and a second MIS transistor inserted between each of a pair of digit lines and a sense amplifier. Each gate electrode wiring of the second MIS transistor is arranged symmetrically and equidistantly from a contact portion with a control signal wiring that transmits a control signal of each MIS transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a planar schematic diagram showing a first embodiment of the present invention. Two aluminum wiring lines 3-1 and 3-2 (control signal lines) for transmitting control signals are arranged at both ends, and a pair of digit lines D
1. Transistors Ml, Ml provided in DI,...
are in pairs on the left and right. Aluminum wiring 3-1.
The lengths of the gate electrode wires from the contacts kl, 1-2 of the gate electrode wires 3-2 and 4 to the pair of transistors M1, M1 are equal and have the same shape. Therefore, the coupling capacitance C1 affects both the transistor M1 and the transistor M1 in the same way, and the wiring resistance R shown in FIG.
1 and the wiring resistance R2 becomes R1=R2, and the delay time becomes equal to τA=CIR1=CIR2−τB. As above, if the delay times are equal,
Transistors Ml and Ml as shown in FIG. 4(b) and (c)
The time lag in the gate voltage waveforms disappears, and the voltages on the pair of digit lines DI, DI, . . . have the same waveform as shown in FIG. This eliminates the potential difference and prevents the sense amplifier from decreasing in sensitivity.

FIG. 2 is a schematic plan view showing a second embodiment of the present invention. The two transistors provided on the pair of digit lines are paired on the left and right, except for the transistors M3 and M3, and the aluminum wiring 3 for transmitting the control signal is arranged in the shape of a cross in the center.

In this example, five pairs of tigits are refined.
For example, three digit line pairs may be refined as shown in the area surrounded by dotted lines. Either 3 pairs or 5 pairs may be selected and designed according to the shape of the memory cell.

In the above description, it is assumed that the digit line is made of a polycide film in which a polysilicon film and a tungsten silicide film are laminated, and that the gate electrode wiring is made of a polysilicon film. Therefore, the length of the gate electrode wiring with relatively high resistance was discussed.

〔Effect of the invention〕

As explained above, in the present invention, in two transistors provided between a pair of digit lines and a sense amplifier, the contact portion between the control signal line for transmitting a control signal and the gate electrode wiring of the transistor is By providing symmetrical wiring equidistant from , the delay time until the control signal is input to the transistors K1 to 1 becomes equal.

Therefore, there is an effect that it is possible to avoid deterioration of the sense amplifier margin or detection sensitivity due to the above-mentioned delay difference, which is a problem in small memory cells.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing a first embodiment of the present invention, FIG. 2 is a schematic plan view showing a second embodiment of the present invention, and FIG.
4 is a schematic plan view showing a conventional example, FIGS. 4(a) to 4(e) are waveform diagrams for explaining the drawbacks of the conventional example, and FIG. 5 is an equivalent circuit diagram of the conventional example shown in FIG. 1-1.1-2...Contact, 2...Diffusion layer, 3.3
-1.3-2...Aluminum wiring, D1 ■, D2
．． D Ding,..., D5. D line... digit line, 4.
...Gate electrode wiring, Ml, Ml...MOS transistor.

Claims (1)

[Claims] A first MIS transistor and a second MIS transistor inserted between each of the pair of digit lines and the sense amplifier.
In a semiconductor memory device having an IS transistor, each gate electrode wiring of the first and second MIS transistors is arranged symmetrically and equidistantly from a contact portion with a control signal wiring that transmits a control signal of each of the MIS transistors. A semiconductor memory device characterized in that: 2. The semiconductor memory device according to claim 1, wherein the control signal wiring is an aluminum wiring and the gate electrode wiring is a polysilicon wiring.