JPH0438569A - Picture processor - Google Patents

Abstract

PURPOSE:To eliminate the trouble of operation and to prevent the lowering of a working rate by providing a selecting means to select a processing system to process different code systems in a picture processor to generate picture data by code information from an external part. CONSTITUTION:The respective programs (processing systems A, B and C) of a picture processor execute picture forming processing by respective code systems based on picture processing information from a host computer. The processing systems A, B and C execute the picture forming processing of a dot pattern and so on. When processing system information is received from the host, the contents of it are set in a processing system indicating area at a step 2. The processing system is determined corresponding to the value of the above mentioned processing system indicating area at a step 3 and the starting address setting area. The input of picture information is waited at a step 4 and when the picture information is inputted, the processing of the picture information is executed along the applying code system form the starting address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that generates image data based on code information sent from the outside.

[Prior Art] In a conventional image processing device that can process multiple code systems, when processing image processing information sent in code from a host computer, it is necessary to determine which of the multiple code systems to process. System settings are performed using an operation panel that is part of the image processing device or a dedicated switch provided within the image processing device.

[Problems to be Solved by the Invention] However, when changing the coding system of image processing information sent from a host computer, it is necessary to change the application of the image processing device using the operation panel or dedicated switch that is part of the image processing device. The troublesome operation of resetting the processing system was required.

In particular, computer networks such as local area networks are expected to become even more popular in the future.
Accordingly, it is expected that there will be an increase in the number of opportunities for image processing apparatuses to be installed in locations separated from host computers in network environments. Therefore, under such circumstances,
The location where the image processing device is installed may be so far away that it cannot be easily accessed from the location where the host computer is located, so the image processing device may be In the conventional method of configuring the processing system to which the system is applied, not only is the operation cumbersome, but it is expected that it will take more time than the conventional method to reset the settings.

In this way, if it takes more time than before to reconfigure the processing system applied to the image processing device, the result is that the host computer, image processing device, and The down time of an image forming unit such as a printer that performs printing according to instructions from an image processing apparatus becomes longer than before, and the operating rate is significantly reduced.

The present invention eliminates the above-mentioned conventional drawbacks, and provides an image processing device that allows a plurality of processing systems to be easily selected from an external device such as a host computer, eliminates troublesome operations, and prevents a decrease in operating rate. do.

[Means for Solving the Problem] In order to solve this problem, the image processing device of the present invention has the following features:
consisting of at least two organized sets of code information
an image processing apparatus having a processing system corresponding to one of the at least two different code systems, the image processing apparatus comprising: receiving means for receiving from the outside information representing one of the at least two different code systems; , and selection means for selecting a processing system that processes the code system corresponding to the information.

[Operation] In such a configuration, by determining the processing system of the code system to be applied when the image processing device processes image processing information in accordance with instructions from an external device such as a host computer, the troublesome operation is eliminated and the operating rate is improved. prevent the decline of

[Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

<Configuration of Conventional Device> First, an example of the hardware configuration of a conventional image processing device will be described with reference to FIG.

In the figure, reference numeral 1 denotes an input unit for inputting image processing information 2 from a host computer (not shown) in the form of a code, and the code data input through the input unit 1 is stored in a page memory 3 under the control of the CPU 5. The memory 3 has a capacity to store at least one page of code data, and stores character codes, graphic formation information, and control information in the order sent from the input section 1. 4 is a font memory that stores character pattern data corresponding to character codes, and CPU 5 is a character code.

Program RO such as an interpreter that analyzes code data of figure formation information and control information to form a dot pattern.
According to the processing program stored in M8, the font memory 4 is accessed based on the character code data stored in the page memory 3, the corresponding pattern data is read out, and the pattern is developed in the dot pattern memory 6.

Further, a control program for controlling the entire device is stored in the program ROM 8, and the CPU 5 controls the entire device according to the control program. 7 is C
A working random access memory (RAM) is used to read and write temporary various data used when the PU 5 performs processing according to the program stored in the program ROM 8. 6 is a dot stored in the program ROM 8. A dot pattern memory that stores dot butter and pattern data developed by a processing program for pattern formation, and can accommodate at least one page of pattern data corresponding to the code data in the page memory 3. .

9 inputs the dot pattern data from the dot pattern memory 6 and outputs it to the image forming section interface section 10.
t) memory. The image forming unit interface unit 10 receives image data (dot pattern data) from the FIFO 9.
The image is sent to an image forming unit such as a printer (not shown) and printed. Reference numeral 12 denotes an operation panel such as a keyboard, through which the operator inputs various instructions such as image formation instructions and error reset. The signal input from the operation panel 12 is
Data bus 1 via operation panel interface section 11
3 and the address bus 14. Further, the clock signal 30 output from the clock generation circuit 15 is transmitted to the CPU 5.
used as a clock signal.

<Configuration of Image Processing Apparatus of First Embodiment> FIG. 1 is a block diagram showing the hardware configuration of the image processing apparatus of this embodiment. Components other than the host-to-host communication interface section 20 and the host-to-host communication line 40 in FIG. 1 perform the same functions as those in the conventional example shown in FIG. 7 described above.

20 is an inter-host communication interface unit for performing general-purpose communication between the image processing device and the host computer;
Communication signals from the image processing device to the host computer are output to the host computer through the host-to-host communication interface section 20, and communication signals from the host computer to the image processing device are input to the image processing device through the host-to-host communication interface section 20. 40 is an inter-host communication line used for general-purpose communication between the image processing apparatus and the host computer.

FIG. 2 is a memory map within the program ROM 5 of the processing program stored in the program ROM 8 of FIG. Each processing program (processing system A, B, C
) performs image formation processing using each code system based on image processing information from the host computer. FIG. 3 shows information for selecting a processing system secured in the working RAM 7 used by the CPU 5 in FIG. 1. This is the memory map of

Processing system A, processing system B, and processing system C in FIG. 2 are processing programs that perform image forming processing such as forming a dot pattern based on image processing information from a host computer, and each processing system uses a different code system. can be processed.

When performing image forming processing, one processing system is selected from these processing systems and executed by the CPU 5.

Also, the start address AAA to the processing system.

Starting address BBB of processing system B and starting address C of processing system C
CC is the start address of processing system A, processing system B, and processing system C in the program ROM 8 in FIG. 1, respectively.

The processing system instruction area 56 in the memory map shown in FIG. 3 is an area for setting information regarding the processing system shown in FIG. Yes, if you are instructed to apply the processing system in Figure 2 as a processing system that processes image processing information sent from the host computer, enter "1", and if you are instructed to apply processing system B, enter "1". "2" is set, and "3" is set when application of processing system C is instructed. Immediately after the power is turned on to the image processing device,
“0” is set in the processing system instruction area 56. The starting address setting area 57 in the memory map in FIG. 3 is an area for setting the starting address of the processing system in FIG. 2 based on the settings in the processing system instruction area 56, and the setting contents in the processing system instruction area 56 are l”, set the start address AAAA of processing system A to “2
”, the start address BBBB of processing system B, “3”, the start address cccc of processing system C, and “0”, “
-1”.

When the image processing apparatus performs image forming processing based on image processing information from the host computer, the image forming processing is performed according to a processing program starting from the starting address set in the starting address setting area 57. If -1'' is set in the area 57, no image forming process is performed because the host computer has not instructed the image processing apparatus to apply a processing system.

4A and 4B are flowcharts illustrating the operating procedure of this embodiment using the hardware configuration of FIG. 1, the processing program of FIG. 2, and the memory map of FIG. 3. Here, the flowcharts shown in FIGS. 4A and 4B are executed by the CPU 5 after a control program based on the flowcharts is stored in the program ROM 8 shown in FIG. FIG. 4A shows the overall flow, and FIG. 4B shows the processing system determination routine in step S3 in FIG. 4A.

In FIG. 4A, first in step S1, processing system information from the host computer is waited for.

When the processing system information is received by the host-to-host communication interface section 2o, the process proceeds to step S2, and its contents are set in the processing system instruction area 56. Note that the processing system information may be "1" to "3" itself set in the processing system instruction area 56, or may be data representing the processing system, and is
It may also be converted into "1" to "3". In step S3, a processing system is determined according to the value in the processing system instruction area 56, and the start address of the processing program is set in the start address setting area 56.
Set to 7. In step S4, the input of image information from the host to the input unit 1 is waited, and when the image information is input, the process proceeds to step S5, where the image information is inputted from the start address set in the start address setting area 57 in step S3. Process according to the code system.

In the flowchart of FIG. 4B, step S31 is a step in which the subsequent flow is determined based on the settings in the processing system instruction area 56. If the setting content is "0" or less, the process proceeds to step S38, and since the host computer has not instructed the image processing apparatus as to which processing system the image processing apparatus should apply as the processing system for image processing information,
-1'' is set in the start address setting area 57 as an invalid start address that means that.

On the other hand, if it is larger than "0", steps S32 to S37
Steps S32 to S34. In S36, the subsequent flow is determined based on the settings in the processing system instruction area 56. If the setting content is "l", steps S32 to S
Proceeding to step 33, the host computer instructs the application of processing system A shown in FIG. Set. The settings are “
2", the process proceeds from step S34 to S35, and the host computer has instructed the application of processing system B in FIG. 2 as the image processing information processing system to be applied to the image processing apparatus, so the start address is set. The start address BBBB of the processing system B is set in the area 57. If the setting content is "3", the process advances from step S36 to S37, and the fourth host computer sets the start address BBBB of the processing system B as the processing system for the image processing information to be applied by the image processing apparatus. Since it is instructed to apply the processing system C shown in Figure 2, the start address cccc of the processing system C is set in the start address setting area 57. If "l" is not "2" or "3", exit the routine without doing anything. .

Configuration of Image Processing Apparatus of Second Embodiment> FIG. 5 is a block diagram showing the hardware configuration of the second embodiment of the present invention. In FIG. 5, the processing system instruction signal input section 21. Components other than the processing system A instruction signal 41, the processing system B instruction signal 42, and the processing system C instruction signal 43 perform the same functions as those of the conventional example shown in FIG.

21 transmits the processing system instruction signal from the host computer to the fifth
This is a processing system instruction signal input section that inputs processing system instruction signals to the image processing apparatus shown in the block diagram of FIG. The processing system B instruction signal 42 and the processing system C instruction signal 43 are input to the image processing apparatus through the processing system instruction signal input section 21.

Instruction signals 41, 42 and 43 indicate which of the processing systems shown in FIG. 2 should be applied to the image processing apparatus when the image processing apparatus performs image forming processing based on image processing information from the host computer. Processing system instruction signal used by the computer to instruct the image processing device; processing system A
When the instruction signal 41 is in the high state, the image processing device applies the processing system A in FIG. 2, and when the processing system B instruction signal 42 is in the high state
When the processing system C instruction signal 43 is in the high state, the image processing apparatus applies the processing system B shown in FIG. 2. When the processing system C instruction signal 43 is in the high state, the image processing apparatus applies the processing system C shown in FIG.

However, processing system A instruction signal 41. Processing system B instruction signal 42
If two or more of the three instruction signals of the processing system C instruction signal 43 and the processing system C instruction signal 43 are in a high state at the same time, the image processing apparatus ignores the processing system instruction based on these instruction signals.

FIG. 6 is a flowchart showing the processing procedure of this embodiment using the processing program shown in FIG. 2, the hardware configuration shown in FIG. 5, and the memory map shown in FIG. However, in this embodiment, unlike the first embodiment, immediately after the power is turned on to the image processing apparatus, the start address AAAA of the processing system A is set as the initial value of the processing system in the start address setting area 57 in FIG. is set. Here, the flowchart shown in FIG. 6 is executed by the CPU 5 after a control program based on this flowchart is stored in the program ROM 8 shown in FIG. Note that the routine in FIG. 6 includes steps S2. in FIG. 4A. Replaced by S3. Further, when the image processing apparatus performs image forming processing based on image processing information from the host computer, the processing program starting from the starting address set in the starting address setting area 57 creates an image. Perform the forming process.

In the flowchart of FIG. 6, in step S61, the processing system A instruction signal 41. It is checked whether two or more of the three instruction signals, processing system B instruction signal 42 and processing system C instruction signal 43, are in a high state at the same time. If two or more are in the high state at the same time, the processing system determination processing routine is ended.

If there is not a plurality of starting devices, the starting device for each processing system is set in steps S62 to S67 based on the instruction signals 41 to 43. When the processing system A instruction signal 41 is in a high state, the process advances from step S62 to S63, and the start address setting area 57 is set as the processing system for image processing information applied by the image processing apparatus.
The start address AAAA of processing system A is set in . If the processing system B instruction signal 42 is in a high state, the process advances from step S64 to S65, and the start address BBBB of the processing system B is set in the start address setting area 57 as the processing system for image processing information applied by the image processing apparatus. do. If the processing system C instruction signal 43 is in a high state, the process advances from step S66 to S67, and the start address cc of the processing system C is set in the start address setting area 57 as the processing system for image processing information applied by the image processing apparatus.
Set cc. If any signal is Low, the routine exits without doing anything.

In the first and second embodiments described above, the image processing apparatus sets the start address of the processing system applied to the image forming process to the working RAM based on instructions from the host computer.
However, if the power supply to the image processing device is cut off, the written memory content will be lost. Therefore, as a place to secure the start address setting area 57, The image processing device is powered on, ensuring that the written memory content is preserved in memory that will not be lost even if the power supply to the image processing device is cut off, such as memory with a backup battery or non-volatile memory. Immediately thereafter, a processing program starting from the start address that was set in the start address setting area 57 at the time when the power supply to the previous image processing apparatus was cut off can be applied to the image forming process.

Furthermore, in the first and second embodiments described above, the host computer could only instruct the image processing apparatus as to one processing system to be applied to the image forming process; A plurality of areas are secured in the working RAM 7, and the start addresses of the processing system instructed by the host computer are stored in the order of instruction in the plurality of start address setting areas, and image forming processing based on image information from the host computer is performed. In this case, the processing system may be changed for each page according to the order of the start addresses of the processing systems set in a plurality of start address setting areas.

As explained above, according to this embodiment, each time the code system of image processing information sent from a host computer to an image processing apparatus is changed, the code applied by the image processing apparatus on the image processing apparatus is changed. This eliminates the trouble of having to reconfigure the system's processing system, and at the same time, it is easy to configure the image processing system's processing system even if the image processing device is installed in a remote location from the host computer. The host computer, the image processing device, and the image forming unit such as a printer that performs printing according to instructions from the image processing device, which are expected when setting up the processing system of the image processing device in an environment that is installed in a remote location from the host computer. It is possible to prevent a decrease in the operating rate.

[Effects of the Invention] The present invention provides an image processing apparatus that allows a plurality of processing systems to be easily selected from an external device such as a host computer, eliminates troublesome operations, and prevents a decrease in operating rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the hardware configuration of the image processing device of the first embodiment, FIG. 2 is a diagram showing a memory map of the processing program stored in the program ROM, and FIG. 3 is a diagram showing the memory map of the processing program stored in the working RAM. FIG. 4A is a flowchart showing the processing procedure of this embodiment; FIG. 4B is a flowchart showing the processing system setting routine of step S3; FIG. 5 is a diagram showing the hardware of the image processing device of the second embodiment. FIG. 6 is a flowchart showing the procedure for determining a processing system in the second embodiment. FIG. 7 is a block diagram showing the hardware configuration of a conventional image processing apparatus. In the figure, l... input section, 3... page memory, 4...
・Font memory, 5...CPU, 6...Dot pattern memory, 7...Working RAM, 8...Program ROM, 9...FIFO memory, 10...
Image forming unit interface section, 11... Operation panel interface section, 12... Operation panel, 13... Data bus, 14... Address bus, 20... Inter-host communication interface section, 21... Processing system instruction signal input unit, 40... Inter-host communication line, 41... Processing system A
instruction signal, 42 . . . processing system B instruction signal, 43 . . . processing system C instruction signal. Figure 3 Figure 4A Figure

Claims (1)

[Scope of Claims] An image processing device having a processing system corresponding to at least two different code systems consisting of a set of organized code information, wherein one of the at least two different code systems is represented. An image processing apparatus comprising: receiving means for receiving information from the outside; and selecting means for selecting a processing system that processes a code system corresponding to the information from the at least two different code systems.