JPH0437917A - Information processor - Google Patents

Abstract

PURPOSE:To attain the active insertion of an information processor without affecting the processing of another parts of the processor by securing an idle state of the control using a bus when a 1st connection means approaches a 2nd connection means up to a prescribed position for connection secured between a circuit part and the bus and then releasing the idle state of the control when the end of said connection is detected. CONSTITUTION:A 1st connection means 4 of a circuit part 3 is put close to a 2nd connection means 5 for connection secured between both means 4 and 5 at a prescribed position. Thus an approach detection means 7 detects the movement of the means 4 to the means 5. Then an idle control means 8 is started to set at least the control using a bus 2 in an idle state among those processing operations of an information processing control means 1. The circuit 3 is put closer to the means 5, and the connection between both means 4 and 5 is finished. This state is detected by a connection end detection means 6. Then an idle state release means 9 is started to release the idle state of the control. Thus the active insertion is attained for an information processor without affecting the processing of another parts of the processor.

Description

[Detailed Description of the Invention] (Summary) To enable active insertion of an information processing device including a plurality of insertable/removable circuit portions without affecting the processing of other portions of the device. and a removable circuit portion having an information processing control means, a bus connected to the information processing control means, a first connection means, and a first connection means for connecting the circuit portion to the bus. In the information processing apparatus, the information processing apparatus includes a second connection means that can be connected to the first connection means, and a connection completion detection means for detecting that the first connection means and the second connection means have completed connection; approach detection means (SW1) for detecting that the first connection means has approached the second connection means to a predetermined position before the first connection means and the second connection means are connected; and the information processing control means is configured to control, when the approach is detected, at least the control using the bus among the processing of the information processing control means to be in an idle state; The apparatus further comprises an idle state canceling means for canceling the idle state when the connection completion is detected in the idle state.

[Industrial application field]

The present invention relates to an information processing device including a plurality of removable circuit parts.

In an information processing device in which a large number of removable circuit boards (printed boards), such as interface circuits for input/output devices, are housed in corresponding slots of a shelf, when the power of the entire device is turned on, each individual circuit There is a request for active insertion to insert the board.

By the way, when inserting a circuit board during active insertion, it is required to prevent the processing of other parts of the device from being affected.
U needs to be aware of which circuit board is installed or not.

[Prior art and problems to be solved by the invention] Part 8
The figure shows an example of connections between a CPU and a plurality of printed boards in an information processing device.

In FIG. 8, 120 is a CPU, 121, 122, and 123 are printed boards, and 10 is a CPU 1.
20 and a plurality of printed boards 121°122, and 1
This is a bus that connects 23.

FIG. 9 shows a conventional procedure in which the CPU 120 checks whether each printed board is mounted or not mounted in an information processing apparatus having the configuration shown in FIG. Here, addresses 0200.0210 and 0220 are assigned to each printed board 121, 1221123 in FIG. 7.

First, in step 31 of FIG. 9, the address is checked, and if the address is 0200, step 0 is executed.
If the address is 0210, the process goes to step 36, and if the address is 0220, the process goes to step 40. The process then proceeds to steps 33, 37, or 41, respectively, and waits for 100 m5 until a response is received.

Individually, in each case, if there is a response, proceed to steps 35, 39 and 43, respectively, to proceed to the next process. If step 33.37 or 41
If there is no response, timeout processing is performed in step 44.

As mentioned above, in the past, the CPU accessed each printed board one by one and determined whether or not the printed board was mounted based on whether there was a response within a predetermined time. . Therefore, there was a problem in that it took time for the CPU to determine whether the device was installed or not.

Furthermore, in the past, there was a problem in that the printed circuit board could not be inserted unless the power to the device was turned off.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an information processing device in which active insertion is possible without affecting the processing of other parts of the device. It is an object of the present invention to provide an information processing device in which a CPU can quickly and reliably recognize whether a board is mounted or not.

(Means for solving problems) FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 is an information processing control means, 2 is a bus, and 3
4 is a circuit portion, 4 is a first connection means, 5 is a second connection means, 6 is a connection completion detection means, 7 is an approach detection means, 8 is an idle control means, and 9 is an idle state release means.

The information processing control means 1 controls information processing performed in the device.

The circuit part 3 is removable from the device and has first connection means 4 .

The second connecting means 5 are connected to the first connecting means 4 by inserting the circuit part 3 described above into the device.

The bus 2 connects the information processing control means 1 and the second connection means 5.

The connection completion detection means 6 detects the completion of connection between the first connection means (4) and the second connection means (5).

The approach detecting means 7 detects that the first connecting means 4 is connected to the second connecting means 5 before the first connecting means 4 and the second connecting means 5 are connected.
It is detected that the terminal approaches the connecting means 5 to a predetermined position.

The information processing control means 1 has an idle control means 8 and an idle state release means 9.

When the approach is detected, the idle control means 8 controls at least the control using the bus 2 among the processes of the information processing control means to be in an idle state.

The idle state release means releases the idle state when the connection completion is detected in the idle state.

[Effect]

According to an arrangement of the invention, the first connection means 4 of the circuit part 3
When the device approaches the second connecting means 5 to connect to the second connecting means 5 and approaches a predetermined position, it is detected by the approach detecting means 7, the idle control means 8 is activated, and at least one of the processes of the information processing control means 1 is activated. The use of the bus 2 is controlled to be in an idle state. and,
The circuit part 3 is brought closer to the second connecting means 5 and the first
When the connection between the connecting means and the second connecting means 5 is completed,
This completion is detected by the connection completion detecting means 6, and the idle state canceling means is activated, thereby canceling the idle state.

Therefore, in the information processing apparatus of the present invention, active insertion is possible without affecting the processing of other parts of the apparatus.

[Embodiment] FIG. 2 is a diagram showing the configuration of a shelf when no circuit board is mounted in an embodiment of the present invention.

In Fig. 2, 21 is a shelf, 22 is a connector, and S
Wl and SW2 are switches.

The shelf 21 is provided with slots for accommodating circuit boards. Each slot is provided with a connector 22. The circuit board is inserted from the entrance side, and the first connector of the circuit board is connected to the connector 22 of the shelf 21. The connection is completed by being connected to.

According to the present invention, a switch SWI is provided at a position in the middle of each slot of the shelf 21 where a circuit board is inserted, and a switch SW2 is provided at the innermost position of the shelf 21. When the circuit board is inserted to the switch SWl position, the switch SWI is tilted in the direction shown by the arrow in FIG. 2, and the switch is turned on. In addition, the switch SW2 has a connector at the top of the circuit board that is connected to the shelf 21.
When the connection to the connector 22 is completed, the switch is pushed to the top of the circuit board and the switch is turned on.

FIG. 3 shows a state in which a circuit board (printed board) is being inserted into the shelf 21 having the structure shown in FIG. 2. As shown in FIG. 3, when the circuit board is inserted to the switch SWI position, the switch SWI
is pressed and turns on, but at this stage, the switch SW
2 is still OFF. Note that a connector 22' connectable to the connector 22 of the shelf 21 is attached to the top of the circuit board.

FIG. 4 shows the state when a circuit board (printed board) has been inserted into the shelf 21 having the structure shown in FIG. 2.

By inserting the circuit board 23 all the way, the circuit board 23
The connector 22' of the shelf 21 and the connector 22 of the shelf 21 are completely connected. Both the switch SW1 and the switch SW2 are pressed by the circuit board 23 and turned on.

FIG. 5 shows an information processing apparatus in which the configuration shown in FIGS. 2 to 4 is provided for a plurality of slots.
This figure shows a configuration for generating an insertion notice signal and an insertion notice interrupt signal.

In FIG. 5, SW・15. ... SWIl is a switch SWI in a plurality of slots, 24 is a rise detection section for SW1, 25 is a CPU, 26 is a mounting flag register provided in the CPU, and 28 is a signal line for transmitting an insertion notice signal. be.

SWt+, --・swl,, respectively, are the switches SW shown in FIG. 2 in a plurality of (n) slots.
A switch is provided in the same manner as I, and one end of each is connected to a high potential level, and when the switch is turned on, the potential of the other end is set to a high level. The level at the other end of each of the switches SWII, ... SWl is transmitted as an insertion notice signal to the corresponding bit of the mounting flag register 26 via a dedicated insertion notice signal transmission signal line 28. At the same time, it is also applied to the SWI rise detection section 24. The level of the above-mentioned insertion notice signal is written to each corresponding pin point of the above-mentioned mounting flag register 26, and on the other hand, in the SWI rise detection section 24, at least one of the above n-bit insertion notice signals is valid. (rises), it detects this and generates the insertion notice interrupt signal lNTl, and the CP
Communicate to U25.

FIG. 6 shows an information processing apparatus in which the configuration shown in FIGS. 2 to 4 is provided for a plurality of slots.
It shows a configuration for generating an insertion completion signal and an insertion completion interrupt signal.

In FIG. 6, SW2+, . . . SW2fl are switches in a plurality of slots, and SW2127 is a rise detector for SW2, and 29 is a signal line for transmitting an insertion completion signal.

SW21, ---3W21 is the switch SW2 shown in FIG. 2 in a plurality of (n) slots, respectively.
A switch is provided in the same manner as the above, and one end of each is connected to a high potential level, and when the switch is turned on, the potential of the other end is set to a high level. each switch S
W21. ...The level of the other end of SW21 is applied as an insertion completion signal to the rising edge detection section 27 for SW2 via the insertion completion signal transmission signal line 29 provided exclusively for each. In the rising edge detection unit 27 for SW2, at least one of the above n-bit insertion completion signals is detected.
When the flag becomes valid (rises), it is detected and an insertion completion interrupt signal INT2 is generated and transmitted to the CPU 25.

FIG. 7 shows the processing procedure in the embodiment (FIGS. 2 to 6) of the present invention.

In FIG. 7, during normal access processing, in step 11, which printed board is to be accessed is determined based on the address, and in step 12, the focus of the mounting flag 26 corresponding to the circuit of the printed board at that address is determined. Check. If it is not mounted, the process jumps to step 14 and the next process is performed. If it is mounted, the circuit of the printed board is accessed in step 13, and then the process goes to step 14.

In step 15 of FIG. 7, it is determined whether the insertion notice interrupt signal lNTl has been received, and if a valid insertion notice interrupt signal lNTl has been received, in step 16, at least the step shown in FIG. Processes that use the bus 10 are placed in an idle state. The idle state continues until a valid insertion completion interrupt signal INT2 is received in step 17, and when the valid insertion completion interrupt signal INT2 is received, the idle state is canceled in step 18 and the next process starts. move on.

[Effects of the Invention] According to the information processing device of the present invention, it is possible to actively insert a circuit board without affecting the processing of other parts of the device. It becomes possible for the CPU to quickly and reliably recognize whether or not a circuit board is mounted.

[Brief explanation of the drawing]

Figure 1 is a basic configuration diagram of the present invention. Figure 2 is a diagram showing the configuration of a shelf when no circuit board is mounted in an embodiment of the present invention. Figure 3 is a diagram showing the shelf configuration as shown in Figure 2. Figure 4 shows the state when a circuit board (printed board) is being inserted into the shelf 21 configured as shown in Figure 2. The figure shown in FIG. 5 is an information processing apparatus in which the configuration shown in FIGS. 2 to 4 is provided for a plurality of slots.
FIG. 6 is a diagram showing a configuration for generating an insertion notice signal and an insertion notice interrupt signal, in an information processing apparatus in which the configurations shown in FIGS. 2 to 4 are provided for a plurality of slots. A diagram showing a configuration for generating an insertion completion signal and an insertion completion interrupt signal, FIG. 7 is a diagram showing a processing procedure in the embodiment of the present invention (FIGS. 2 to 6), and FIG. 8 is a CPU FIG. 9 is a diagram showing an example of the connection between a plurality of printed boards and a plurality of printed boards, and FIG. 9 is a diagram showing a processing procedure of a conventional printed board mounting check. [Explanation of symbols] 1.-information processing control means, 2.--bus, 3.--circuit portion, 4..-first connection means, 5..-second connection means, 6.-connection completion detection Means, 7-... Approach detection means, 8.
...Idle control means, 9--Idle state release means, 21--Shelf, 22... Connector, SWl,
SW2-...Switch, SW1+,...SW
IE...Switch SWI in multiple slots, 2
4-3 Rising detection section for W1, 25...CP
Ll, 26-mounting flag register, 28--Insertion notice signal transmission signal 1! , SW21, ...SW21
l---Switch SW2127 in multiple slots
... Rising detection section for SW2, 29-... Signal line for transmitting insertion completion signal.

Claims (1)

[Claims] 1. Information processing control means (1);
1); a removable circuit part (3) having a first connection means (4); and the circuit part (3).
in an information processing device comprising a second connection means (5) that can be connected to the first connection means (4) to connect the first connection means (2) to the bus (2); connection completion detection means (6) for detecting that the connection between the first connection means (4) and the second connection means (5) is completed; and the connection between the first connection means (4) and the second connection means (5). and an approach detection means (7) for detecting that the first connection means (4) approaches the second connection means (5) to a predetermined position, the information processing control means ( 1) is an idle control means (8) for controlling, when the approach is detected, at least the control using the bus (2) among the processes of the information processing control means (1) to be in an idle state; and an idle state canceling means (9) for canceling the idle state when the connection completion is detected in the idle state. 2. A CPU (25), a bus (10) connected to the CPU (25), a removable circuit section (23), and a circuit section (23) for connecting the circuit section (23) to the bus (10). An information processing device comprising a shelf (21) having a slot (22) for accommodating the circuit portion (3), wherein the shelf (21) accommodates the circuit portion (23) in the slot (22). a first switch (SW1) that is provided at a predetermined position of a path to be inserted in order to connect to the circuit part (23) and turns on when detecting the presence of the circuit part (23) at the predetermined position; ) has a second switch (SW2) provided so as to be turned ON when the connection to the slot (22) is completed, and the first switch (SW
1) generates a first interrupt signal in response to turning on of
interrupt signal generating means (24); and second interrupt signal generating means (24) that generates a second interrupt signal in response to turning on of the second switch (SW1).
7), and upon receiving the first interrupt signal, the CPU (25
), at least the control using the bus (10) is performed by an idle control means (16) that controls the bus (10) to be in an idle state;
An information processing device comprising: idle state canceling means (18) for canceling the idle state when receiving an interrupt signal. 3. A CPU (25), a bus (10) connected to the CPU (25), and a plurality of removable circuit parts (23);
Each of the plurality of circuit parts (23) is connected to the bus (10).
An information processing device comprising: a shelf (21) having a plurality of slots (22) each accommodating the circuit portion (23) for connection to the plurality of circuits; The corresponding circuit portions (23) are provided at predetermined positions in the respective paths into which the portions (23) are inserted for connection to the respective corresponding slots (22);
A plurality of first switches (SW1_1, . . . SW1_
n) and a plurality of second switches (SW 2
_1, ... SW2_n), and generates a first interrupt signal in response to turning on of at least one of the plurality of first switches (SW1_1, ... SW1_n). (24) and the plurality of second switches (SW2_1,...SW2
a second interrupt signal generating means (27) that generates a second interrupt signal in response to turning ON of at least one of the CPU (25);
), at least the control using the bus (10) is performed by an idle control means (16) that controls the bus (10) to be in an idle state;
An information processing device comprising: idle state canceling means (18) for canceling the idle state when receiving an interrupt signal. 4. Further, mounting flag means (26) having a plurality of bits provided corresponding to the plurality of circuit parts (3) is provided, and each bit of the mounting flag means (26) corresponds to the plurality of circuit parts (3). 4. The information processing apparatus according to claim 3, wherein the information processing apparatus is set when a corresponding one of the switches (SW1_1, . . . SW1_n) is turned on.