JPH04373168A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce etching residue and increase electrode area, by a method wherein, after an insulating film having triangular protruding parts are formed on a gate electrode on a silicon substrate, a contact hole is formed, and an electrode is formed on the contact hole and the insulating film. CONSTITUTION:While O2 and Ar are made to flow in a plasma chamber, and SiH4 is made to flow in a wafer chamber, plasma is drawn in a shower state from the plasma chamber to a wafer chamber, SiO2 is deposited by applying an RF bias to a wafer holder, and Ar sputtering is performed. Thereby triangular protruding parts 4 whose inclination angles are about 45 deg. are formed. After a contact hole 5 is formed by photo etching process, a capacitor electrode 6 is formed bar a sputtering method. Thereby etching residue is reduced and the area of the electrode 6 can be increased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device having a three-dimensionally structured capacitor electrode.

0002

[Prior art] Dynamic random access memory (
DRAM) stores data by storing charge in a capacitor. The above capacitor has a certain value (several 1
A capacitance of 0 fF or more is required, and as semiconductor devices become smaller, the capacitor area becomes insufficient if the capacitor electrode has a two-dimensional structure. Therefore, methods for forming capacitor electrodes having a three-dimensional structure are currently being proposed.

FIG. 2 shows a process using a local planarization method (LOPLAD), and the manufacturing process will be explained. First, a transistor section is formed on a silicon substrate 1, and a gate electrode 2 is formed on the silicon substrate 1.
After forming, a polysilicon film 7 is deposited by CVD method. Next, the polysilicon film is processed into a desired shape using a photo-etching process (FIG. 2(a)). Next, CVD
A silicon oxide film 8 is deposited by a method, and is processed into a desired shape by a photo-etching process. After that, by an etching process, as shown in FIG. 2(b),
Polysilicon film 7 is hollowed out to form protrusions 8a of silicon oxide film 8, and then capacitor electrode 6 is formed by sputtering (FIG. 2(c)).

By using the above process, the capacitor electrode 6 has a three-dimensional structure due to the protrusions of the silicon oxide film 8, and the electrode area can be increased.

[0005]

Problems to be Solved by the Invention In capacitor electrodes having a rectangular cross section due to the above process, etching residues are likely to be left. Also, if a vertical step is formed, the subsequent C
When the insulating film grown by the VD method becomes an overhang, etched residue of the electrode material is left in the shadowed portion, which may cause a short circuit between the electrodes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor memory device that reduces etching residue and increases electrode area.

[0007]

Means for Solving the Problems In the method of manufacturing a semiconductor memory device according to the present invention as set forth in claim 1, after forming a gate electrode on a silicon substrate, a triangular protrusion is formed on the gate electrode using a bias ECRCVD method. and, after the step, forming a contact hole and depositing an electrode material on the contact hole portion and the insulating film to form an electrode. .

A method for manufacturing a semiconductor memory device according to a second aspect of the present invention is characterized in that a bias sputtering method is used in place of the bias ECRCVD method in the method for manufacturing a semiconductor memory device according to the first aspect. .

[0009]

[Operation] By using the present invention as set forth in claims 1 and 2 above, the inclination angle of the protrusion of the capacitor electrode is approximately 45°.
Therefore, in subsequent processing steps, overhang does not occur, etching residue is reduced, and the area of the capacitor electrode portion is increased, resulting in an increase in capacitance.

0010

EXAMPLES The present invention will be explained in detail below based on examples.

FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention according to claims 1 and 2.

Reference numeral 1 indicates a silicon substrate, 2 a gate electrode, 3 a silicon oxide film, 4 a triangular protrusion, 5 a contact hole, and 6 a capacitor electrode.

Next, a manufacturing process of an embodiment of the present invention as defined in claim 1 will be described. First, a gate electrode 2 is formed on a silicon substrate 1 using a conventional technique (FIG. 1(a)).
. Next, by bias ECRCVD method ("ECR" is an abbreviation for "electro cyclotron resonance" and indicates "electron cyclotron resonance"), a triangular protrusion 4 having a cross section with an inclination angle of about 45 degrees is formed on the wiring. A silicon oxide film 3 is deposited (FIG. 1(b)). Figure 3 shows the bias E
A schematic diagram of an apparatus used in the CRCVD method is shown. 9 is a plasma chamber, 10 is a wafer chamber, 11 is a waveguide, 12 is a coil, 13 is a wafer, 14 is a wafer holder, and 15 is a gas introduction tube. Actually, while O2 and Ar are flowing into the plasma chamber 9 through the gas introduction pipe 15, and SiH4 is flowing into the wafer chamber 10 through the gas introduction pipe 15.
Plasma is showered from plasma chamber 9 to wafer chamber 1.
By applying an RF bias to the wafer holder 14, SiO2 is deposited and at the same time Ar
Triangular protrusions 4 are formed by sputtering. As the above forming conditions, the pressure is 10-3 to 10-4
Torr, microwave is 2.45 GHz, magnetic flux density is 875 Gaus, and RF is 13.56 MHz. Next, by a photo-etching process using conventional technology,
After forming the contact hole 5 (FIG. 1(c)), a capacitor electrode 6 is formed by sputtering (FIG. 1(d)).
).

Next, a manufacturing process of an embodiment of the present invention as defined in claim 2 will be described. First, a gate electrode 2 is formed on a silicon substrate 1 using a conventional technique (FIG. 1(a)).
. Next, a silicon oxide film 3, which becomes a triangular protrusion 4 having a cross section with an inclination angle of about 45°, is deposited on the wiring by bias sputtering (FIG. 1(b)). The bias sputtering method is a method in which an RF bias is added to the normal sputtering method, and quartz is used as a target to form a silicon oxide film.
Sputtering is used to physically attach SiO2. After the above steps, a contact hole 5 is formed by a photo-etching process using a conventional technique (FIG. 1(c)), and then a capacitor electrode 6 is formed by a sputtering method (FIG. 1(d)). Each cross-sectional view of the manufacturing process has the same shape as when using the bias ECRCVD method shown in FIG.

[0015]

As described above in detail, by using the present invention as claimed in claims 1 and 2, the area of the capacitor can be increased by providing a protrusion with a triangular cross section on the gate electrode. Also, the slope is approximately 45°.
Since it has a slope of , etching residue can be suppressed.

Furthermore, in order to further increase the capacitor area, even if a raised material is placed on top of the gate electrode to further increase the step, the groove can be filled in, and the area can be increased at the protrusion. , it becomes possible to obtain a DRAM with even higher integration.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of the present invention according to claims 1 and 2.

FIG. 2 is a manufacturing process diagram of the prior art.

FIG. 3 is a conceptual diagram of an apparatus used in a bias ECRCVD method.

[Explanation of symbols]

1 Silicon 2 Gate electrode 3 Silicon oxide film 4 Triangular protrusion 5 Contact hole 6 Capacitor electrode 9 Plasma chamber 10 Wafer room 12 Coil 13 Wafer 14 Wafer holder 15 Gas introduction pipe

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor memory device having a capacitor electrode having a three-dimensional structure, after forming a gate electrode on a silicon substrate, a bias ECRCVD method is used to form a triangular protrusion on the gate electrode. A semiconductor memory comprising a step of forming an insulating film, and a step of forming a contact hole after the step and depositing an electrode material on the contact hole portion and the insulating film to form an electrode. Method of manufacturing the device. 2. In a method of manufacturing a semiconductor memory device having a capacitor electrode having a three-dimensional structure, after forming a gate electrode on a silicon substrate, using a bias sputtering method,
A step of forming an insulating film having a triangular protrusion on the gate electrode, and after this step, forming a contact hole and depositing an electrode material on the contact hole portion and the insulating film to form an electrode. characterized by having
A method for manufacturing a semiconductor memory device.