JPH0437312A - High functional pld - Google Patents

Abstract

PURPOSE:To offer an electronic circuit element being a high speed logic arithmetic circuit whose arithmetic operation is freely designated, and having a storage function by forming a PLD and a RAM on a same Si substrate. CONSTITUTION:A PLD applies a desired processing such as OR, AND or NOT to a signal inputted from an external input terminal, and produces a resulting signal to an output terminal. A RAM section 2 is manufactured on the same Si substrate. Part of outputs of the PLD are outputs X1, X2,...XM. Part of outputs of the PLD are connected to the RAM 2 through internal wires x1, x2,...xM. An output of the RAM 2 is connected to part of inputs of the PLD through internal wires y1, y2,...yM. Since the signal is delivered through the internal wires, the delay in the signal is less and the area of the wires for the signal delivery is less.

Description

[Detailed description of the invention] [Industrial application field]

This invention relates to improvements in the internal structure of PLDs.

[Conventional technology] PLD is Pr
This is an abbreviation for ogrammable log devlce, and it is a digital IC that allows the user to freely specify the contents of logical operations. Made with 81 semiconductors. For example, a large number of multi-input NAND or NOR circuit elements are formed vertically and horizontally on a chip, and there are a plurality of inputs and outputs. An arbitrary combination of input values and their negated values is applied to a multi-input NAND circuit and a multi-input NOR circuit, and the results of the NAND and NOR operations appear at the output. There is also a combination of multiple input AND and one multiple input OR circuits. The connection state between the input line and these logic operation circuits can be specified arbitrarily. In the case of bipolar PLD, the connection part is a fuse or PLD.
It is an N junction. Apply a large current or voltage to the parts where you do not want to connect, blowing the fuse or destroying the PN junction. In the case of a CMOS PLD, this is done by applying a voltage between the gate and source and injecting electrons into the floating gate. The degree of freedom in design is greater than that of standard logic ICs. Moreover, since it is standardized as an IC, it is easy to obtain and inexpensive. Since it only performs logical operations, high-speed processing is possible. Arithmetic operations performed by a computer can be performed using software, but the speed is slow and is not as fast as that performed by logical operation elements. There are TTL and CMOS level ones. RAM is also made of Sl semiconductor chips. A memory element that has an address, data input, and data output. Each element is a combination of two inverters. There are static RAM and dynamic RAM. Static RAM also includes NHO2RAM and NC.
There are MOS RAM, CMOS RAM, etc. These flip-flops are made by combining several FETs that differ mainly in their individual element parts. The same elements are lined up vertically and horizontally, and control lines and data lines are provided vertically and horizontally. These do not require capacitors. Refreshing is not required, but the degree of integration is inferior. A dynamic RAM is a single element made up of a combination of a capacitor and a switching transistor, and requires an IJ' 7 L/shocker to replenish the discharge of the capacitor. It is the same as static RAM that control lines and data lines are arranged vertically and horizontally. Both PLD and RAM are commercially available and are used for their respective purposes. RAM is often used as a storage element in computers. Since addresses are specified, data is input, and data is output, the existence of computer control is a prerequisite. On the other hand, since PLDs are elements that perform high-speed logic operations, they can be considered to be on the same level as standard logic operation ICs. It is used in the pre-processing stage of computer processing, such as preliminary processing of sensor signals, or in cases where relatively simple but high-speed processing that does not involve a computer is desired. Although computer processing is highly versatile and has a high degree of freedom, it has the disadvantage that it is slow because it runs through a program. In this way, RAM and PLD are generally used in different places. Some PLDs have memory functions as well as sequential logical operations. This is to temporarily hold the logic operation output in a data flip-flop and feed it back to the logic operation input. This allows the influence of data from one or several clocks ago to remain. A collection of data flip-flops is called a register, and some PLDs include registers in addition to a logic operation section. As already mentioned, in the logical operation section, elements such as multi-input NOR, NAND, AND, NOT, and OR are formed vertically and horizontally, but these alone cannot store data temporally. . If there is a register after the logic operation section, part of the output can be fed back, so even complex counters can be designed freely. There are also devices on the market that have a register consisting of a data flip-flop at the stage subsequent to the logic element. In such a case, of course, the register section and the logic operation section are manufactured on the same 81 chip. Together, these constitute a single IC.

[Problem to be solved by the invention]

It seems that in the past, PLDs and RAMs were rarely used in parallel. Therefore, when a PLD is used by connecting it to a RAM, it has to be done by attaching a commercially available PLD and RAM to a printed circuit board on which wiring is drawn. This allows a high degree of freedom in design, but there is a delay in the signal since the signal flows through the wiring pattern on the printed circuit board. This is a problem that cannot be ignored if you want to build a high-speed system. In order to reduce signal delay, wiring patterns must be made as short as possible. The delay within the IC and the delay in the printed circuit board wiring are added together, resulting in a considerable delay. As explained earlier, there are already PLDs that have a built-in register consisting of a logic operation section and a data flip-flop. This returns the output of the data flip-flop to the input of the logic operation section. It can be connected to any input. However, since there is no interaction between two or more data flip-flops included in a register, it is not possible to store data separated by two or more clocks, and it is not possible to perform logical operations between data separated by two or more clocks. Another inconvenience is that calculations cannot be made between the stored data. Products such as gate arrays with built-in RAM are also available. However, in the case of gate arrays, there are drawbacks such as the high cost of development and the long development period. It is an object of the present invention to provide an electronic circuit element which is a high-speed logic operation circuit, allows operations to be freely specified, and has a memory function.

[Means to solve the problem]

The PLD of the present invention includes a RAM having a large number of memory cells arranged vertically and horizontally including transistors and capacitors, a control line and a data line connecting the memory cells vertically and horizontally, and having address input and data input/output, and a plurality of inputs. It has a sum operation circuit, a product operation circuit, a NOT circuit, a NOR circuit, a NAND circuit, an exclusive OR circuit, etc., and many of the same circuit elements are combined. A PL that allows you to arbitrarily specify the relationship between these multiple input values and output values by determining the input wiring state.
D is formed on the same semiconductor chip, and part of the output of the PLD is connected to the address input and data input of the RAM by wiring on the chip, and the output of the RAM is connected to part of the input of the PLD by wiring on the chip. characterized by being connected

[For works]

PLD and RAM are formed on the same 51 substrate. This means that the logic operation section and the highly flexible memory element are integrated on one chip. Since it includes a PLD, it also includes a RAM that can specify any logical operation, so it can also hold input data at any time. Therefore, the functionality of the PLD can be further improved. Looking at this electronic circuit element from the RAM side, it is sometimes desirable to perform logical operations on data before inputting it into the RAM, and in this case, the PLD can perform any preliminary calculations, thereby increasing the functionality of the RAM. Furthermore, since the RAM and PLD are fabricated on the same SI chip and signals are transmitted through short wiring patterns on the chip, there is little signal delay. Furthermore, since the wiring patterns are in the same plane, they can be made into microstrip lines, and distortion can be reduced even with high-speed signals. It is suitable as an element that performs high-speed calculations.

【 Example 】

FIG. 1 is a block diagram of the internal configuration of a PLD according to an embodiment of the present invention. The part surrounded by the wavy line is the high-performance PL of the present invention.
It is D. AND/OR 714 part 1 is a part corresponding to PLD. This is an area in which a large number of multi-input AND elements and multi-input OR elements are formed vertically and horizontally. It has external input terminals YI, YE, and Ym. The PLD performs desired processing such as logical sum, logical product, and negation on signals inputted from an external input, and generates a signal at an output terminal. The RAM section 2 is also manufactured on the same 51 board. R
AM2 has address input, data input, and data output. These points are the same as conventional RAMs. A part of the PLD output is external output XIN X2,...x
It becomes M. A part of the PLD output is connected to the internal wiring XIN X2
・Connected to RAM section 2 by III.Xs. The outputs of the RAM section 2 are also connected to some inputs of the PLD via internal wirings y1, y2, ee and y9. Signals are transmitted through internal wiring, so there is little signal delay (
Furthermore, the area of wiring for signals becomes smaller. Here, the PLD section is an 0R-AND array, but the NANDl
Of course, the circuit may be constructed using NOR. [Effects of the Invention] The RAM, which is a storage element, and the PLD, which is a logic operation element, are formed on the same Sl substrate chip. Therefore, the wiring connecting the two is shortened, and signal delay is reduced. Suitable for high-speed signal processing, with little signal attenuation or distortion even at high speeds. Furthermore, compared to a case in which individual PLDs and RAMs are mounted on a printed circuit board, the size can be reduced because there are fewer packages and wiring. Looking at this from the PLD, it is a RAM that can hold data in the output.
Since they are connected, it is possible to perform calculations on data separated in time. In other words, it can be considered that the functionality of the PLD is improved. Looking at this from the perspective of RAM, it is possible to integrate the RAM and its surrounding logic circuits into one chip, increasing the functionality of the RAM. RAM is often activated only by instructions from a computer, but since it can be pre-processed by a PLD, it can also be used as an independent element, such as an element for directly storing signals from sensors etc. that are generated over time. Become.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the internal configuration of a high-performance PLD according to an embodiment of the present invention. 1- ・ ・ 2 ・ ・ ・ Y□, Y2, X,, X2, XIN・ °“−°°” xN ・ °゛°“−yn ・ Single-handed e output/internal wiring e internal wiring

Claims (1)

[Claims] A RAM including a large number of memory cells arranged vertically and horizontally including transistors and capacitors, a control line and a data line connecting the memory cells vertically and horizontally, and having address input and data input/output, and a plurality of inputs and outputs. A large number of identical circuit elements are combined, such as sum operation circuits, product operation circuits, NOT circuits, NOR circuits, NAND circuits, exclusive OR circuits, etc., and determines the connection state of the product, sum, and NON operation elements and inputs. A PLD that allows the relationship between these multiple input values and output values to be specified arbitrarily.
are formed on the same semiconductor chip, and a part of the output of the PLD is connected to the address input of the RAM by wiring on the chip.
A high-performance PLD characterized in that it is connected to a data input, and the output of a RAM is connected to a part of the input of the PLD by wiring on the chip.