JPH04372594A - Rotational speed and torque control circuit for dc motor - Google Patents

Abstract

PURPOSE:To control the rotational speed of DC motor without increasing the load of CPU by a constitution wherein the CPU once sets a phase difference in a specific counter, hereafter a hardware circuit creates a phase signal. CONSTITUTION:A central processing unit(CPU) previously sets a phase difference, in the form of complement of 1, in a third counter 5. Hereafter, a phase generating circuit 70 creates a second phase signal 2' having desired phase difference. Consequently, rotational speed and torque of a DC motor 1 are controlled with no intervention of the CPU. According to the invention, a low speed CPU can deal with a DC motor 1 having high rotational speed resulting in suppression of cost increase.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for configuring a control circuit for controlling the rotational speed and torque of a DC motor by changing the timing of signals applied to the field of the DC motor.

[0002] In recent years, with the trend toward miniaturization of computer systems, the disk devices used in DC motors, for example, have become smaller and lighter, and the circuits that control the DC motors have become smaller and lighter. Progress is being made, but even with such miniaturization and weight reduction, improvements in torque and reduction in power consumption during steady operation are required.

[0003] In this case, it is necessary to make the circuit for controlling the DC motor as small and lightweight as possible at low cost.

0004

2. Description of the Related Art FIG. 4 is a diagram showing the driving principle of a DC motor, and FIG. 5 is a diagram illustrating a conventional control circuit for a DC motor, in which (a) shows an example of the configuration, and (b) ) is the first phase signal ■ and the input signal to the rectifier circuit {second
FIG. 6 shows an operation time chart of a conventional DC motor.

A general drive circuit for the DC motor (M) 1 takes the form shown in FIG. That is, a DC motor (M
) In order to rotate the rotor of 1, for example, when the DC motor (M) 1 is a three-phase motor, current is passed in the direction of A → B → D to the field coil shown in the figure. After that, A→B→C, D→B→C, D→B→A, C→B→
A, C→B→D, and then repeat the flow in the direction of A→B→D.

In order to control the current direction as described above, when flowing from A to B to D, the drive circuit shown in this figure is used.
8, a switch (field effect transistor, etc.)
Turn on LA1 and LC2. Thereafter, the DC motor rotates by controlling the "on" order of the switches so that current flows in the above direction.

The signals for controlling the switches LA1 and LC2 are decoded from the phase signal of the DC motor, in fact, the second phase signal ■, which will be described later, to create the switches LA1, LA2, ~LC1, LC2 shown in the figure. 6
Figure 5 (
This is the rectifier circuit 7 shown in a).

Normally, the DC motor (M) 1 has the above-mentioned rotor and a stator (not shown), and the magnetic field of the stator is detected by, for example, a Hall element provided on the rotor. A signal that determines the timing of applying current to the field coil (this is the first phase signal
If a current is passed through the field coil in accordance with the first phase signal (2) outputted by the DC motor (M) 1 , the input power can be used most efficiently.

However, in the DC motor, when a rotor having a field coil rotates in a magnetic field generated by a stator,
It functions as a generator, and a back electromotive force is generated in the field coil, and the number of revolutions can only be obtained according to the voltage difference from the input field voltage. When it is desired to increase the rotation speed, the phase of the input second phase signal (2) is slightly shifted.

FIG. 5 is a diagram illustrating a conventional DC motor control circuit, in which (a) shows an example of the configuration, and (b) shows the above first phase signal ■ and the input signal to the rectifier circuit {the above first 2 shows the relationship with phase signal {}}.

The front edge of the first phase signal ■ outputted by the DC motor (M) 1 is detected by the front edge detection section 2 of the period measurement circuit (period measurement) 2, 3, and 4.
Each time it is detected, the period measured by the first counter 3 is latched by a latch circuit (not shown), and is notified to the central processing unit (CPU) 10, for example, by an interrupt. Also, at this time, the first counter 3 of the period measurement circuits (period measurement) 2, 3, and 4 is cleared to measure the next period.

[0012] The central processing unit (CPU) 10 calculates a phase difference with respect to the current rotational speed based on the period data of the first phase signal (2) measured above, and calculates a second phase difference to which the calculated phase difference is added. A phase signal {indicated by phases A' to C' in the time chart of FIG. 6} is generated and input to the rectifier circuit 7, and the aforementioned switches LA1, LA2,
A signal for controlling ~LC1, LC2 is generated and inputted to the aforementioned drive circuit (in this figure, the drive circuit, hereinafter referred to as the drive circuit) 8.

The first phase signal ■ (phases A to C) output from this DC motor (M) 1 and the second phase signal ■ (phases A' to C') input to the rectifier circuit 7. and the decode signal of the rectifier circuit 7 (
For convenience, LA1, LA
2, ~LC1, LC2) is shown in the time chart shown in FIG. 6.

Normally, the period of phase A of the first phase signal (2) of the DC motor (M) 1 is measured to generate the second phase signal (1) (phases A' to C').

[0015]

[Problem to be Solved by the Invention] In the control circuit for controlling the rotation speed of the conventional DC motor (M) 1 described above, 1
Every time the cycle measurement is completed, the central processing unit (CPU) 10
Each time an interrupt occurs, the central processing unit (CPU) 10 interrupts other processing, and in the interrupt processing, the DC motor (
M) 1 rotation control (referred to as local processing).

Normally, when the central processing unit (CPU) 10 synchronously controls a plurality of disk devices, the so-called master disk device among the plurality of disk devices is controlled. Based on the generated master pulse, spindle sync processing is performed to synchronize the rotations of the plurality of disk devices, and the pulse width of the second phase signal is modulated to adjust the rotation speed. So-called PW
It performs M processing, command processing from a host device (main device), etc.

In the central processing unit (CPU) 10, it is an absolute condition to control the DC motor (M) 1 to be controlled and rotate it at a constant rotation speed, but during the spindle sink process, When the rotation control by the above-mentioned interrupt is input, the synchronization process after the input of the master pulse is delayed at least during the rotation control period of the DC motor (M) 1, so the spindle sync process A problem arises in that the accuracy of is limited.

For example, the above interrupt processing takes 0.3 m
s, the above spindle sync processing takes 1.5 ms,
0.6 ms for the above PWM processing, total 2.4 ms
If necessary, for a DC motor (M) 1 with a rotation speed of 4000 rpm, 3 phases, and 8 poles, 3.75 m
3.75-2.4 because the above interrupt occurs every s
= 1.35 ms, it is necessary to perform other processing, such as normal data processing, but disk devices tend to rotate at higher speeds year by year, and for example, the rotation speed is 5000 ms.
rpm, the time allowed for the other processes mentioned above is 0.6 ms, which poses a problem in that the functions of the disk device are impaired.

Of course, this problem can be solved by improving the processing speed of the central processing unit (CPU) 10, but changing from the current 8-bit machine to a 16-bit machine would be extremely expensive. However, there was a problem in that the cost was reduced and the economic efficiency was impaired.

In view of the above-mentioned drawbacks of the conventional art, the present invention provides a simple configuration of a control circuit that controls the rotational speed by changing the timing signal (first phase signal) (1) output from the DC motor (M). The purpose of this invention is to provide a control circuit that can control the rotational speed of a DC motor (M) without increasing the burden on the central processing unit (CPU).

[0021]

[Means for Solving the Problems] FIG. 1 is a diagram showing the basic configuration of the present invention. The above problem can be solved by a control circuit for controlling the rotation speed of the DC motor (M) configured as follows.

By applying a field current generated based on a phase-shifted second phase signal ■ in synchronization with the first phase signal ■ outputted by the DC motor (M) 1, the DC motor (M) M) A control circuit for controlling the rotation speed of the first phase signal 3, which measures the period of the first phase signal 3, and a first counter 3 that measures the period of the first phase signal 3,
A circuit that generates a second phase signal ■ that is synchronized with the first phase signal ■ and has a specific phase shift; A rectifier circuit 7 that determines the direction in which the field current flows, divides the measured period by 2n, and divides the measured period by 2n.
Latch counting units 41 and 42 that output the divided signal ■, a third counter 5 that outputs the above phase difference in units of 1/2n cycles, and triggered by the output timing signal ■ from the third counter 5. , a fourth counter 6 for counting the 2n divided signal ■ and generating a clock signal ■ for generating a phase-shifted second phase signal ■ in synchronization with the first phase signal ■. So, the above 1st
The phase signal ■ is input to the first counter 3, the period of the first phase signal ■ is measured, and the measured period data is input to the latch count sections 41 and 42 to obtain a 2n divided signal. The generated 2n divided signal ■ is sent to the third counter set to a specific value.
5 to obtain the timing signal ■ corresponding to the predetermined specific value and having a phase difference in units of 1/2n cycles, and the obtained timing signal ■
Based on this, the fourth counter 6 is energized to output a clock signal (2) for generating the second phase signal (2).

[0023]

[Operation] That is, in the control circuit for the rotation speed of the DC motor (M) of the present invention, the period of the first phase signal (■) output from the DC motor (M) is set in the conventional format. From the time when the front edge of, for example, phase A of the first phase signal (2) is detected, the first counter measures the signal at a specific clock.

The measured period data is divided in accordance with the phase difference of the required precision and is loaded into the n-bit second counter. Specifically, if the first counter is, for example, a 16-bit counter, after the upper 8 bits of the output of the first counter are latched into a latch circuit, the upper 8 bits are
By loading the second 8-bit counter (specifically, taking the one's complement and loading it) and running the second 8-bit counter with the same clock as the first counter. , 1 of the above first phase signal ■
A divided signal (2) obtained by dividing the period by 28=256 can be obtained as a carry signal. The above can also be done by latching 16 bits into a latch circuit and shifting 8 bits to divide into 28.

The accuracy of the divided signal (2) can be determined by the value of n. When n is increased, a finely divided signal (2) can be obtained. This divided signal ■ is given in advance as
A second value set to the one's complement of a specific value, for example
By counting with the counter, it is possible to obtain the "deviation timing signal" ■ by the set 1's complement x divided signal ■ as a carry signal, and use this as the phase difference given to the DC motor (M). .

In this way, the cycle data of the first phase signal (2) is input to the n-bit second counter, for example.
After shifting and setting its 1's complement, the 2n-divided divided signal (carry signal) obtained from the second counter is counted by a third counter set to the 1's complement of a specific value. By doing so, the phase difference of the complement in units of 1/2n periods, for example, in the case of an up counter,
{360 degrees x 1/2n x (counter full value - complement)} can be obtained.

Therefore, in the control circuit of the present invention, for example,
The central processing unit (CPU) simply sets the one's complement of the specific value in the third counter in advance.
The phase difference for the complement can be obtained with an accuracy of /2n.

After that, using the carry signal (■) of the third counter that specifies the phase difference as a trigger, a fourth clock (■) for generating the divided signal (■) and the second phase signal (■) is generated. By inputting it into the counter and dividing it, the first
With respect to the phase signal ■, it is possible to obtain a clock ■ that generates a second phase signal ■ having the above-mentioned phase difference.

When the DC motor (M) is a three-phase motor, the second phase signal ■ has a deviation of 60 degrees (1/6 of 360 degrees), as shown in FIG. Since it has a timing, the second phase signal ■ is
The second phase signal ■ is generated by using a clock signal ■ obtained by dividing one cycle of the first phase signal ■ by 28=256, for example, by dividing the frequency of the divided signal ■ by 256/6≒42. Can be done.

[0030] Thus, in the present invention, for example,
The central processing unit (CPU) inputs the above third counter,
By simply setting the phase difference once in one's complement format, the second phase signal ■ can be generated by the hardware circuit, so the central processing unit (CPU) can:
The DC motor (M) without the need for any intervention
The rotation speed and torque can be controlled. Therefore, even if the rotation speed of the DC motor (M) is high, it can be handled by a low-speed central processing unit (CPU).
This has the effect of suppressing cost increases.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below in detail with reference to the drawings. The above-mentioned FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart of the present invention.

In the present invention, a DC motor (M) 1
The switches LA1, LA2, ~, LC1, L are activated by a rectified signal generated by decoding the phase-shifted second phase signal ■ in synchronization with the first phase signal ■ output by the
A first control circuit that measures the period of the first phase signal ■ serves as a control circuit that controls the rotation speed of the DC motor (M) 1 by controlling C2 and determining the direction of the current flowing through the field. 3 and a second phase signal ■ which is synchronized with the first phase signal ■ and has a specific phase shift based on the measured period, and inputs the field to be input to the field. and a rectifier circuit 7 that determines the direction of the magnetic current, and divides the measured period into 2n, and divides the measured period into 2n.
Latch counting units 41 and 42 that output divided signals ■, and a third counter that counts the 2n divided signals ■ from the latch counting units 41 and 42 and outputs the phase difference in units of 1/2n periods. 5 and the third counter
Clock signal ■ for counting the 2n divided signal ■ and generating a phase-shifted second phase signal ■ in synchronization with the first phase signal ■, triggered by the output timing signal ■ from 5. The means provided with the fourth counter 6 that generates is the means necessary to implement the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The configuration and operation of the control circuit for controlling the rotational speed and torque of the DC motor (M) 1 of the present invention will be explained below with reference to FIG. 1 and FIGS. 2 and 3. In this embodiment, for example, a 3-phase 8-pole DC motor (M)
1, the rotation speed is 4000 rpm (therefore, the period is about 15000 μs), and the amount of phase shift is set to 1.
An example of control in steps of /256=1.4 degrees will be explained. Also, all counters that do not have a clock listed are 1.
Assume that it is clocked at μs.

First, in FIG. 2, the front edge detection section 2 detects the front edge of the phase A signal of the first phase signal (2), and at that timing, the first counter (for example, 16 bit counter)
Load the cycle data of the phase A measured in step 3 into the latch circuit 41, clear the first counter 3 at a timing shifted by 1 μs, and start measuring the cycle of the next phase A. do.

Next, for example, the 1's complement of the upper 8 bits of the periodic data of phase A latched by the latch circuit 41 is taken and loaded into the second counter 42 (load 1). When this second counter 42 is configured with 16 bits, the upper 8 bits contain all "1"s.
Set.

[0036] The second counter 42 is
When operated with a clock, the first counter 3 above becomes 2
8=256 The divided signal ■ is output as a carry. Each time the carry is output, the latch circuit
By repeating the process of taking the 1's complement of the upper 8 bits of the data latched in 41 and loading it into the second counter 42 (Load 1), a divided signal (■) obtained by dividing the period of the phase A by 256 is obtained. 256 pulses are output. {Refer to the operation time chart in Figure 3} This divided signal ■ is the phase signal of the DC motor (M) 1 (
This is a signal obtained by dividing one period of the first phase signal (2) into 256 equal parts.

The third counter 5 is a counter clocked by the above-mentioned divided signal
PU) 10, in order to set the phase difference in advance, by setting the 1's complement of a specific value m, the set "specific It is possible to obtain a signal (load 2) (2) at timing T after a time difference of "value m x 1/256 cycles". This time difference is taken as the phase difference of the second phase signal (■) with respect to the first phase signal (2), and at the timing T, the fourth counter 6 is energized and the divided signal (2) is set as a clock to convert the divided signal (2). For example, by dividing the frequency by 42, it is possible to obtain the clock {circle around (2)} shown in the operation time chart of FIG. Also, at the above timing T, the phase generation circuit 70 is forcibly set.

By inputting the clock ■ to the phase generation circuit 70 shown in FIG. 1, the second phase signal ■ (phases A' to C') shown in FIG. 3 can be generated. .

By inputting the second phase signal (1) (phases A' to C') thus obtained to the rectifier circuit 7, the six types of decoded signals (switches LA1, By supplying this decoded signal to the drive circuit 8, the DC motor (M) 1 can be rotated at a desired rotation speed. become.

In the above embodiment, in order to obtain the desired phase difference, the central processing unit (CPU) 10 generates a phase difference of 1/2n of the period of the first phase signal (2) and m times the period of the first phase signal (2). When you want to set for the second phase signal ■, in advance,
An example was explained in which the 1's complement of m is set in the third counter 5. Therefore, in this case, as described above, the central processing unit (CPU) 10 sets the 1's complement of m. The central processing unit (CPU) 10 is not limited to the method of setting the one's complement of the value m;
It goes without saying that it may be possible to set it permanently using the hardware.

In this way, the DC motor (M
) 1 rotation speed and torque control circuit decodes the phase-shifted second phase signal ■ in synchronization with the first phase signal ■ output from the DC motor (M) (1). Switch the generated rectified signal LA1, LA2, ~,
By applying to LC1 and LC2, the DC motor (M
) A first counter 3 that measures the period of the first phase signal ■ as a control circuit for controlling the rotation speed of the first phase signal ■; a rectifier circuit 7 that receives a second phase signal (1) having a specific phase shift and generates a signal that determines the direction of the current input to the field; Latch count units 41 and 42 of n bits to be divided and the latch count units 41 and 42
A third counter 5 counts the 2n divided signal ■ from the 1/2n cycle and outputs the above phase difference in units of 1/2n period, and the output timing signal ■ from the third counter 5 triggers the 2n divided signal ■. A fourth clock signal (2) that counts the divided signal (2) and generates a clock signal (2) in synchronization with the first phase signal (2) to generate a second phase signal (2) with a phase shift.
The counter 6 is provided with a counter 6, and the divided signal
For example, by dividing the frequency by 42 with the counter 6, a clock ■ having a timing obtained by dividing the 2n divided signal ■ of the period of the first phase signal ■ into six equal parts is obtained, and the clock ■ is synchronized with the first phase signal ■. The feature is that the second phase signal (2) having a desired phase difference is generated.

[0042]

Effects of the Invention As described above in detail, in the circuit for controlling the rotational speed and torque of a DC motor of the present invention, for example, the central processing unit (CPU) inputs the phase difference into the third counter. By simply setting .
The central processing unit (CPU) can control the rotation speed of the DC motor (M) without requiring any intervention. Therefore, even when the rotational speed of the DC motor (M) is high, it can be handled by a low-speed central processing unit (CPU), which has the effect of suppressing an increase in costs.

[Brief explanation of the drawing]

[Figure 1] Principle configuration diagram of the present invention

[Fig. 2] A diagram showing an embodiment of the present invention

[Figure 3] Operation time chart of the present invention

[Figure 4] Diagram showing the driving principle of a DC motor

[Figure 5] Diagram explaining a conventional DC motor control circuit

[Figure 6] Operation time chart of conventional DC motor

[Explanation of symbols]

1 DC motor (M)
2 Front edge detection section 3 First counter
41 Latch circuit 42 Second counter 5 Third counter 6 Fourth counter
7 Rectifier circuit 70 Phase generation circuit 8 Drive circuit or drive circuit■ First phase signal (phases A to C)■
Second phase signal (phase A' to C') ■
split signal

Claims (1)

[Claims] Claim 1: In synchronization with the first phase signal (■) outputted by the DC motor (M) (1), a second phase signal with a phase shift is provided.
A control circuit that controls the rotation speed of the DC motor (M) (1) by applying a field current generated based on the first phase signal (■) of the first phase signal (■). A first counter (3) that measures the period divides the measured period into 2n and generates a 2n divided signal (
(2) A latch count unit (41, 42) that outputs , a third counter (5) that outputs the above phase difference in units of 1/2n periods, and an output timing from the third counter (5) At the signal (■), the above 2n
A clock signal (■) for counting the divided signal (■) and generating a phase-shifted second phase signal (■) in synchronization with the first phase signal (■).
a fourth counter (6) that generates the first phase signal (■) or the second phase signal (■
) and a rectifier circuit (7) for determining the direction in which the field current flows, the first phase signal (■
) into the first counter (3), and
The period of the phase signal (■) is measured, and the measured period data is sent to the latch count section (41, 42).
to generate a 2n divided signal (■), and input the generated 2n divided signal (■) to the third counter (5) to which a specific value is set. A timing signal (■) having a phase difference in units of 1/2n periods corresponding to a specific value is obtained, and the fourth counter (6) is controlled based on the obtained timing signal (■). Clock signal for energizing and generating the second phase signal (■)
(■) A rotation speed and torque control circuit for a DC motor, characterized in that it is configured to output.