JPH04371041A - Atm communication processing device - Google Patents

Abstract

PURPOSE:To prevent the increase of the data transfer rate, to simplify the circuit constitution, and to give a flexibility for the increase/reduction of the area for storage of intra-device control information with respect to ATM communication processing device where additional control information is added for the purpose of controlling transfer at the time of transferring data as the processing object in the device. CONSTITUTION:The device consists of plural units including an input unit for data input and an output unit for data output. The input unit is provided with a data input detecting means 1 which detects input of data and a parallel additional information generating means 2 which generates control information for data transfer among plural units in the device in accordance with detection and outputs control information to transfer it in parallel with data in the device.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an ATM communication processing device which is composed of a plurality of units, receives data in a predetermined format, and transfers the input data between the plurality of units along a predetermined route. In particular, the present invention provides additional control information (routing) information to be added to the data to control the transfer when the data to be processed is transferred within the ATM communication processing device. ) is related to the transfer method.

Although the speed of data transmitted in ATM (asynchronous transfer mode) is very high, it is desirable that these data be processed as slowly as possible inside a communication processing device. Furthermore, it is desirable that the configuration for adding additional control information and the like as described above to data to be processed within the apparatus be as simple as possible.

0003

2. Description of the Related Art FIG. 5 shows a schematic configuration of a conventionally proposed digital communication processing device, such as a digital transmission device used in an ATM network. As shown in FIG. 5, the ATM transmission device includes a plurality of input/output interface units IF, a plurality of multiplexing units MUX and demultiplexing units DMUX, a cross-connect unit, and the like. For example, the data input from each input interface unit IF is
Based on the information that determines the input interface unit and the destination information added to the data, predetermined internal control information is added at the input interface unit, and the data is transmitted to multiple units within the device. The data is transferred along a route based on the added intra-device control information, outputted from an output interface unit based on the added intra-device control information, and sent out to a line connected to the output interface unit. In addition, “
150M'' etc. indicate an example of the transmission speed.

FIG. 6 shows the format of an ATM cell. As shown in FIG. 6, each ATM cell on the transmission path consists of 53 bytes, of which 5 bytes are a header section and the remaining 48 bytes are a field of information to be transmitted. In this 5-byte header, VPI indicates a virtual path identifier,
VCI indicates a virtual channel identifier, HEC indicates header error control information, and other information indicates CCI.
TT I. This is as recommended by 432 etc. Here, the header error control information HEC indicates the CRC calculation result of the header part of the ATM cell.
When input to the TM communication processing device, it is removed and the AT
It is added again when outputting from the M communication processing device. Therefore, ATM cells transferred within the device do not include header error control information HEC. Furthermore, as mentioned above, within the device, this header error control information HEC
Internal control information is added to the ATM cell information excluding the .

FIG. 7 shows how internal control information is added within a conventional ATM transmission device. As shown in FIG. 7, conventionally, 52 bytes of ATM cell information excluding the above header error control information HEC include:
An area for accommodating 2 bytes of internal control information is inserted to form an internal cell format of 54 bytes in total, and the information of this internal cell is stored in 1 byte (8 bits).
was transferred between units within the device.

[0006]

[Problems to be Solved by the Invention] However, depending on the conventional device control information addition method as shown in FIG. 7, the area for accommodating the device control information is small, and If an attempt is made to increase the area for accommodating the data, there is a problem in that the data transfer rate within the device increases. Furthermore, as shown in FIG. 7, in order to insert the internal control information between the ATM cell information, the circuit configuration becomes complicated, and the area for accommodating the internal control information must be increased or decreased. There is a problem that there is no flexibility for

[0007] The present invention provides an ATM communication processing device consisting of a plurality of units without increasing the data transfer rate within the device, has a simple circuit configuration, and can accommodate internal control information. It is an object of the present invention to provide an ATM communication processing device that has flexibility in dealing with increases and decreases in area for communication.

[0008]

[Means for Solving the Problem] FIG. 1 shows an AT according to the present invention.
This figure shows the characteristic configuration of the new reception section of the M communication processing device. As shown in FIG. 5 as an example, the present invention is composed of a plurality of units including an input unit that inputs data in a predetermined format including synchronization information, and an output unit that outputs the data. The present invention is intended for an ATM communication processing device in which data input to the input unit is transferred between the plurality of units via a predetermined route.

As shown in FIG. 1, in the ATM communication processing device according to the present invention, the input unit includes:
A data input detection means 1 detects input of data in the predetermined format, and control information for transferring the data between the plurality of units in the apparatus is generated in response to the detection, and The apparatus includes parallel additional information generating means 2 for outputting additional information in parallel with the data so as to be transferred within the apparatus.

0010

[Operation] According to the present invention, when data input is detected by the data input detection means 1, the parallel additional information generation means 2 performs control for transferring the data between the plurality of units in the apparatus. Information is generated in response to this detection and outputted so that the control information is transferred within the device in parallel with the data. Therefore, the control information is transferred within the device in parallel to the data. Therefore, unlike in the past, control information is not inserted between data flows, so the data transfer speed within the device does not increase, and the circuit configuration is simplified, allowing for control within the device. This makes it possible to flexibly respond to increases and decreases in the area for accommodating information.

[0011]

Embodiment FIG. 2 is a diagram showing the configuration of a signal input section (each input unit) in an embodiment of the ATM communication processing device of the present invention. In FIG. 2, 11 is a transmission line, 12 is an S
A TM termination circuit, 13 a cell synchronization circuit, 14 an address counter, 15 a memory, and 16 an additional information generator.

In the embodiment shown in FIG. 2, SDH (Synchronous Transfer) is
The STM-1 frame in the rModule is used as an external frame, and the ATM cell is loaded in the payload area within this frame. Further, the overall configuration of this ATM communication processing device is, for example,
Like the ATM transmission device in Figure 5, multiple input (interface) units and multiple output (interfaces)
units, and between these there are generally multiple units and multiple inputs (interfaces).
It is assumed that an ATM cell input to each unit is to be outputted from any output unit via any one of the plurality of units described above based on the routing information contained in the ATM cell.

FIG. 8 shows SDH (Sy
nchronous Transfer Module
) as the frame structure of data in STM-1
This shows the frame structure of . As shown in Figure 8, each STM-1 frame consists of sections
overhead SOH, AU pointer AU4, and
It consists of a payload PAYLOAD area, and the payload PAYLOAD area further includes a path overhead P.
A plurality of ATM cells are included in the remaining area of the payload PAYLOAD, including the OH.

In the STM termination circuit 12 of FIG. 2, individual ATM cells are separated from the STM-1 frame of FIG. That is, the section overhead SOH
, AU pointer AU4, and path overhead P
Header areas such as OH are removed. In the cell synchronization circuit 13 of FIG. 2, the HEC region as shown in FIG. 6 is detected from the above-mentioned ATM cell, and thereby the phase of the input (received) ATM cell is recognized. This phase information is supplied to the address counter 14. The ATM cells that have passed through the cell synchronization circuit 13 are sequentially applied to the memory 15, but the address counter 14 sends successive write addresses to the memory 15 along with a write control signal based on the above phase information. However, at the timing when the above HEC area is applied to the memory 15, the write control signal is not supplied and the address is not updated. As a result, the HEC area is not written into the memory 15. The address counter 14 also supplies the read address of the memory 15, and the contents of the ATM cells except the above-mentioned HEC area are continuously read from the memory 15. The read contents of the ATM cell excluding the HEC area are supplied to an additional information generating section 16 consisting of a hardware logic circuit.
Based on the virtual path identifier VPI and the identification number of its own input unit among the contents of the TM cell, the AT
Generates routing information indicating what route the M cell should take within the device and from which output unit it should be output from, and other intra-device path monitoring information;
It is output to a signal line for additional control information provided in parallel with the information of the ATM cell at the same timing as that of the ATM cell.

FIG. 3 shows ATM cell information and control information added for transferring the ATM cell within the device, which are output in parallel from the input unit of the embodiment of the present invention as described above. This shows the array of . As shown in FIG. 3, according to this embodiment, a maximum of 52 bits of internal control information can be added to one ATM cell, and one ATM cell is 52 bytes long. Therefore, the transmission speed within the device has not increased.

[0016]

[Table 1]

Table 1 shows that the A
This is an evaluation of how much margin can be given to the TM cell transfer (processing) speed. One frame of STM-1 is 270×9=243 as shown in Table 1.
It has a capacity of 0 bytes. Of these, 81+9=90 bytes of the header portion of this frame are separated by the STM termination circuit 12, so the remaining 53 bytes of A
The TM cells are 44 cells and 8 bytes. According to the conventional method shown in FIG. 7, the length of one ATM cell transferred within the equipment is 54 bytes, so if we evaluate the transmission speed within the equipment as the same as on the transmission path, the length of this one frame is 54 bytes. There is only enough margin to transfer 45 cells within the time. However, according to the present invention, since the length of one ATM cell transferred within the device is 52 bytes,
If we evaluate it on the assumption that the transmission speed within the device is the same as that on the transmission path, there is enough margin to transfer 46 cells and an additional 38 bytes within the time of one frame. Therefore, according to the present invention, the in-device OAM information area can be divided into two cells (125 μsec) without increasing the speed of the processing circuit in the device.
Hit) can be secured.

FIG. 4 is a diagram showing the configuration of the signal output section (each output unit) in an embodiment of the ATM communication processing device of the present invention. In FIG. 4, 21 is a transmission line, 22 is an STM termination circuit, 23 is a cell generation circuit, 24 is a CRC calculation circuit, 25 is an address counter, 26 is a memory, and 27 is a control section. 5 as shown in Figure 3.
The information of the 2-byte long ATM cell is written into the memory 26 one byte at a time. Here, the address counter 25 outputs consecutive write addresses to the memory 26 together with a write control signal. In this way, 52-byte long ATM cell information is temporarily written into the memory 26. The address counter 25 also, on the other hand,
6, outputs consecutive read addresses. However, the address is not updated at the timing when the HEC area should be inserted into this ATM cell. As a result, the HE of the ATM cell read from the memory 15 is
Area C becomes empty. A when this HEC area becomes free
The CRC calculation circuit 24 performs a CRC calculation on the header portion of the TM cell data, and the cell generation circuit 23 inserts the result of this calculation into the HEC area of the ATM cell. In this way, an ATM cell is generated. Such an ATM cell is processed by the STM termination circuit 22.
-1 frame and output onto the transmission line 22.

[0019]

As explained above, according to the ATM communication processing device of the present invention, internal control information is transferred within the device in parallel with data, so it is possible to increase the data transfer speed within the device. In addition, the circuit configuration becomes simple, and it becomes flexible with respect to increases and decreases in the area for accommodating control information within the device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a characteristic configuration of a signal input section of an ATM communication processing device according to the present invention.

FIG. 2 is a diagram showing the configuration of a signal input section in an embodiment of the ATM communication processing device of the present invention.

FIG. 3 is a diagram showing a data arrangement during intra-device ATM cell transfer according to the present invention.

FIG. 4 is a diagram showing the configuration of a signal output section in an embodiment of the ATM communication processing device of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a conventionally proposed ATM communication processing device, for example, an ATM transmission device used in an ATM network.

FIG. 6 is a diagram showing a cell format in ATM.

FIG. 7 is a diagram showing how intra-device control information is added in a conventional ATM transmission device.

[Figure 8] On the transmission path, SDH (Synchronization)
FIG. 3 is a diagram showing a frame structure of STM-1 as a frame structure of data in the ous Transfer Module.

[Explanation of symbols]

1...Data input detection means 2...Parallel additional information generation means 11, 21...transmission line 12, 22...STM termination circuit 13...Cell synchronization circuit 14, 25...address counter 15, 26...Memory 16...Additional information generation section 23...Cell generation circuit 24...CRC calculation circuit

Claims (3)

[Claims] 1. Consisting of a plurality of units including an input unit that inputs data in a predetermined format and an output unit that outputs the data, the data input to the input unit is transmitted between the plurality of units in a predetermined manner. In an ATM communication processing device that transfers data via a route, each of the input units includes data input detection means (1) for detecting input of data in the predetermined format, and data input detection means (1) for detecting input of data in the predetermined format, and data input detection means (1) for transmitting the data between the plurality of units in the device. parallel additional information generation means (2) that generates control information to be transferred in the apparatus in response to the detection, and outputs the control information in parallel with the data so as to be transferred within the apparatus; An ATM communication processing device characterized by: 2. The predetermined format is an ATM cell format, and the input unit is an ATM cell format.
cell synchronization means (13) that detects HEC information from a cell and performs cell synchronization using the HEC information; and HEC information deletion means (14, 15) that removes HEC information from the ATM cell.
), and based on the header information of the ATM cell, the AT
2. The ATM communication processing device according to claim 1, wherein the control information to be added to the M cell is generated and outputted so that the control information is transferred within the device in parallel with the information of the ATM cell. 3. Each of the output units performs a CRC calculation on the header part of the ATM cell information transferred within the apparatus together with the control information, and performs a CRC calculation on the header part of the ATM cell information only. The CRC calculation result of HE
HEC information insertion means (23) that forms and outputs the ATM cell format by inserting it as C information.
, 24, 25, 26).