JPH04368065A - Video signal binarizing circuit - Google Patents

Abstract

PURPOSE:To convert a video signal of information described on paper such as a character or an image into a binary signal. CONSTITUTION:A high level tracking circuit 2 tracking a high amplitude level of a video signal, a low level tracking circuit 3 tracking a low level of a video signal, and an inflection point detection circuit 4 detecting a vertical change point of the amplitude are used to track high and low levels of the video signal and a threshold level generating circuit 6 obtains a signal of an intermediate level from the two level signals. A comparator 5 receives a delay video signal outputted from a delay circuit 1 and an output signal of the threshold level generating circuit 6 to obtain a binarized video signal. Thus, the binarized video signal with less distortion and without being affected of the level of the amplitude of the video signal is obtained.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a circuit for binarizing a video signal, and more particularly to a circuit for converting a video signal obtained from information written on paper such as characters or images into binarized information. This invention relates to a signal binarization circuit.

0002

2. Description of the Related Art Conventionally, this type of binarization circuit uses a fixed binarization method or a floating binarization method as shown in FIG. 4, for example.

In FIG. 4, in a fixed binarization method in which a video signal 20 is binarized at a uniform level such as a threshold value 21, the binarized signal in a section S4 of the video signal is as shown in 24. Become.

Furthermore, in the floating binarization method, a signal 22 that follows the high level of the video signal 20 (ordinarily, if the video signal is generated by photoelectric conversion of the reflected light of information written on paper, the level of the reflected light of the paper) is Binarization is performed using a level 23 below a certain amount as a threshold, and the binary signal becomes 25.

[0005]

According to the prior art described above, it is obvious at a glance that the information obtained by binarizing the section S4 of the video signal 20, such as the binarized signals 24 and 25 in FIG. 4, is inappropriate. . It is clear that there are three pieces of information on the left side of the video signal 20 in section S4, and two pieces of information on the right side, so in the binarized signal 24 or 25, there is similarly “” on the left side.
It is desirable that there be three 1” signals, two on the right side.

However, in the fixed binarization method and the exemplified floating binarization method, a difference occurs between the information of the video signal 20 before binarization and the information of the signal 24 or 25 after binarization.
Therefore, inconvenience occurs.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel video signal binarization circuit that makes it possible to solve the above-mentioned problems inherent in the conventional technology. Our goal is to provide the following.

[0008]

[Means for Solving the Problems] In order to achieve the above object, a binarization circuit according to the present invention is configured to detect information components of a video signal, that is, peak portions of the amplitude (that is, the highest signal level), The valley part of the signal (that is, the lowest signal level) is captured, and the peak part is set as a high signal level, and the valley part is set as a low signal level, and each peak and valley is tracked and held as it occurs, and the high signal level and low signal level are It is configured to binarize the original video signal by setting a threshold value in the middle of the levels.

In order to realize this method, the present invention includes a high level tracking circuit for a video signal, a low level tracking circuit, a circuit for generating an intermediate level thereof, a comparison circuit for binarizing the video signal, and the above-mentioned circuit. It is configured with circuits for timing and phase matching of each circuit.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

Referring to FIG. 1, a delay circuit 1 is a circuit that delays and outputs a video signal by a time ΔT seconds. The high level tracking circuit 2 maintains the high level of the video signal, and the timing for holding the same is given by an inflection point detection circuit 4, which will be described later. The high level tracking circuit 2 also has the high level initial value as its input. The low level tracking circuit 3 holds the low level of the video signal, and the holding timing is given by an inflection point detection circuit 4, which will be described later. The low level tracking circuit 3 also has the low level initial value as its input.

[0013] The inflection point detection circuit 4 detects the peaks and troughs of the amplitude change of the video signal and diagnoses the time when the peak value of the peak or trough reaches its peak value, and when the video signal peaks, the high level tracking circuit 2
Send level tracking timing to maintain high level,
When the video signal is at a valley, level tracking timing is sent to the low level tracking circuit 3 to maintain the low level.

The threshold generation circuit 6 receives the output signals of the high level follow-up circuit 2 and the low level follow-up circuit 3, and outputs an intermediate value between these levels as a threshold value. Comparator 5 compares the delayed video signal with a threshold value, 2
Obtain digitized output.

In the above configuration, when the video signal 10 is supplied to the delay circuit 1, high level follow-up circuit 2, low level follow-up circuit 3, and inflection point detection circuit 4, the following operations occur. In order to ensure understanding, the explanation will be made using the waveform diagram of FIG. 2.

A video signal 10 is provided on conductor 10 . The broken line 14 indicates the output signal of the high level tracking circuit 2. The broken line 15 indicates the output signal of the low level tracking circuit 3. As can be seen in the figure, the change points of the broken line follow the peaks of the video signal.

The two level signals 14 and 15 thus obtained
is supplied to the threshold generation circuit 6. In the example, the threshold generation circuit 6 generates an intermediate value (threshold value) between the level signals 14 and 15.
17 is generated. A delayed video signal 13 delayed by ΔT seconds from the video signal 10 and a threshold value 17 are input to the comparator 5, and a binarized video signal 18 is generated at its output.

FIG. 3 shows delayed video signal 1 of video signal 10.
FIG. 3 is a diagram illustrating a second embodiment of the present invention in which control is performed so that a binarization error does not occur in section S3 of No. 3.

Referring to FIG. 3, in the case of the content explained in FIGS. 1 and 2, the high level tracking timing is sent to the high level tracking circuit 2 near the arrow 19, and the high level output indicated by the broken line 14 is set to the level of the video signal 10. Trying to pull it down closer. Therefore, a circuit for measuring the direction of change in the video signal and the absolute value of the amount of change is added to the inflection point detection circuit 4. In the case of high level tracking, if an inflection point (peak) of the video signal is detected, the current inflection point (peak) will change from the previous inflection point (trough) to the current inflection point (mountain).
Control is performed so that high-level follow-up timing is generated only when the absolute value is greater than or equal to a certain value. This prevents high level output 14 from being pulled down to the level of video signal 10. By performing binarization using the threshold value 17 created with reference to the outputs of the high and low level follow-up circuits thus obtained, a correct binarized signal 18 can be obtained.

In FIG. 1, input lines for initial value inputs 11 and 12 are provided with the high level initial value 14 and low level initial value 15, respectively, of FIG. The time given by this initial value is a time period in which the video signal 10 does not provide information on paper. In FIG. 2, this corresponds to the time at the tail portions at both ends of the video signal 10 where the signal level is lowest.

[0021]

[Effects of the Invention] As explained above, according to the present invention, two
Create two level signals that follow the high and low parts of the amplitude part of the video signal created from the information part of the video signal to be converted into values, take the intermediate level between the high and low as the intermediate value between the two levels, and convert it into the video signal. By binarizing the threshold value, the presence or absence of information can be determined reliably and without error.
An effect that can be converted into value is obtained.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is an output waveform diagram of each part of the circuit shown in FIG. 1;

FIG. 3 is a diagram showing a second example of output waveforms of each part of the circuit shown in FIG. 1;

FIG. 4 is a signal waveform diagram according to a conventional method.

[Explanation of symbols]

1...Delay circuit 2...High level tracking circuit 3...Low level tracking circuit 4...Inflection point detection circuit 5... Comparator 6...Threshold generation circuit 10...Video signal 13...Delayed video signal 17...Threshold value 18...Binarized output signal

Claims (2)

[Claims] 1. A video signal delay circuit, a video signal high level follow-up circuit, a video signal low level follow-up circuit, and the output signals of the high and low level follow-up circuit are input, and a signal at an intermediate level between the two signals is input. A threshold generation circuit that generates
an inflection point detection circuit that detects an inflection point where the amplitude of the video signal changes from rising to falling or from falling to rising, and generates timing for level tracking to the high level tracking circuit and the low level tracking circuit; and the delay circuit. 1. A video signal binarization circuit comprising: a comparator that receives a delayed video signal output from the threshold generating circuit and a threshold signal output from the threshold generation circuit and binarizes the delayed video signal. 2. When the inflection point detection circuit detects an inflection point at which the operation of the inflection point detection circuit changes from a rise to a fall in the video signal, the amount of rise in the video signal at that time is small in absolute amount. 3. The video signal binarization circuit according to claim 2, further characterized in that level follow-up timing is not supplied to the high level follow-up circuit.