JPH04366497A - Semiconductor memory integrated circuit - Google Patents

Abstract

PURPOSE:To enable shortening of writing time by making all memory cells non-selectable without delaying the selection of the memory cells to eliminate set up time of a writing pulse. CONSTITUTION:When writing a data into a memory cell array 5 through a read/write circuit 9 based on a writing control signal, a control circuit 8 transmits an address non-selection signal to X and Y address selection circuits 2 and 4 to turn the selection of the address to a non-selectable position temporarily. Such memory cells in transition become the least in the cell holding voltage thereby enabling quick writing with stable condition.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory integrated circuit, and more particularly to a semiconductor memory device such as a synchronous SRAM that latches input signals and control signals.

0002

2. Description of the Related Art A conventional semiconductor memory device such as a synchronous SRAM is constructed using an address latch, an address selection circuit, a memory cell array, etc., and is capable of writing and reading.

FIG. 4 shows an example of such a conventional synchronous SR.
It is a circuit diagram of AM. As shown in Figure 4, the conventional SRA
M includes a memory cell array 5, X and Y address selection circuits 2 and 4 for selecting one memory cell in this memory cell array 5, and reading or writing the contents of the selected memory cell. A read/write circuit 9 for writing input data into the memory cell, a control circuit 8 for controlling the read/write circuit 9 using various external control signals and switching between write and read operations, and a memory cell. An output latch 10 for outputting the data read from the external device using a clock; It is composed of a clock circuit 6 that outputs a clock, and a control signal latch 7 that controls a control circuit 8 using data input, a write control signal, and a selection signal. This control signal latch 7 also inputs a control clock from the clock circuit 6, but in particular, the write control signal to this latch 7 is sent to the memory cell only after the address has been determined, in order to prevent erroneous writing to other memory cells. It is generated so that it can be transmitted to. Also,
Clock circuit 6 outputs an address clock to X address latch 1 and Y address latch 3, and outputs an output clock to output latch 10, thereby synchronizing each latch.

FIG. 5 is a block diagram of the memory cell shown in FIG. 4. As shown in FIG. 5, the two memory cells are memory cells composed of bipolar transistors, and the word driver transistor QW connected to the word line.
T1, QWT2, write transistors QWC1, QWC2 connected to digit lines RWC1, RWC2, and read current sources ID1, ID2 are configured in a matrix, and cell PNP transistors QP1, QP2 and multi-emitter cell NPN are arranged at the intersections thereof. A memory cell composed of transistors QN3 and QN2 is connected to a memory cell similarly composed of PNP transistors QP3 and QP4 and NPN transistors QN3 and QN4. Each of the multi-emitter NPN transistors QN1 and QN2 connects one emitter to the digit line RWC.
1 and RWC2, and the other emitter is connected in common to the holding current source IH1. Similarly, QN3, QN
4 also connects digit lines RWC1, RWC2 and holding current source IN2.
connected to. In such a memory cell array 5, during writing, write transistors QWC1, Q
Writing is performed by applying a potential higher than the higher base potential (A1, B1) of the cell and lower potential than the lower base potential of the cell to the base of WC2.

FIG. 6 is a signal waveform diagram at each point in the memory cell for explaining the write timing in FIG. As shown in FIG. 6, the base potentials A1,
B1, A2, and B2 become complementary. VH at this time is the cell holding voltage.

[0006]

[Problems to be Solved by the Invention] In the conventional synchronous memory integrated circuit described above, in order to prevent erroneous writing during writing, the writing pulse is input after the selection of the memory cell is confirmed. There is. Therefore, since the write cycle time consists of a setup time, a write pulse time, and a hold time, it tends to be longer than the read cycle time. However, due to recent demands for miniaturization and higher speed, the setup time has become relatively longer than the write time. For example, if the write pulse time is 3ns, the setup time and hold time are each 1ns, the write cycle time is 5nS.
sec, and the address access time is 3 to 5 ns'.
Compared to this, it is considerably longer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory integrated circuit that can eliminate such setup time and shorten write time.

[0008]

Means for Solving the Problems The semiconductor memory integrated circuit of the present invention includes a memory cell array, X and Y address latches for inputting and latching address signals, and An X and Y address selection circuit that selects the address of the memory cell array, a read/write circuit that writes and reads data to and from the memory cell array, and various controls based on an external clock. a clock circuit that creates a clock; a control signal latch that inputs data input, a write control signal, and a selection signal and latches the control signal;
the X and Y based on the output from the control signal latch.
a control circuit that generates an address deselection signal and various control signals for deselecting the selection operation of the address selection circuit; and an output latch for outputting data from the read/write circuit to the outside; The device is configured to send out the address non-selection signal by detecting a write state when the clock is input, and to generate an internal write signal before the end of the address non-selection signal.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a synchronous SR showing an embodiment of the present invention.
It is a circuit diagram of AM. As shown in FIG. 1, the synchronous SRAM of this embodiment includes X and Y address latches 1 and 3 that latch address inputs, and an X and Y address selection circuit that selects each address based on the output of these latches 1 and 3. 2 and 4, and a memory cell array 5 whose addresses are specified by these selection circuits. Furthermore, in order to control reading and writing of the memory cell array 5, this embodiment includes a clock circuit 6 that inputs an external clock to generate an address clock control clock and an output clock, and a clock circuit 6 that inputs an external clock and generates an address clock control clock and an output clock, and a clock circuit 6 that inputs an external clock and generates an address clock control clock and an output clock. A control signal latch 7 inputs a selection signal and latches the control signal using a control clock from a clock circuit 6, and a control signal latch 7 inputs a control signal from this latch 7 to temporarily stop the selection operation of the X, Y address selection circuits 2 and 4. A control circuit 8 that generates an address non-selection signal and various other write/read control signals, etc., and a read/write circuit that performs writing or reading between the control circuit 8 and the memory cell array 5 based on the control signals from the control circuit 8.
It has a write circuit 9 and an output latch 10 that sends data from the read/write circuit 9 to the outside using an output clock.

In such a synchronous SRAM, when a clock is input to the clock circuit 6 and outputs an address clock, a control clock, etc., and the memory cell array 5 is in a write state, the control circuit 8 outputs an address non-selection signal. is generated for 1 nsec and the X, Y address selection circuit 2
, 4 are unselected, and all memory cells are once unselected. At this time, write transistors QWC1,
A potential higher than the cell potential high and a potential lower than the low cell potential is applied to the base of the QWC2 (see FIG. 5) corresponding to data 0 and 1. Next, the address non-selection signal is released and the memory cell transitions to the selected state. Writing to the memory cell is started at the same time as this selected state is reached. That is, the cell becomes in a state corresponding to data 0 and 1, and writing is completed. A memory cell during such a transition can be written to faster than in a stable state because the cell's holding voltage VH is at its lowest. The write cycle time in this embodiment is 1 ns for address non-selection time.
, write pulse width is 2.5ns, hold time is 1n
s, and the total time is 4.5 ns, so writing can be performed 0.5 ns faster than in the conventional example described above.

FIG. 3 shows a synchronous S system according to another embodiment of the present invention.
It is a circuit diagram of RAM. As shown in FIG. 3, in this embodiment, the clock circuit 6 generates an address non-selection signal based on an external clock, a write control signal, and a chip selection signal, and The difference is that they are sent to selection circuits 2 and 4. Since the address non-selection signal is sent from the clock circuit 6, this embodiment is 0.2 times smaller than the previous embodiment by one stage of the control circuit 8.
ns can be written even faster. It should be noted that the other circuit configurations and operations are the same as those of the above-mentioned embodiment, so explanations thereof will be omitted.

[0013]

Effects of the Invention As explained above, the semiconductor memory integrated circuit of the present invention generates a signal that deselects all memory cells when entering a write state, thereby deselecting all memory cells without delaying the selection of memory cells. Since the memory cells can be temporarily unselected, the write pulse setup time can be eliminated and the write time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a synchronous SRAM showing an embodiment of the present invention.

FIG. 2 is a signal waveform diagram at each point of a memory cell for explaining write timing in FIG. 1;

FIG. 3 is a circuit diagram of a synchronous SRAM showing another embodiment of the present invention.

FIG. 4 is a circuit diagram of a synchronous SRAM showing an example of the related art.

FIG. 5 is a configuration diagram of a memory cell shown in FIG. 4;

6 is a signal waveform diagram at each point of a memory cell for explaining write timing in FIG. 4; FIG.

[Explanation of symbols]

1 X address latch 2 X address selection circuit 3 Y address latch 4 Y address selection circuit 5. Memory cell array 6 Clock circuit 7 Control signal latch 8 Control circuit 9 Read/write circuit 10 Output latch

Claims (2)

[Claims] 1. A memory cell array; X and Y address latches that input and latch address signals; An address selection circuit, a read/write circuit for writing and reading data between the memory cell array, a clock circuit for creating various control clocks based on an external clock, and data input and write control. a control signal latch for inputting a signal and a selection signal and latching a control signal; an address deselect signal for deselecting the selection operation of the X and Y address selection circuits based on the output from the control signal latch; and various controls. It has a control circuit that creates a signal, and an output latch that outputs data from the read/write circuit to the outside, and detects the write state when the clock is input to generate the address non-selection signal. What is claimed is: 1. A semiconductor memory integrated circuit, wherein an internal write signal is generated before the end of the address non-selection signal. 2. An address non-selection signal from the control circuit is generated by the clock circuit based on the write control signal and the selection signal, and is sent to the X and Y address selection circuits. The semiconductor memory integrated circuit described.