JPH04361567A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a large impulse current to flow out of a semiconductor device by a method wherein the control electrode of a P-channel transistor is connected to a second high potential power supply, and the control electrode of an N-channel transistor is connected to a second low potential power supply. CONSTITUTION:The source 6 and the diffusion layer 7 of an upper P-channel transistor Q1 of a protection element A are connected to a first power supply VDD1 which serves as power supply of an input circuit, and the gate 5 is kept at a certain potential by another power supply VDD2 of an inner circuit. The same as above, the source 6 and the diffusion layer 7 of a lower N-channel transistor Q2 are connected to a VSS1 power supply, and the gate 5 is connected to a VSS2 power supply. Therefore, even if the first power supply VDD1 and VSS2 are changed in potential when the charge is supplied through the sources of the transistors Q1 and Q2 the transistors Q1 and Q2 are prevented from changing in gate potential corresponding to the change of the first power supply in potential, because the second power potential is isolated from the first power potential.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a protection element for protecting circuit elements connected to external terminals from static electricity, impact voltage, and the like.

Generally, MOS transistors have a gate part insulated from a channel by an extremely thin oxide film, so they are vulnerable to overvoltages and shock voltages applied to the gate, for example during transportation or before mounting on equipment. Furthermore, it is known that after being incorporated into a device, it is charged with static electricity, etc., and dielectric breakdown due to overvoltage is likely to occur. For this reason, in semiconductor devices with MOS transistors, in order to protect the gates of internal circuits, protection circuits are installed in the input/output circuits where static electricity or shock voltage is likely to enter from the outside to prevent dielectric breakdown caused by static electricity, etc. is prevented.

0003

2. Description of the Related Art A protection element for an input circuit in a conventional semiconductor device will be described with reference to FIG. This figure is a circuit diagram showing an example of a conventional protection element having a protection transistor. In the figure, an input node n1 connected to the pad portion 1 is first connected to a C-MOS transistor (protection transistor) arranged in the protection element A. That is, as shown in the figure, the input node n1 is the C-MO
It is connected to the series connection node of the source-drain path of both p-channel and n-channel transistors Q1 and Q2 that constitute the S transistor, and is connected to each power supply via diodes D1 and D2 that are parasitic when they constitute a protection transistor. It is connected to VDD and VSS in opposite directions so that no current flows during normal operation. p channel and n channel M
Each gate of the OS transistors Q1 and Q2 is connected to a power supply line VDD or VSS, which has the same potential as the respective source.

Next, the input node n1 is connected to a circuit element of the internal circuit via a resistor R disposed subsequent to the protection element A.
For example, as shown in the figure, it is connected to the inverter INV. The resistor R is formed as a diffused resistor or a poly resistor by a thin film formation technique in the same way as each transistor part.

FIG. 9 shows a cross-sectional view of a p-channel transistor Q1 portion as an example of both protection transistors Q1 and Q2 in the protection element A. Note that FIG. 9 shows an example of the structure of a protection element portion in a conventional semiconductor device. In the figure, in an N-type well 3 formed on a substrate 2 and forming one diffusion region, there are drains 4 forming first diffusion layers forming each p-channel transistor Q1.
, and a source 6 forming a second diffusion layer, and this p
The gate electrode 5 of the channel transistor Q1 is formed on the SiO2 oxide film 10 in the N-type well, and the drain 4 and source 6 are each formed as a P-type diffusion layer. A channel is not formed between each P-type diffusion layer 4 and 6 during normal operation because the gate electrode 5 is connected to a high potential power source and is always maintained at H level. A third diffusion layer (N+) 7 having a conductivity type different from that of the drain 4 and source 6 to which a back gate voltage is applied is formed in the N-type well.

In the conventional semiconductor device, the drain 4 is connected to the pad portion 1 constituting an external input terminal by an aluminum wiring 8, and the third diffusion layer (hereinafter referred to as a diffusion layer) 7 is connected to the gate 5 and the source. 6 and are collectively connected to a high potential power supply VDD line by aluminum wiring or the like. The diffusion layer 7 forms a PN junction with the drain 4 as an anode and the diffusion layer 7 as a cathode, that is, a parasitically formed diode portion D1 (FIG. 8), in the N well 3 together with the drain.

With the above configuration, when this semiconductor device is in operation (for example, when 5V or 0V is applied to the power supplies VDD and VSS), the pad of the p-channel protection transistor Q1 of the protection element A is Since the gate 5 is maintained at the same potential as the source 6 and is off regardless of the input from the pad section 1, the signal level of the input signal input from the pad section 1 is not changed, and the above-mentioned The diffusion layer 7 forms a PN junction (diode part D1) together with the drain 4 as shown in FIG. is not conductive, so diode part D
1 also does not change the signal level of the input signal. Similarly, the n-channel transistor Q2 does not change the signal level, and as a result, the protection element A does not logically change the input signal.

In the above semiconductor device, if positive charges invade the pad portion 1 due to static electricity or the like, and the potential of the drain 4 becomes higher than that of the source, drain, etc. due to the invaded charges, the drain 4 Current flows from the source 6 to the power supply VDD line through the source 6 and through the diffusion layer 7 that forms the diode portion D1 together with the drain 4, and charges flow to the power supply line VDD having a large capacitance. The potential of the input node n1, which tends to rise to a high potential even with a small amount of charge due to its small capacitance, is maintained at a relatively low potential, and the internal circuit connected to this input node n1 via a diffused resistor R etc. In the inverter INV, etc., dielectric breakdown caused by overvoltage is prevented without the gate potential increasing significantly. Similarly, negative charges flow out to power supply line VSS through n-channel transistor Q2 and diode D2.

[0009]

Problem to be Solved by the Invention In the case of the protection element A of the conventional semiconductor device described above, both protection transistors Q1 and Q
2, the gate 5 is connected to the same power supply as the source 6 as described above to ensure proper operation during normal operation. For this reason, for example, in the p-channel transistor Q1, the potential of the gate 5 also increases due to the power supply VDD line, which is given a positive charge and whose potential increases, so the channel decreases or disappears due to the increase in gate potential, causing this channel to increase. There is a problem in that the continuous flow of charge from the drain becomes difficult or is prevented.

For example, when a large amount of impulse current flows into the power supply line and the gate potential rises momentarily and the channel current is reduced or blocked, the on-resistance of the diode section is generally relatively large and the current Since the area of the path is not large, sufficient current flow cannot be obtained by passing current only through the diode portion via the diffusion layer 7. Therefore, as a result of the penetration of high-level impact voltage, the potential of the input node increases significantly, increasing the potential penetrating into the internal circuit, resulting in a serious problem of causing dielectric breakdown in the internal circuit.

[0011] In view of the above-mentioned problem with the conventional protection element of a semiconductor device, the present invention has been developed to prevent the current from flowing due to the intruding charge or impact voltage from continuing even if a large amount of charge or high impact voltage enters from the external terminal. As something that can be leaked out,
The protection function of the protection transistor does not deteriorate easily.
It is an object of the present invention to provide a highly reliable semiconductor device that is unlikely to suffer dielectric breakdown due to impact voltage or the like.

0012

FIG. 1 is a circuit diagram of an input circuit section in a semiconductor device according to a first embodiment of the present invention. In the same figure, 1 is an external terminal (pad part), Q1, Q2
is a transistor, VDD1, VSS1 are the first power supply, V
DD2 and VSS2 are second power supplies.

In order to achieve the above object, the semiconductor device of the present invention has a p-channel connected between an external terminal (1) and a first high-potential side power supply line (VDD1), as illustrated in FIG. It includes a MOS transistor (Q1) and an n-channel MOS transistor (Q2) connected between an external terminal (1) and a first low-potential side power supply line (VSS1), and controls the p-channel MOS transistor. The electrode is connected to a second high-potential power line (VDD2) provided independently of the first high-potential power line, and is connected to the n-channel MOS
The control electrode of the transistor is connected to a second low-potential power line (VDD2) provided independently of the first low-potential power line.
The device is characterized by having a protection circuit connected to.

[0014]

[Operation] Due to the configuration in which the gates of the transistors Q1 and Q2 are connected to the second power supplies VDD2 and VSS2, respectively, the potential of the first power supplies VDD1 and VSS1 that receive charges from the sources of the transistors Q1 and Q2 increases or Even if the second power supply is separated from the first power supply, the gate potentials of the transistors Q and Q21 do not directly rise or fall in accordance with the change in the potential of the first power supply, and the gate potentials of the transistors Q1 and As long as the potential of the drain is high or low, a continuous draining of charge to the first power supply in transistors Q1, Q2 is guaranteed, since the channel does not decrease or disappear in Q2, and the charge enters the drain from external terminal 1. The charge flows to the source side up to the limit limited by the on-voltage of transistors Q1 and Q2, and the drain potential recovers.
A large potential change occurring in the internal circuit elements connected to the external terminal 1 is prevented and these are protected.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in more detail with reference to the drawings. In FIG. 1, this protection element A is a protection transistor Q
In addition to 1 and Q2, PN junction diode portions D1 and D2 are formed parasitically by forming a protection transistor. Each of the diode parts D1 and D2 is inserted in such a direction that its cathode is connected to VDD1 and the input node n1, which form a line on the high potential side, respectively, to block diode current during operation of the semiconductor device, and to form an external terminal. It functions to cause the positive or negative impact current entering from the pad portion 1 to flow out to the first power supply VDD1 and VSS1 lines, respectively.

In addition, in FIG. 1, a diffused resistor R is provided subsequent to the protective element A, and the input node n1 is connected to the internal circuit via the diffused resistor R, as in the conventional semiconductor device.

In FIG. 2, the gate 5 formed on the oxide film 10 is connected to the power supply VDD2 of the internal circuit via the aluminum wiring 82 based on the structure of the present invention, and in this respect, it is different from the conventional diagram. This is different from FIG. The source 6 and the third diffusion layer N+7 are connected to the first power supply VDD1 as in the conventional case.

FIG. 3 is a schematic plan view mainly showing the protection element A portion of the semiconductor device of the embodiment shown in FIG. In the figure, each protection element A is formed in a structure that surrounds a pad 1 as a whole, and a p-channel transistor Q on the upper side of the figure
1 and the lower n-channel transistor Q2. The p-channel transistor Q1 has its source 6 and diffusion layer 7 connected to a first power supply VDD1, which is the power supply for the input circuit section.
and its gate 5 is connected to the power supply V in the input circuit.
Power supply VD from the internal circuit, which is a power supply different from the DD1 power supply
The potential is maintained by the D2 power supply. Similarly n
In the channel transistor Q2, the source 6 and diffusion layer 7 are connected to the VSS1 power supply, and the gate 5 is connected to the VSS2 power supply. Aluminum wiring lines 81 and 82 from the internal circuit are shown with diagonal lines for easy identification in the figure. In addition,
VDD1 and VSS1 supply power to protection element A and an I/O buffer (not shown), and VDD2 and VSS1 supply power to protection element A and an I/O buffer (not shown).
SS2 supplies power to the internal circuit.

From the pad portion 1, both transistors Q1
, an aluminum wiring 8 is connected to the drain 4 of Q2, and a diffused resistance R is formed in the aluminum wiring 8 at the exit of the input circuit section going from this input circuit section to the internal circuit section. It is extending.

FIG. 4 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention. The difference from the embodiment in FIG. 1 is that the gates of p-channel and n-channel protection transistors Q1 and Q2 are connected to the outputs of inverters INV2 and INV3 of the internal circuit, respectively, and the input of one inverter INV2 is connected to the low potential of the internal circuit. The other inverter INV3 is connected to the power supply GND2.
The input is connected to the high potential power supply VDD2 of the internal circuit. As in the first embodiment, during normal operation of the semiconductor device, the outputs of the inverters INV2 and INV3 keep the protection transistors Q1 and Q2 off, and allow charge to flow out in the event of an impact current or the like. do. In the case of this embodiment as well, the gate potential does not change due to the impulse current flowing from the external terminal 1, and therefore the channels of the protection transistors Q1 and Q2 are reduced or eliminated to turn off the protection transistors Q1 and Q2. Never.

FIG. 5 is a circuit diagram of a third embodiment of the present invention. In the circuit shown in the figure, a signal from an internal logic 13 of an internal circuit 12 is input to the gates of transistors Q1 and Q2. Transistors Q1 and Q2 receive a control signal C
When the logic level of NTL'(CNTL' indicates that CNTL has a top bar) is "L", the gate is connected to the power supplies VDD2 and VSS2 of the internal circuit and operates as a protection transistor. Further, when the control signal CNTL' is at the logic level "H", the NAND gate 14 and the NOR
The logic level of the data “H” through the gate 15
or “L” according to the logic level “H” or “L” respectively.
It operates as a logic element that provides a signal to an inverter 17 consisting of transistors Q3 and Q4. Therefore, transistors Q1 and Q2 maintain their inputs at desired levels via the control signals and data outputs from internal logic during circuit testing and the like.

FIGS. 6 and 7 each show an example of the configuration of the power supply in the above embodiment. The power supply configuration in FIG. 6 is an example in which power supplies VDD1 and VSS1 for the input/output section (I/O section) and power supplies VDD2 and VSS2 for the internal circuit are separated from the power supply pads, respectively. Further, in FIG. 7, inside the chip, the power supply is separated between the I/O section and the internal circuit section, but the power supply pad is shared. In the case of the power supply configuration shown in Figure 6,
The charges that have entered from the protection transistors Q1 and Q2 simply increase the potential of the power supply VDD1 or VSS1, so that the gate potentials of these transistors are not affected at all. In the case of the power supply configuration shown in FIG. 7, a rise in potential (noise) of the power supplies VDD1 and VSS1 of the I/O section affects the power supplies VDD2 and VSS2 of the internal circuit through the pad section. However, even in this case, the rise in the potential of the power supply of the I/O section is sufficiently absorbed by the parasitic capacitance and resistance of the power supply line, or the elements of the internal circuit, so the rise in the potential of the power supply of the internal circuit is suppressed to a small level. Protection transistor Q1
, Q2 can be suppressed from increasing in gate potential.

[0023] In each of the above embodiments, a protection element having a diode section is mentioned, but the presence or absence of a diode itself is not an essential requirement of the present invention, and a semiconductor device that does not have a diode section but merely includes a protection transistor. Also included within the scope of the present invention.

[0024] Also, the power supply lines VDD1, VSS1 and VDD
2. The pad may be independent from VSS2, or it may be branched at a common pad, but instead of this, the power supply lines VDD2, VSS2 may be branched, and in either case the object of the invention is achieved.

[0025]

As explained above, according to the semiconductor device of the present invention, the gate potential does not change directly due to charges flowing out from the drain, and the risk of the channel of the protection transistor decreasing or disappearing is suppressed. This has the remarkable effect of safely discharging even a large impact current, preventing dielectric breakdown of the semiconductor device, and improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an input circuit section in a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing the structure of a protection element portion of the input circuit section in FIG. 1;

FIG. 3 is a schematic plan view of the input circuit section of FIG. 1;

FIG. 4 is a circuit diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a schematic plan view (1) illustrating the configuration of power supply separation in the present invention.

FIG. 7 is a schematic plan view (2) illustrating the configuration of power supply separation in the present invention.

FIG. 8 is a circuit diagram of an input circuit section of a conventional semiconductor device.

FIG. 9 is a cross-sectional view showing the structure of a protection element portion of a conventional semiconductor device.

[Explanation of symbols]

1 External terminal (pad part) 2
Substrate 3 N-well (diffusion region) 11
I/O section 12
Internal circuit A Protection elements Q1, Q2 Protection transistors D1, D
2 Diode R
resistance

Claims (3)

[Claims] Claim 1: An external terminal (1) and a first high potential side power supply line (
a p-channel MOS transistor (Q1) connected between the external terminal (1) and the first low-potential side power supply line (VSS1);
transistor (Q2), the p-channel MO
The control electrode of the S transistor is connected to a second high potential power line (VDD2) provided independently of the first high potential power line.
), and the control electrode of the n-channel MOS transistor has a protection circuit connected to a second low-potential power line (VSS2) provided independently of the first low-potential power line. Semiconductor equipment. Claim 2: A first power supply pad commonly connected to a first power supply pad.
The high potential side power supply line (VDD1) and the second high potential side power supply line (VDD2) of the a p-channel MOS transistor (Q1) connected between a potential side power line (VSS2), an external terminal (1) and the first low potential side power line; an n-channel MOS transistor (Q2) connected between the power supply line on the low potential side and a control electrode of the p-channel MOS transistor connected to the second power supply line on the high potential side; A semiconductor device including a protection circuit in which a control electrode of a MOS transistor is connected to the second low-potential side power supply line (VSS2). 3. The first high-potential power line and the first low-potential power line supply a power supply voltage to an interface circuit, and the second high-potential power line and the second low-potential power line supply a power supply voltage to an interface circuit. 3. The semiconductor device according to claim 1, wherein the side power supply line supplies a power supply voltage to an internal circuit connected to the interface circuit.