JPH04360410A - Sinc filter - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity while keeping a required function for a SINC filter. CONSTITUTION:A shifter 100 shifting a low-order bit data is provided just before an accumulator ACCn at a final stage in an IIR filter and a required bit number for the accumulator ACCn is decreased. Thus, overflow is prevented by the shift to suppress a bit width.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SINC filter, and more particularly to a technique for reducing the amount of hardware in a filter.

0002

2. Description of the Related Art A SINC filter is a low-pass filter having frequency characteristics as shown in FIG. filters used to convert data and remove noise.

Conventional SINC filters include a cyclic (IIR) filter and an acyclic (FIR) filter, as shown in FIG.
It is configured by connecting a filter. The IIR filter is
It is constructed by connecting n stages of accumulators (ACC) in series, each consisting of an adder (ADD) and a delay means (Z-1) such as a D-type flip-flop. Further, the FIR filter is constructed by connecting n stages of accumulators in series, each of which is a combination of M-order delay means (Z-M) and a subtracter (SUB).

[0004] In order to make the cutoff characteristic of this SINC filter steeper (that is, to increase the output attenuation rate), the order of the SINC filter must be increased, or the number of times the input is accumulated, that is, the decimation rate must be increased. It is necessary to.

[0005]

[Problem to be Solved by the Invention] The maximum bit width of the output of the SINC filter is determined by the order of the SINC filter and the thinning rate.
1”, the order is “n”, and the thinning rate is 2 to the “M” power, the maximum bit width is (1+n×m+1=n×m+2)
Becomes a bit.

Therefore, as described above, when the order of the filter and the thinning rate are increased in order to increase the output attenuation rate, the number of output bits of the SINC filter also increases according to the above formula. For this reason, conventionally, when designing a filter, the bit width of the hardware (accumulator, flip-flop, etc.) that makes up the filter is set such that the bit width of the input data is "1" and the order of the SINC filter is "n".
, when the thinning rate is 2 to the "m" power, the bit width is uniformly determined to be (1+n×m+1=n×m+2) bits.

An example of such a conventional filter is shown in FIG.
) is shown. This conventional example is a SINC in which the input data bit width is "10", the order is "2", and the thinning rate is "256".
It's a filter.

As shown in the figure, the maximum bit width of the final stage (second stage) accumulator (ACC2) constituting the IIR filter is 27 bits, and this bit width determines the function of the subsequent circuit (FIR filter). The bit width is fixed.

However, in reality, as mentioned above, SIN
The attenuation characteristic of the C filter is not so large as shown in Fig. 6(b) (that is, it does not have a steep attenuation characteristic as shown in Fig. 6(a)), and for this reason, only a small portion of the output is actually used. is only the upper bit of the output. Therefore, if the bit width is set uniformly as described above, in reality, unnecessary bits will be provided.

The present invention has been made based on such considerations, and its purpose is to reduce the amount of hardware while maintaining the necessary functions of the SINC filter.

[0011]

[Means for Solving the Problems] The present invention is characterized in that a shifter for shifting lower bit data is provided immediately before the final stage accumulator (ACC) in the IIR filter, which determines the maximum bit width of the circuit. That is.

0012

[Operation] In the present invention, data is shifted and then accumulated to prevent overflow and suppress the bit width.

[0013]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. (Structure) FIG. 1 is a diagram showing the structure of an embodiment of the SINC filter of the present invention. A feature of this embodiment is that a shifter 100 is provided before the final stage accumulator (ACCn) to reduce the bit width required for this final stage accumulator (ACCn).

The lower bit width α to be shifted shown in FIG. 2 is determined so as to satisfy at least the minimum level of attenuation characteristics required of the SINC filter. The maximum bit width after shifting is (n-1)×m+2-α.

As a specific example, FIG. 3(b) shows an S with a bit width of "10", an order of "2", and a thinning rate of "256".
A block diagram of an INC filter is shown. Unlike in FIG. 3(a), a 7-bit lower shifter 200 is provided before the final stage accumulator, and even if the bit width of the final stage accumulator is not 27 bits as in the conventional case (20 bits is sufficient in this example), Prevents overflow from occurring.

FIG. 3(c) shows the case of tertiary thinning with a thinning rate of 256. In this case, the upper 12 bits of the output are used, the shift amount of the shifter 300 is set to 6 bits, and the output bit width is suppressed to 20 bits. (Operation) The operation will be explained using FIG. 3(b). The input 10-bit width data is first input to the accumulator AC.
It is accumulated at C1 the number of times corresponding to the thinning rate of 256. As a result, the bit width becomes 19 bits. If this 19-bit data is directly accumulated again, the output of the SINC filter becomes 27-bit data, as shown in FIG. 3(a). However, if only the upper 12 bits of this output are used, the lower 7 bits of the 19 output bits will not affect the output.

Therefore, the output of ACC1 is transferred to the shifter 200.
Shift to the lower 7 bits with and then shift the accumulator ACC
Add to 3. Then, the bit width after that will also be automatically set to 7.
This means that the bits can be small, and the maximum bit width can be suppressed to 20 bits.

FIG. 4 is a diagram showing the configuration of a ΣΔ A/D converter using the SINC filter of FIG. 3(c). The data quantized by the 1-bit quantizer 8 is converted into a multi-bit signal by the multiplexer 9, and is input to the SINC filter. This SINC filter is used to cancel oversampling of the quantized output and convert it into normal data, and to remove noise. Since the amount of filter hardware can be reduced, ΣΔA/
The overall configuration of the D converter can also be simplified.

[0019]

[Effects of the Invention] As explained above, the present invention uses a shifter to suppress the output bit width of a SINC filter, thereby reducing the amount of hardware required for filter configuration while maintaining necessary functions. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of a SINC filter of the present invention.

FIG. 2 is a diagram showing the state of data after lower bit shifting.

FIG. 3(a) is a diagram showing the configuration of a conventional example as a comparative example, (b) is a diagram showing the configuration of a second-order SINC filter to which the present invention is applied, and (C) is a diagram showing the configuration of a second-order SINC filter to which the present invention is applied. Next SIN
It is a figure showing the composition of a C filter.

[Fig. 4] ΣΔA/ using the SINC filter of the present invention
It is a figure showing the composition of a D converter.

FIG. 5 is a diagram showing the configuration of a conventional example.

FIG. 6(a) is a diagram showing the frequency characteristics of a low-pass filter having a steep cutoff characteristic, and FIG. 6(b) is a diagram showing the frequency characteristics of the SINC filter.

[Explanation of symbols]

1 Prefilter 2 Arithmetic unit 3 Integrator 4 Comparator 5 Delay circuit 8 1-bit quantizer 100, 200, 300 Shifter ACC Accumulator ADD Adder Z-1 Delay means SUB such as a D-type flip-flop
Subtractor Z-M Delay means

Claims (1)

[Claims] 1. A SINC filter configured by connecting a cyclic (IIR) filter and an acyclic (FIR) filter, wherein the cyclic (IIR) filter has an accumulator (ACC) in n stages ( n is a natural number greater than or equal to 2)
1. A SINC filter configured to be connected in cascade, and characterized in that a shifter for shifting lower bit data is provided immediately before a final stage (n-th stage) accumulator.