JPH04360340A - Cell transfer equipment - Google Patents

Abstract

PURPOSE:To transfer a cell with higher priority earlier than a cell with lower priority to an outgoing line at all times. CONSTITUTION:When a cell is inputted from incoming lines 1001-100m in the operation step 1, an incoming line module stores the cell to its internal priority depending buffer. The incoming line module storing a cell in its incoming side buffer makes a request of a cell transmission right to buses 21, 22 in the operation step 2. The incoming line module survived in the contention of the cell transmission right reads the cell from its internal incoming side buffer and sends the cell to a bus together with an outgoing line number of an output destination. Each outgoing line module selects and receives only the cell addressed to its own outgoing line from the bus and stores it to the outgoing buffer. The outgoing line module reads a cell from an outgoing side buffer and outputs the cell to an outgoing line in the operation step 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell transfer device for transferring communication information such as voice and data using fixed length cells having a header for routing.

0002

2. Description of the Related Art FIG. 5 shows the configuration of a conventional cell transfer device.

In FIG. 5, 4001 to 400m are incoming lines, 4011 to 401m are incoming line modules, and 6001 to 6
00n is the outgoing line, 6011-601n is the outgoing line module,
51, 52, and 53 are buses, and 54 is a frame synchronization signal generation circuit.

FIG. 6 shows the configuration of the input line module 401i. In FIG. 6, 402i is a frame synchronization circuit, to which a frame synchronization signal is input from the frame synchronization signal generation circuit 54 through the bus 53. The output of the frame synchronization circuit 402i is input to each circuit in the input line module 401i.

[0005] 403i is an incoming line interface (I/F)
404i is an input buffer, and 410i is a cell transmission circuit.

[0006] 405i and 406i are incoming I/Fs, respectively.
These are write cells and write signals from the circuit 403i to the input buffer 404i.

407i is an empty signal of the input buffer 404i, and 408i is an empty signal of the input buffer 404i.
This is a read cell from the cell transmission circuit 410i. 4
09i is the input buffer 40 from the cell transmitting circuit 410i.
This is a read signal to 4i. An incoming line 400i is connected to the incoming buffer 404i.

411i is a cell output of a cell transmitting circuit 410i, and 412i is a driver. The cell output 411i is
It is connected to bus 52 via driver 412i.

413i is a bus access number setting circuit;
14i is a sending control circuit, 415i is a bus access number sending circuit, 416i is a driver, 417i is a receiver, and 418i is a competition circuit.

Further, 419i is a mismatch detection signal of the competition circuit 418i, 420i is a winning/remaining determination signal of the competition circuit 418i, 421i is a transmission control signal of the transmission control circuit 414i, and 422i is an output from the bus access number transmission circuit 415i. .

An empty signal 407i is input to the transmission control circuit 414i, and the bus access number transmission circuit 41
5i, the output of the bus access number setting circuit and the sending control signal 421i are input. The bus access number sending circuit output 422i is sent to the bus 5 via the driver 416i.
1 is connected by wired or.

A bus 51 is connected to the receiver 417i. The output of the receiver 417i and the bus access number sending circuit output 422i are input to the competition circuit 418i. Further, the winning/remaining determination signal 420i is input to the cell transmitting circuit 410i.

FIG. 7 shows the configuration of the outgoing line module 601j. In FIG. 7, 602j is a frame synchronization circuit, and the frame synchronization signal output from the frame synchronization signal generation circuit 54 is inputted through the bus 53. The output of the frame synchronization circuit 602j is input to each circuit in the output module 601j.

603j is a receiver, 604j is a cell selection receiving circuit, 605j is an output buffer, and 611j is an output line I/F circuit. Bus 52 is connected to cell selection receiving circuit 604j via receiver 603j.

Reference numerals 606j and 607j represent a write cell and a write signal, respectively, from the cell selection receiving circuit 604j to the output buffer 605j. 608j is an empty signal of the output buffer 605j. 609j is a read cell from the output buffer 605j to the output I/F circuit 611j, and 610j is a read signal from the output I/F circuit 611j to the output buffer 605j. Outgoing line I/F
Circuit 611j is connected to output line 600j.

A counter 612j receives a write signal 607i and a read signal 610i. 6
13j is a congestion notification signal of the counter 612j.

614j is a bus access number setting circuit;
15j is a bus access number sending circuit, and 616j is a driver. The congestion notification signal 613j of the counter 612j and the output of the bus access number setting circuit 614j are input to the bus access number sending circuit 615j. An output 617i of the bus access number sending circuit 615j is input to a driver 616j, and the driver 616j is connected to the bus 51 by wired OR.

Next, the operation of the above structure will be explained by dividing it into operation (1), operation (2), and operation (3).

Operation (1), operation (2), and operation (3) are each executed independently. Through the following operations, cells from the incoming line are output to the desired outgoing line.

In operation (1), when a cell is input from the input line, the input line module stores the cell in an internal input buffer. In action (2), the ingress module storing the cell in the ingress buffer requests the right to send the cell onto the bus. The incoming module that survives the competition for cell sending rights is
The cell is read from the internal incoming buffer and sent to the bus along with the destination outgoing line number. Each outgoing module selectively receives only cells addressed to its own outgoing line from the bus and stores them in the outgoing buffer. In operation (3), the outgoing line module reads the cell from the outgoing buffer and outputs it to the outgoing line.

These operations (1), (2), and (3) will be explained by taking the incoming line module 401i and the outgoing line module 601j as an example.

Prior to explaining the operation, contention control based on bus access numbers will be explained. Each incoming line module sends a bus access number given to each incoming line to the bus 51 in order to obtain the right to send cells to the bus 52. In the competition for the cell sending right, the module with the highest bus access number among the incoming modules that requested the cell sending right wins. In order to make competition for cell transmission rights fair, a bus access number setting circuit 413i inside the incoming line module updates the bus access number of the own incoming line every cycle of the frame synchronization signal x (x is a constant).

On the other hand, each outgoing module sends out a bus access number and requests a cell sending right when its internal buffer is congested. The outgoing module does not transmit cells even if it obtains the right to transmit cells. The bus access number of each outgoing module is fixed and is assigned a larger value than the bus access number of the incoming module. Therefore, when an outgoing module requests the right to send a cell, it always wins.

FIG. 8 shows the operation timing of the processed signal. Contention control, sending cells to the bus, and receiving cells from the bus are performed in synchronization with the frame synchronization signal from the frame synchronization signal generation circuit 54. Signal 81 in FIG. 8 is a frame synchronization signal. The signal 83 is an example of a signal on the bus 51, and the timing 85 in the signal 83 is the timing at which the incoming module and the outgoing module send a bus access number to the bus 51 in competition control. A signal 86 is an example of a signal on the bus 52, and a timing 87 is a timing at which the winning incoming module that sent out the bus access number at timing 85 sends out the destination outgoing line number and cell from the cell transmission circuit.

First, operation (1) will be explained. In FIG. 6, when a cell arrives at the incoming line 400i, the incoming line I/F circuit 4
01i receives the cell. Next, write signal 406
i is activated to write the cell to the incoming buffer 404i through the write cell 405i. The input buffer 404i makes the empty signal 407i active when it does not store a cell, and makes it inactive when it stores a cell.

Next, operation (2) will be explained. When the empty signal 407i is inactive, the sending control circuit 414i makes the sending control signal 421i active at bus access number sending timing 85 in FIG. The bus access number sending circuit 415i sends out the sending control signal 42
When 1i is active, bus access number setting circuit 4
The bus access number input from 13i is output to bus 51.

At the same time, receiver 417i receives the bus access number on bus 51 and outputs it to contention circuit 418i. The competition circuit 418i compares the transmitted bus access number and the bus access number input from the receiver 417i bit by bit. If they match, the winning/remaining determination signal 420i is activated. When there is a mismatch, the mismatch detection signal 419i is activated.

The transmission control circuit 415i outputs a mismatch signal 419.
When i is active, the transmission control signal 421i is made inactive regardless of the empty signal 407i, and transmission of the bus access number is stopped.

The cell transmitting circuit receives a winning/remaining determination signal 420
When i is active, the cell is read from the input buffer 4041i, the output destination line number is analyzed from the header, and the cell sending timing 8 in FIG. 8 is performed in the order of the output destination line number and the cell.
7, output to bus 52.

At the same time, the outgoing line module 601i receives the outgoing line number on the bus 52 and compares it with its own outgoing line number. If they match, the cell following the outgoing line number is received, and the cell is written into the outgoing buffer 305i through the outgoing write cell 606i. The counter 612i receives the write signal 607i.
Each time the read signal 610i becomes active, it counts up, and every time the read signal 610i becomes active, it counts down. When the congestion notification signal 613i from the counter 612i is active, the bus access number sending circuit 615i
outputs the bus access number input from the bus access number setting circuit 614i to the bus 51.

Operation (3) will be explained. When the empty signal 608i is inactive, the outgoing I/F
The circuit 611i activates the read signal 610i, reads out the cell, and outputs it to the outgoing line 600i.

In this manner, the conventional cell transfer device described above can also transfer cells to any outgoing line.

[0033]

However, since the conventional cell transfer device described above has only a single buffer for each incoming line, cells can only be sent out in the order in which they are input to each incoming line. There was a problem in that cells could not be transferred to the outgoing line before cells with lower priority.

[0034] The present invention solves the above problems,
To provide an excellent cell transfer device capable of always transferring a cell with a high priority to an outgoing line before a cell with a low priority.

[0035]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides priority-based buffering means for buffering cells input to an incoming line by priority for each incoming line, and buffering means for buffering cells input to all incoming lines. The incoming line that is buffering the cell with the highest priority among the cells that are currently in use is connected to the cell sending right contention means configured to obtain the right to send out cells to the shared bus, and the incoming line that has obtained the right to send out the cell , a cell reading means for reading out a cell with the highest priority from among the buffered cells, so that the incoming line that is buffering the cell with the highest priority among all the incoming lines obtains the cell sending right. This is what I did.

[0036]

[Operation] Therefore, according to the present invention, the cell with the highest priority is checked from among the cells buffered for each incoming line, and the cell with the highest priority is buffered by comparing it on all incoming lines. By obtaining the right to transmit cells from the incoming line, cells with high priority can always be transferred to the outgoing line before cells with low priority.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the embodiment. Figure 1
, 1001-100m is the incoming line, 1011-10
1m is the incoming line module, 3001~300n is the outgoing line, 3
011-301n are outgoing line modules, 21, 22, 23
24 is a bus, and 24 is a frame synchronization signal generation circuit.

FIG. 2 shows the configuration of the input line module 101i. In FIG. 2, 102i is a frame synchronization circuit, and a frame synchronization signal is inputted from the frame synchronization signal circuit 24 through the bus 23. In FIG. The output of the frame synchronization circuit 102i is input to each circuit within the input line module 101i.

103i is an incoming line I/F circuit;
An input line 100i is connected to the /F circuit 103i. 104i is a cell output of the input line I/F circuit 103i,
105i is a cell distribution circuit of the input line I/F circuit 103i.

The cell distribution circuit 105i has a cell output 10
4i is input. 106i and 107i are input buffers. 108i and 109i are cell distribution circuits 105
This is a write cell and write signal from i to the input buffer 106i.

110i and 111i are cell distribution circuits 105
This is a write cell and a write signal from i to the input buffer 107i. 112i and 115i are input buffers 10
6i and 107i empty signals. 118i is a cell transmitting circuit; 113i and 116i are reading cells from the input buffers 106i and 107i, respectively, to the cell transmitting circuit 118i; 114i and 117i are cell transmitting circuits 118
This is a read signal from i to the input buffers 106i and 107i. 119i and 120i are respectively transmitting circuits 11
8i cell output and driver. Cell output 119i is connected to bus 22 via driver 120i.

121i is a bus access number setting circuit; 1
22i is a priority detection circuit, 123i is a transmission control circuit, 1
24i is a selector, 125i is a bus access number sending circuit, 126i is a driver, 127i is a receiver and 1
28i is a competition circuit.

Further, 129i is a priority detection circuit 122i.
cell presence/absence detection signal from to the sending control circuit 123i, 13
0i is a mismatch detection signal from the competition circuit 128i to the transmission control circuit 123i, 131i is a priority signal from the priority detection circuit 122i to the cell transmission circuit 118i and the selector 124i, and 132i is a bus access number transmission circuit 125i from the transmission control circuit 123i. 133i is the bus access number sending circuit output, 134i is the competition circuit 1
28i to the cell transmission circuit 118i.

Empty signals 112i and 115i are input to the priority detection circuit 122i, and the selector 124i
The output of the bus access number setting circuit 121i and the priority signal 131i are input to the bus access number setting circuit 121i. The output of the selector 124i and the sending control signal 132i are input to the bus access number sending circuit 125i. The bus access number sending circuit output 133i is connected to the bus 21 via a driver 126i in a wired-OR manner.

The bus 21 is connected to the receiver 127i. The output of the receiver 127i and the bus access number sending circuit output 133i are input to the competition circuit 128i. Further, the winning/remaining determination signal 134i and the priority signal 131i are input to the cell transmitting circuit 118i.

FIG. 3 shows the configuration of the outgoing line module 301j. In FIG. 3, 302j is a frame synchronization circuit, which connects the frame synchronization signal generation circuit 23 to the shared bus 2.
A frame synchronization signal is input through 1. The output of the frame synchronization circuit 302j is sent to the output line module 301.
It is input to each circuit in j.

303j is a receiver, 304j is a cell selection receiving circuit, and 305j is an output buffer. Bus 22 is connected to cell selection receiving circuit 304j via receiver 303j.

306j is a write cell from the cell selection receiving circuit to the output buffer 305j, 307j is a write signal, and 311j is an output line I/F circuit 311j. 308j is an empty signal of the output buffer 305j, and 309j is an empty signal from the output buffer 305j to the output line I/
The read cell 310j to the F circuit 311j is the output line I
This is a read signal from the /F circuit 311j to the output buffer 305j. The output of the outgoing line I/F circuit 311j is connected to the outgoing line 300j.

312j is a counter to which a write signal 307i and a read signal 310i are input. 3
13j is a congestion notification signal of the counter 312j.

314j is a bus access number setting circuit;
15j is a bus access number sending circuit, and 316j is a driver. The bus access number sending circuit 315j includes a congestion notification signal 313j and a bus access number setting circuit 314.
The output of j is input. The bus access number sending circuit output 317i is connected to the bus 21 via a driver 316j in a wired-OR manner.

Next, the operation of the above configuration will be explained by operation and operation (2).
) and operation (3). Action (1) and action (
2) and operation (3) are executed independently. Through the following operations, cells from the incoming line are output to the desired outgoing line.

In operation (1), when a cell is input from the incoming line, the incoming line module stores the cell in an internal priority buffer. In action (2), the ingress module storing the cell in the ingress buffer requests the right to send the cell onto the bus. The incoming line module that survives the competition for cell sending rights reads the cell from its internal incoming buffer and sends it to the bus along with the outgoing line number of the output destination. Each outgoing module selectively receives only cells addressed to its own outgoing line from the bus and stores them in the outgoing buffer. In operation (3), the outgoing line module reads the cell from the outgoing buffer and outputs it to the outgoing line.

These operations (1), (2), and (
3) will be explained using the incoming line module 101i in FIG. 2 and the outgoing line module 301j in FIG. 3 as examples.

Prior to explaining the operation, contention control using cell priority and bus access numbers will be explained.

Each incoming line module selects the cell with the highest priority among those buffered in each incoming buffer, and requests the right to send that cell to the bus 22.

The following is the content of contention control for cell transmission rights. The internal bus access number sending circuit 125i sequentially sends out to the bus 21 the priority of the cell to be sent and the bus access number corresponding to the input module. In the competition for the right to send a cell, the module that sends the highest priority to the bus 21 and has the largest bus access number among the incoming modules that have requested the right to send a cell wins. In order to make competition for cell transmission rights fair, a bus access number setting circuit inside the incoming line module updates the bus access number every cycle of the frame synchronization signal x (x is a constant).

On the other hand, the outgoing module requests the cell sending right when the internal buffer is congested. The outgoing module does not send out cells even if it obtains the right to send out cells. It has the highest sending priority due to contention and has a bus access number greater than any incoming module. Therefore, when an outgoing module requests the right to send a cell, it always wins.

FIG. 7 shows the timing of processed signals for explaining the operation. Contention control, sending cells to the bus 22, and receiving cells from the bus 22 are performed in synchronization with the frame synchronization signal from the frame synchronization signal generation circuit 24. Signal 71 in FIG. 7 is a frame synchronization signal. signal 73
is an example of a signal on the bus 21, and timing 74 in the signal 73 is the timing at which the incoming module and the outgoing module send out a priority signal indicating the priority of a cell in contention control. Timing 75 in the signal 73 is the timing at which the incoming line module and the outgoing line module send the bus access number to the bus 21 under contention control. signal 7
6 is an example of a signal on the bus 22, and the timing 77 is
At timing 75, the winning incoming line module that sends out the bus access number sends out the output destination outgoing line number and cell from the cell sending circuit.

Operation (1) will be explained. Incoming line 100
When a cell arrives at i, via the incoming I/F 103i,
The signal is input to the cell distribution circuit 105i. Cell distribution 105i
If the priority of the input cell is high, the buffer 106
If i is low, write the cell to buffer 107i. When buffers 106i and 107i do not store cells, they activate empty signals 112i and 115i,
When a cell is stored, it is made inactive and output to the priority detection circuit 122i.

Operation (2) will be explained. The priority detection circuit 122i receives the input empty signal 112i,
115i is inactive, that is, when a cell is buffered in either the input buffer 106i or 107i, the cell presence detection signal 12
Activate 9i. And empty signal 11
2i, 151i, input buffers 106i, 107i
The cell with the highest priority among those buffered in the cell is selected, and a priority signal 131i indicating the priority of that cell is output to the cell transmitting circuit 118i and the selector 124i. The bus access number setting circuit 121i includes a selector 124
Output the bus access number to i.

The bus access number sending circuit 125i switches the selector 124i and outputs the priority signal 131i to the bus 21 when the sending control signal 132i is active at the priority signal sending timing 74. Also, at the bus access number transmission timing 73, the transmission control signal 132i
is active, switch the selector 124i,
The bus access number from the bus access number setting circuit 121i is output to the bus 21.

[0063] Through the above operations, the input line module 101
A priority signal 131i indicating the highest priority among the cells buffered by i and a bus access number are sent out to request the cell sending right.

On the other hand, receiver 127i receives the bus access number on bus 21 at bus access number sending timing 74 in FIG. 4, and outputs it to competition circuit 128i. The competition circuit 128i compares the bus access number received from the receiver 127i bit by bit with the bus access number sent out from the bus access number sending circuit 125i. If there is a match, the winning/remaining determination signal 134i is made active, and if there is a mismatch, the mismatch detection signal 130i is made active. The transmission control circuit 123i outputs a mismatch detection signal 1.
When 30i is active, cell presence detection signal 129i
Regardless of the situation, the transmission control signal 132i is made inactive to stop the bus access number transmission circuit 125i from transmitting the signal. Cells are sent to the bus 22 when the remaining winner determination signal 134i is active.

The sending procedure is as follows. When the priority signal 131i inputted from the priority detection circuit 122i indicates a high priority, the cell transmission circuit 118i activates the readout signal 114i to read the input buffer 106.
Read the cell from i. When the priority indicated by the priority signal 131i is low, the read signal 117i is activated to read the cell from the input buffer 107i. The read cell is analyzed for the output destination line number from the header, and the output destination line number and cell are output at cell sending timing 76 in the order of the output line number and cell.
Output to bus 22.

The outgoing line module receives the outgoing line number on the bus 21 at cell sending timing 77 in FIG. 4 and compares it with its own outgoing line number. If they match, receive the cell following the outgoing number,
The write signal 307i is activated to write a cell to the output buffer 305i through the write cell 307i. The counter 312i counts up every time the write signal 307i becomes active, and counts down every time the read signal 310i becomes active. When the count value of the counter 312i exceeds the upper limit, the counter 312i activates the congestion notification signal 313j.

When the congestion notification signal 313j of the counter 312j is active, the bus access number sending circuit 315i of the outgoing module 301i receives the highest priority signal at the priority signal sending timing 74 in FIG. Bus access number setting circuit 121i
The input bus access number is output to the bus 21. This requests cell transmission rights.

Operation (3) will be explained. When the empty signal 308i of the output buffer 305i is inactive, the output line I/F circuit 311i activates the read signal 310i, reads the cell through the read cell 309i, and outputs it to the output line 300i.

As described above, according to the above embodiment, the incoming line module that is buffering the cell with the highest priority among all the incoming line modules can obtain the right to send cells to the bus 22, and Cells with a high priority can be transferred to the outgoing line before cells with a low priority.

[0070]

[Effects of the Invention] As is clear from the above description, the present invention has the following advantages:
Cells are buffered by priority for each incoming line, and the incoming line module that buffers the cells with the highest priority among all buffered incoming lines obtains the right to send cells to the shared bus. Since cells are sent out, it has the effect that cells with higher priority can always be transferred to the outgoing line before cells with lower priority.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a cell transfer device of the present invention.

[Figure 2] Block diagram showing the configuration of the input line module in Figure 1

[Figure 3] Block diagram showing the configuration of the outgoing line module in Figure 1

[Fig. 4] Timing chart for explaining timing operation in Fig. 1

[Fig. 5] Block diagram showing the configuration of a conventional cell transfer device

[
Figure 6 is a block diagram showing the configuration of the incoming line module in Figure 5.

[Figure 7] Block diagram showing the configuration of the outgoing line module in Figure 5

[FIG. 8] Timing chart for explaining timing operation in FIG. 5

[Explanation of symbols]

21, 22, 23 Bus 24 Frame synchronization signal generation circuit 1001-100m Incoming line 1011-101m Incoming line module 3001-30
0n Outgoing lines 3011 to 301n Outgoing line module 101i Incoming line module 102i Frame synchronization circuit 103i Incoming line I/F circuit 105i Cell distribution circuit 120i Driver 121i Bus access number setting circuit 122i Priority detection circuit 123i Sending control circuit 124i Selector 125i Bus access number sending Circuit 126i Driver 127i Receiver 128i Competition circuit 133i Bus access number sending circuit output 301j
Outgoing module 302j Frame synchronization circuit 303j Receiver 304j Cell selection receiving circuit 305j Outgoing buffer 311j Outgoing I/F circuit 311j 312j Counter 314j Bus access number setting circuit 315j Bus access number sending circuit 316j Driver

Claims (1)

[Claims] 1. Priority-based input buffering means for buffering cells input for each incoming line according to priority; competition means for competing for the right to send cells to a shared bus; and when the right to send cells is obtained, cell sending means for sending cells to the shared bus from the priority input buffering means; output buffering means for selecting and receiving cells destined for itself from the shared bus for each outgoing line; and buffering the cells; cell reading means for outputting cells from the output buffering means to a line, and the competing means buffers a cell with the highest priority among cells buffered on all input lines. A cell transfer device characterized in that an incoming line obtains a cell sending right and the cell sending means sends out a cell with the highest priority among buffered cells when the cell sending means obtains the cell sending right.