JPH04358396A - Delay circuit and semiconductor memory using the same - Google Patents

Abstract

PURPOSE:To increase signal propagation delay time in a semiconductor memory using a delay circuit and without being affected greatly by the changes in the production process conditions and without increasing power consumption and an occupancy area on a semiconductor chip. CONSTITUTION:In the delay circuit cascade-connecting plural stages of ECL inverter 1-n, by using plural kinds of reference voltages VR1-VRn, the signal propagation delay time is increased than a case where one kind of the reference voltage VR1-VRn is used.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit and a semiconductor memory device using the same.

0002

2. Description of the Related Art In response to demands for higher performance, so-called STRAMs (self-timed RAMs), which have built-in input latch circuits, write enable signal automatic generation circuits, etc., have been widely used in recent years. FIG. 5 shows a write enable signal generation circuit used in STRAM.

[0003] This circuit includes inverters 11 to 1n, 21
2n and 31 to 3n are cascade-connected delay circuits. Outputs of inverters 1n, 2n and 3n are supplied to NOR gates 41, 42 and 43, respectively. A clock CLK is supplied to the inverter 11, and this clock CLK is also commonly supplied to NOR gates 41, 42, and 43. On the other hand, the 2-bit pulse width selection signals C1 and C2 are supplied to the decoder 44 and decoded, and one of the NOR gates 41, 42, and 43 is opened. The outputs of the NOR gates 41, 42, and 43 are supplied to the NOR gate 45, and the write enable signal WEX is taken out from the NOR gate 45.

In the above configuration, n is an odd number, and when the NOR gate 41 is opened by the decoder 44, the clock CLK, the output of the inverter 1n, the output of the NOR gate 41, and the output of the NOR gate 45 are as shown in FIG.
) to (D). Write enable signal WE
When the NOR gate 42 is opened in the decoder 44, the width of the negative pulse of X becomes twice that in FIG.
When the Noah gate 43 is opened at step 4, 3 of FIG. 6(D)
Double.

Which of the NOR gates 41 to 43 is opened by the decoder 44 is determined by the characteristics of the memory cell and the clock frequency. In order to obtain the write enable signal WEX with a desired pulse width depending on the characteristics of the memory cell and the clock frequency, it is necessary to provide multiple stages of inverters. This pulse width is determined by (inverter signal propagation delay time) x (number of inverter stages), so to obtain a wide pulse, either lengthen the inverter signal propagation delay time or increase the number of inverter stages. There is a need.

Conventionally, measures have been taken to increase the signal propagation delay time of the inverter, such as reducing the signal current and increasing the additional capacitance.

[0007]

However, all of the above countermeasures have the drawback that the signal propagation delay time varies greatly due to slight unavoidable variations in various conditions of the semiconductor device manufacturing process. Furthermore, increasing the number of inverter stages increases power consumption and occupies an area on a semiconductor chip, which is not preferable.

In view of these problems, it is an object of the present invention to reduce signal propagation delay time without being greatly affected by variations in manufacturing process conditions and without increasing power consumption or occupying area on a semiconductor chip. An object of the present invention is to provide a delay circuit that can increase the delay time and a semiconductor memory device using the delay circuit.

[0009]

[Means for Solving the Problems and Their Effects] FIG. 1 is a diagram showing the principle configuration of a delay circuit according to the first invention.

In the first invention, in the delay circuit in which ECL inverters 1 to n are connected in series, the reference voltage VR1
By using multiple types of ~VRn, the reference voltage VR1~
The signal propagation delay time is increased compared to when one type of VRn is used.

For example, as shown in FIG. 2, this delay circuit is
Inverter 11 and inverter 12 are connected in cascade, and the reference voltage VRA of inverter 11 is lower than the median logic amplitude VRO, as shown in FIG. 4, and the reference voltage VRB of inverter 12 is higher than the median logic amplitude VRO. It has become.

As shown in FIG. 4, when the clock CLK transitions from a high level to a low level, the output voltage VO1 of the inverter 11 and the output voltage VO2 of the inverter 12 become as shown by solid lines in FIGS. 4(B) and 4(C), respectively. Change. That is, when the voltage of the clock CLK decreases to the reference voltage VRA lower than the voltage VRO, the output voltage VO1 of the inverter 11 starts to rise. When this voltage VO1 rises and becomes the reference voltage VRB higher than the voltage VRO,
The output voltage VO2 of the inverter 12 begins to fall.

The signal propagation delay time td2 of this delay circuit is longer than the conventional signal propagation delay time td1. Further, since the signal propagation delay time can be increased without increasing the number of connected inverter stages, there is no increase in power consumption or area occupied on the semiconductor chip. Furthermore, this signal propagation delay time is not significantly affected by variations in semiconductor device manufacturing process conditions.

In the first aspect of the first invention, the reference voltage VR1
~VRn, the reference voltage of one of the even-numbered stages or odd-numbered stages is set to the median value of the logic amplitude of the inverter, VRO.
As described above, the reference voltage of the other inverter of the even-numbered stage or the odd-numbered stage is set to be less than or equal to the median value VRO of the logical amplitude of the inverter.

In this configuration, the signal propagation delay time can be increased in each of the even-stage and odd-stage inverters, so that the above-mentioned effects of the present invention become remarkable.

In the semiconductor memory device of the second invention, the first
The present invention includes a circuit that delays an input signal to generate a write enable signal WE using the delay circuit of the invention, for example, a circuit as shown in FIG.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In this embodiment, in the circuit shown in FIG. 5, each inverter of the delay circuit consisting of inverters 11-1n, 21-2n, and 31-3n is constituted by an ECL circuit. Then, the reference voltage VR of the odd-numbered inverters
A is lower than the median value VRO of the logic amplitude as shown in FIG.
It is higher than O. For example, VRO is -1.3V
, VRA is -1.4V and VRB is -1.2
It is V.

FIG. 2 shows the circuit configuration of inverters 11 and 12 forming part of the delay circuit. The inverter 11 consists of a differential amplifier circuit and an emitter follower type output buffer circuit.

In this differential amplifier circuit, one ends of the resistors R1 and R2 are connected to the power supply line VCC, and one end of the resistors R1 and R2 is connected to the power supply line VCC.
The other ends are connected to the collectors of NPN transistors T1 and T2, respectively.
The emitters of the two transistors are commonly connected to the collector of the NPN transistor T3, and the emitter of the NPN transistor T3 is connected to the power supply line VEE via a resistor R3. The NPN transistor T3 and the resistor R3 constitute a current source, and a constant voltage VCS is supplied to the gate of the NPN transistor T3. Further, a clock CLK is supplied to the gate of the NPN transistor T1, and a reference voltage VRA lower than the voltage VRO is supplied to the gate of the NPN transistor T2. For example, VCC is 0V
, VEE is -5.2V and VCS is -4.0
It is V.

In the output buffer circuit, the collector of the NPN transistor T4 is connected to the power supply line VCC, the base of the NPN transistor T4 is connected to the collector of the NPN transistor T1, and the emitter of the NPN transistor T4 is connected to the resistor. Power supply line VTT via R4
It is connected to the.

The output terminal of the inverter 11 is the emitter of the NPN transistor T4, and if its voltage is VO1, then when the voltage of the clock CLK becomes higher than the reference voltage VRA, the base potential of the NPN transistor T4 decreases and the output is When voltage VO1 becomes low level and the voltage of clock CLK becomes lower than reference voltage VRA, the base potential of NPN transistor T4 rises and output voltage VO1 becomes high level.

The inverter 12 also has the same configuration as the inverter 11, and in FIG. 2, the same components are given the same reference numerals. However, the NPN transistor T2 of the inverter 12
A reference voltage VRB higher than the above voltage VRO is applied to the gate of
is supplied. Further, the emitter voltage of the NPN transistor T4 of the inverter 12 is assumed to be VO2.

FIG. 3 shows a reference voltage source circuit. This circuit includes a reference voltage source circuit 51 that generates a reference voltage VRA,
The reference voltage source circuit 52 generates a reference voltage VRB.

In the reference voltage source circuit 51, one end of the resistor RA is connected to the power supply line VCC, and the other end of the resistor RA is connected to the NPN
The emitter of the NPN transistor T5 is connected to the power supply line VEE via a resistor R5. Further, the collector of the NPN transistor T6 is connected to the power supply line VCC, and the NPN transistor T6 is connected to the power supply line VCC.
The base of the N-type transistor T6 is connected to the collector of the NPN-type transistor T5, and the NPN-type transistor T6
The emitter of the NPN transistor T7 is connected to the collector of the NPN transistor T7, and the emitter of the NPN transistor T7 is connected to the resistor R.
6 to the power supply line VEE. NPN
A constant voltage VCS is commonly supplied to the bases of the NPN type transistor T5 and the NPN type transistor T7, and the NPN type transistor T5 and the resistor R5 and the NPN type transistor T7 and the resistor R6 respectively constitute a current source.

The reference voltage VRA is an NPN transistor T.
If the current taken out from the emitter of 6 and flowing through the resistor R5 is I, the reference voltage VRA is VCC-IRA-VBE
becomes. Here, VBE is the base of the NPN transistor T6.
This is the emitter voltage, which is about 0.8V.

The reference voltage source circuit 52 includes the reference voltage source circuit 5
It has the same configuration as 1. However, in place of the resistor RA of the reference voltage source circuit 51, a resistor RB having a lower resistance value than the resistor RA is used.
is used. The reference voltage VRB is a reference voltage source circuit 52.
The output voltage is taken out from the emitter of the NPN transistor T6 and becomes VCC-IRB-VBE.

Next, the operation of this embodiment configured as described above will be explained.

As shown in FIG. 4, when the clock CLK transitions from a high level to a low level, the output voltage VO1 of the inverter 11 and the output voltage VO2 of the inverter 12 become as shown by solid lines in FIGS. 4(B) and (C), respectively. Change. That is, when the voltage of the clock CLK decreases to the reference voltage VRA lower than the voltage VRO, the output voltage VO1 of the inverter 11 starts to rise. When this voltage VO1 rises and becomes the reference voltage VRB higher than the voltage VRO,
The output voltage VO2 of the inverter 12 begins to fall.

Conventionally, since the reference voltage of the inverters 11 and 12 was the median value VRO of the logic amplitude, the output voltages VO1 and VO2 changed as shown by the dotted line. In contrast, in this embodiment, the reference voltage VRB of the inverters 11 in odd-numbered stages is set higher than the voltage VRO, and the reference voltage VRB of the inverters 12 in even-numbered stages is set higher than the voltage VRO. The signal propagation delay time td2 of the delay circuit in which 12 circuits are connected in cascade is longer than the conventional signal propagation delay time td1. Further, this signal propagation delay time is not affected much by variations in the conditions of the semiconductor device manufacturing process.

In the above embodiment, the case where the reference voltage VRA of the odd-numbered inverters is set lower than the conventional reference voltage VRO, and the reference voltage VRB of the even-numbered stage inverters is set higher than the conventional reference voltage VRO is explained. However, VRA=
The effects of the present invention can also be obtained by setting VRO or VRB=VRO. Furthermore, the reference voltages of the inverters in the odd-numbered stages may not all be equal, and the same applies to the even-numbered stages. Furthermore, even if the delay circuit of the present invention is applied to a part of the configuration of a conventional delay circuit, the effects of the present invention can be obtained.

[0032]

As explained above, in the delay circuit according to the present invention and the semiconductor memory device using the same, multiple types of reference voltages of ECL inverters connected in series in multiple stages are used, so that fluctuations in manufacturing process conditions are avoided. This provides an excellent effect in that the signal propagation delay time can be increased without being greatly affected by the noise and without increasing the power consumption or the area occupied on the semiconductor chip.

In the first aspect of the first invention, the reference voltage of one of the inverters in the even-numbered stages or the odd-numbered stages is set to be equal to or higher than the median of the logic amplitude of the inverter, and the reference voltage of the other inverter in the even-numbered stages or the odd-numbered stages is set to Since the logical amplitude of the inverters is set to be less than the median value, the signal propagation delay time can be increased in each of the even-numbered and odd-numbered stage inverters, resulting in the effect that the signal delay becomes significant.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of a delay circuit according to the present invention.

FIG. 2 is a delay circuit diagram in which inverters are connected in series.

FIG. 3 is a reference voltage source circuit diagram.

FIG. 4 is a waveform diagram showing the operation of the circuit in FIG. 2;

FIG. 5 is a write enable signal generation circuit diagram.

FIG. 6 is a waveform diagram showing the operation of the circuit of FIG. 5;

[Explanation of symbols]

11~1n, 21~2n, 31~3n Inverter 4
1 to 43, 45 NOR gate 44 Decoder 51, 52 Reference voltage source circuit T1 to T7 NPN transistor R1 to R6, RA, RB Resistor CLK Clock C1, C2 Pulse width selection signal VRA, VRB Reference voltage WEX Write enable signal td1, td2 Signal propagation delay time

Claims (3)

[Claims] [Claim 1] In a delay circuit in which multiple stages of ECL inverters (1 to n) are connected in series, a reference voltage (VR1
A delay circuit and a semiconductor memory device using the same, characterized in that by using a plurality of types of reference voltages, the signal propagation delay time is increased compared to when one type of reference voltage is used. 2. The reference voltage of the inverter of one of the even-numbered stages or the odd-numbered stages is set to the median value of the logic amplitude of the inverter (V
RO) or more, and the reference voltage of the other of the inverters in even-numbered stages or odd-numbered stages is set to be less than or equal to the median of the logic amplitudes of the inverters, and a semiconductor memory device using the same. . 3. A semiconductor memory device comprising a circuit for generating a write enable signal (WEX) by delaying an input signal using the delay circuit according to claim 1 or 2.