JPH04358242A - Device and method for translating address - Google Patents

Abstract

PURPOSE:To provide the device and method for translating addresses for improving access speed while suppressing the frequency of exchanging an entry and for effectively utilizing an area to hold the entry at a high-speed buffer for address translation. CONSTITUTION:The entries of logical page numbers and physical page numbers used for converting the addresses generated by a network controller 2, hard disk controller 4 and CPU 5 are respectively held in the prescribed areas of a logical page number part 21 and a physical page number part 23, and the entries are exchanged to the prescribed areas as well.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applied to information processing systems having access means such as a CPU and peripheral devices, and accessed means such as memory and I/O registers.
The present invention relates to an address conversion device and an address conversion method for converting an address generated by a PU or the like into an address actually allocated to a memory or the like.

0002

[Prior Art] In information processing systems, CPUs
For example, if the generated address is 32 bits, an address space of 4 Gbytes can be handled. On the other hand, DRAM that constitutes main memory usually
Due to physical limitations, price limitations, etc., only a few Mbytes to several tens of Mbytes can be implemented.

Therefore, in order to be able to handle an address space larger than that of the main memory, C
Data corresponding to the address space of the PU is stored in a hard disk device, etc., which is a mass storage device, and data is transferred between the hard disk device, etc. and the main memory as appropriate, and access by the CPU is made to the main memory. Many systems called virtual memory are being applied. Here, access to the main memory by the CPU is, more specifically, a virtual address (hereinafter referred to as a logical address) generated by the CPU stored in the main memory and an actual address of the main memory (hereinafter referred to as a logical address). This is done by converting logical addresses into physical addresses based on a page table that shows the correspondence with physical addresses (referred to as physical addresses).

[0004]According to this, regardless of whether data is actually stored in the main memory or in a hard disk drive or the like, and in which physical address area in the main memory the data is stored. Regardless,
Access is possible using virtual addresses. By the way, if the page table is read every time the main memory is accessed, it will take a long time to access. Therefore, for example, "Information Processing Handbook" (edited by Information Processing Society of Japan, May 1989, published by Ohm Publishing) p. 69, TLB (tra
nslation lookaside buffer
) is used, which has a high-speed buffer for address translation.

An example of an information processing system equipped with a conventional address translation device will be described below with reference to FIGS. 3 and 4. As shown in the figure, the information processing system has CP
It is configured by providing a U31, a high-speed address conversion buffer 32, a main memory 33, and a hard disk device 34.

The main memory 33 and the hard disk drive 3
4, data is exchanged in units of a predetermined amount called pages (hereinafter referred to as swapping), and some of the data stored in the hard disk drive 34 is stored in the main memory 33. It is now stored. The main memory 33 also stores a page table 35 that associates logical page numbers forming the upper bits of the logical address with physical page numbers forming the upper bits of the physical address.

The high-speed address conversion buffer 32 holds a part of the page table 35 and converts the logical page number output from the CPU 31 into a physical page number. A logical page number section 41, a comparison section 42, and a physical page number section 43 are provided. The above logical page number section 41
The physical page number section 43 each holds a logical page number or a physical page number in the page table 35 as an entry. The comparison section 42
The logical page number output from the PU 31 is compared with each entry in the logical page number section 41, and the entry in the physical page number section 43 corresponding to the matching entry is outputted to the physical page number section 43 as a physical page number. It is something.

[0008] Note that the logical intra-page offset constituting the lower bits of the logical address output from the CPU 31 is directly combined with the physical page number as an intra-physical page offset, and is output as a physical address. Here, due to hardware constraints, the address translation high-speed buffer 32 has a page table 3.
Since only a portion of 5 is retained, CP
There may be no entry matching the logical page number output from U31. In this case, the necessary portion of the page table 35 is read out and held as a new entry in the address conversion high-speed buffer 32, and then the above conversion is performed. If such an operation is performed, it will take a long time to translate the address, and therefore the access time will increase.

[0009] Therefore, the new entry is maintained in place of the entry that is least frequently referenced within a predetermined time range. That is, CPU3
An access made by No. 1 is usually very likely to be made to an address near the address once accessed. In other words, the less frequently accessed a logical page is, the less likely it is to be accessed again. Therefore, by replacing the least frequently referenced entry with a new entry, the necessary entry exists as often as possible.

0010

[Problems to be Solved by the Invention] By the way, the address translation device described above not only converts logical addresses output from the CPU, but also converts logical addresses output from multiple peripheral controllers such as network controllers and hard disk controllers. It is sometimes used to associate addresses with physical addresses.

[0011] However, in such a case, the entry is frequently replaced and the access speed tends to decrease, and the area for holding the entry in the address translation high-speed buffer is not used effectively. had. That is, for example, the address space handled by a network controller is narrower than the address space handled by a CPU. Therefore, whenever an access is made by the network controller, a predetermined limited range of addresses is output.

[0012] However, if the access frequency itself by these network controllers is low, the corresponding entries are referenced infrequently, and as described above, they are replaced with new entries due to accesses by the CPU, etc. In many cases, such entries are not held in the high-speed address translation buffer. Therefore, every time an access is made by the network controller, entry replacement tends to occur, thus reducing the access speed.

[0013] Furthermore, when data is swapped between the hard disk device and the main memory under the control of the hard disk controller, the correspondence between logical addresses and real addresses is changed, so the page table is rewritten and A new entry is held in the address translation high-speed buffer, and if an entry in the page table before being rewritten is held in the address translation high-speed buffer, that entry is invalidated.

By the way, the above-mentioned swapping is almost never performed consecutively for data at the same logical address. Therefore, entries held in the high-speed address translation buffer by swapping are rarely referenced again by subsequent swapping. However, since entries held through swapping are frequently accessed until a certain amount of time has passed after swapping, they are often held without being replaced with other entries. In other words, the area for holding entries in the high-speed address conversion buffer is not effectively utilized, and as a result, the high-speed address conversion buffer often does not hold entries necessary for access by the CPU, etc. Entries tend to be replaced frequently, resulting in a decrease in access speed.

In view of the above-mentioned points, the present invention provides an address translation device and an address translation device in which the frequency of occurrence of entry replacement is kept low to improve access speed, and an area for holding entries in a high-speed address translation buffer is effectively utilized. Its purpose is to provide an address translation method.

[0016]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first group of addresses generated by a plurality of access means accessing the accessed means, which are actually assigned to the accessed means. an address conversion device that converts addresses into a second group of addresses, an address conversion means that performs address conversion while maintaining at least a part of the correspondence between the first group of addresses and the second group of addresses; If the correspondence between the first group of addresses and the second group of addresses to be accessed is not held in the address translation means, the correspondence is stored in a predetermined area allocated for each access means in the address translation means. The present invention is characterized by comprising a correspondence relationship control means for maintaining the relationship.

[0017]

[Operation] According to the above configuration, the address conversion means
Address translation is performed by retaining at least a part of the correspondence between the group addresses and the second group addresses, and the correspondence control means is configured to maintain at least a part of the correspondence between the addresses of the group and the addresses of the second group. If the correspondence relationship is not held in the address conversion means, the correspondence relationship is held in a predetermined area allocated for each access means in the address conversion means.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of an information processing system including an address translation device according to an embodiment of the present invention. As shown in the figure, the information processing system includes network 1
a network controller 2 connected to the hard disk device 3, a hard disk controller 4 connected to the hard disk device 3, a CPU 5, an arbitration unit 6, a high-speed address conversion buffer 7, an address bus 8, a main memory 12 and an I
A data storage section 11 consisting of a /O register 13 is provided.

The arbitration unit 6 sends a data transfer permission signal to only one of the network controllers 2, etc. in response to a data transfer request signal from the network controller 2, etc., so that addresses are not output simultaneously from the network controllers 2, etc. In addition to outputting the address conversion high-speed buffer 7
In addition, a selection signal for selecting a network controller logical page number section 21a, which will be described later, is output.

Data is exchanged between the main memory 12 and the hard disk drive 3 in units of a predetermined amount called pages.
Hereinafter, this will be referred to as swapping. ) is performed and main memory 1
Part 2 of the data stored in the hard disk device 3 is stored therein. Main memory 1
2 also includes a page table 1 that associates logical page numbers that constitute the upper bits of all logical addresses with physical page numbers that constitute the upper bits of physical addresses.
4 is stored.

[0021] Furthermore, the address conversion high-speed buffer 7 is
It holds logical page numbers and physical page numbers in a corresponding relationship as entries, and converts the logical page numbers output from the CPU 5 etc. into physical page numbers.More specifically, as shown in Figure 2, the logical page numbers A section 21, a comparison section 22, and a physical page number section 23 are provided.

The logical page number section 21 includes a logical page number section 21a for the network controller, a logical page number section 21b for the hard disk controller, and a logical page number section 21b for the CPU.
The physical page number section 23 consists of a physical page number section 23a for a network controller, a physical page number section 23b for a hard disk controller, and a physical page number section 23c for a CPU. .

If the page size is 8K bytes and the address space of the address output from the network controller 2 is 16K bytes, the network controller logical page number section 21a and the network controller physical page number section 23a have 16/16K bytes. 8
It is configured to be able to hold two sets of entries, that is, entries for the entire address space handled by the network controller 2. This entry is set under the control of the CPU 5 at the time of initial setting of the information processing system, and is not changed thereafter.

The hard disk controller logical page number section 21b and the hard disk controller physical page number section 23b are 64/8=8, for example, assuming that the page size is 8K bytes and the maximum transfer amount in one data transfer is 64K bytes. It is configured to be able to hold a set of entries, that is, all entries referenced in one data transfer. This entry is set under the control of the CPU 5 every time data transfer is started.

The CPU logical page number section 21c and the CPU physical page number section 23c are configured to hold a predetermined amount of entries depending on the purpose of the information processing system. It is meant to be retained. Further, if an entry matching the logical page number output from the CPU 5 does not exist in the CPU logical page number section 21c, the necessary portion in the page table 14 is read out, and the CPU logical page number section 21c and CPU A new entry is set in the physical page number field 23c.

The comparing section 22 is composed of a comparing section 22a for a network controller, a comparing section 22b for a hard disk controller, and a comparing section 22c for a CPU.
2a to 22c are selected, the logical page number output from the CPU 5, etc. is compared with each entry in the CPU logical page number section 21c, etc., and the C corresponding to the matching entry is selected.
Entries in the PU physical page number section 23c, etc. are output as physical page numbers to the CPU physical page number section 23c, etc.

Note that the logical intra-page offset that constitutes the lower bits of the logical address output from the CPU 5 and the like is directly combined with the physical page number as an intra-physical page offset, and is output as a physical address. In the above configuration, when the network controller 2 accesses the data storage unit 11, the network controller 2 first outputs a data transfer request signal to the arbitration unit 6.

If the data transfer request signal is not simultaneously output from the CPU 5 or the like, the arbitration unit 6 outputs a data transfer permission signal to the network controller 2, and
A selection signal for selecting the network controller logical page number section 21a, the network controller comparison section 22a, and the network controller physical page number section 23a is output to the address conversion high-speed buffer 7.

When the network controller 2 outputs a logical address, the network controller comparing section 22a compares the logical page number of its upper bits with the entry in the network controller logical page number section 21a. Here, entries for all logical page numbers output from the network controller 2 are set in advance in the network controller logical page number section 21a as described above, and are not replaced by access from the network controller 2. , one of the entries always matches, and high-speed address translation is performed. Further, entries such as the hard disk controller logical page number section 21b and the CPU logical page number section 21c are not replaced.

The network controller physical page number unit 23a outputs the entry corresponding to the matching entry as a physical page number, which is combined with the logical page offset (=physical page offset) and output as a physical address, Main memory 1 of data storage unit 11
2 is accessed. Furthermore, when swapping is performed between the main memory 12 and the hard disk device 3 via the hard disk controller 4, first the CPU 5
sets an entry used for data transfer in the hard disk controller logical page number section 21b and the hard disk controller physical page number section 23b. That is, entries such as the network controller logical page number section 21a and the CPU logical page number section 21c are not replaced with new entries. Moreover, since the new entry replaces the entry used when the previous swapping was performed in the hard disk controller logical page number section 21b and the hard disk controller physical page number section 23b, the area holding the entry is valid. It will be used for

After that, the network controller 2
Similarly to the access by
b and the hard disk controller physical page number section 23b are selected, and the hard disk controller comparing section 22b compares the logical page number output from the hard disk controller 4 with the entry in the hard disk controller logical page number section 21b, The hard disk controller physical page number unit 23b outputs a physical page number, and data transfer is performed by accessing the main memory 12 using a physical address.

Here, even if, for example, interrupt processing is performed by the network controller 2 or the CPU 5 while swapping is being performed, the hard disk controller logical page number section 21b and the hard disk controller physical page number section 23b are Since no entries are replaced, address translations occur quickly until swapping is complete.

On the other hand, when the CPU 5 accesses the data storage section 11, as in the case of access by the network controller 2, the CPU comparison section 22c
The logical page number output from the CPU 5 is compared with the entry in the CPU logical page number section 21c, and the CPU physical page number section 23c outputs the physical page number,
Main memory 12 or I/O register 13 is accessed by physical address.

[0034] Here, if there is no matching entry as a result of the above comparison, the necessary part in the page table 14 is read out, and the CP
It is replaced with the least frequently referenced entry within a predetermined time range in the U logical page number section 21c and the CPU physical page number section 23c. In other words, the access time of the network controller 2 etc. is not increased by replacing entries such as the network controller logical page number section 21a and the hard disk controller logical page number section 21b. In addition, as mentioned above, entry replacement does not occur due to access by the network controller 2 or hard disk controller 4, so entries that are likely to be referenced are always held and high-speed address translation is performed. Become.

[0035] Note that, as described above, referencing and replacing entries is performed using the network controller logical page number section 21a corresponding to the network controller 2, etc.
and physical page number section 23a for network controller
In the case where the conversion is performed only for the above, it is possible to provide each with an independent address space, or the high-speed address conversion buffer 7 can be divided into a plurality of parts and provided separately.

On the other hand, for example, when the CPU 5 accesses, only entry replacement is performed in the CPU logical page number section 21c and the CPU physical page number section 23.
Address translation may also refer to the logical page number section 21b for the hard disk controller, etc., by limiting the number to c. Further, the address conversion high-speed buffer 7 is not limited to the network controller 2, the hard disk controller 4, and the CPU 5, but may also be connected to a plurality of other peripheral controllers.

Furthermore, although an example has been shown in which entries are configured to be set in the network controller logical page number section 21a etc. under the control of the CPU 5, the present invention is not limited to this. You can also do this.

[0038]

[Effects of the Invention] As explained above, according to the present invention,
If the correspondence between the first group of addresses and the second group of addresses to be converted is not held in the address conversion means, the correspondence is stored in a predetermined area allocated to each access means in the address conversion means. By providing a correspondence relationship control means that maintains a new correspondence relationship, even if a new correspondence relationship is maintained due to access by each access means, that new correspondence relationship is necessary for address conversion when accessed by other access means. Since the correspondence relationship is never replaced with a corresponding relationship, the frequency of occurrence of correspondence relationship replacement can be kept low and the access speed can be improved. Moreover, the capacity of the area for holding the correspondence relationship in the address conversion means is limited to This has the advantage that the capacity can be set to the minimum necessary for each case.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing system including an address translation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of the address translation high-speed buffer.

FIG. 3 is a block diagram showing the configuration of an information processing system including a conventional address translation device.

FIG. 4 is a block diagram showing a detailed configuration of the address translation high-speed buffer.

[Explanation of symbols]

1 Network 2 Network controller 3 Hard disk device 4 Hard disk controller 5 CP
U 6 Arbitration unit 7 Address conversion high-speed buffer 8 Address bus 11 Data storage unit 12 Main memory 13 I/O register 14 Page table 21 Logical page number unit 21a Network controller logical page number unit 21b Hard disk controller logical page number unit 21c CPU logical page number section 22 Comparison section 22a Network controller comparison section 22b
Hard disk controller comparison section 22c CP
Comparison section for U 23 Physical page number section 23a Physical page number section for network controller 23b Physical page number section for hard disk controller 23c Physical page number section for CPU

Claims (7)

[Claims] 1. An address translation device for converting a first group of addresses generated by a plurality of access means accessing an accessed means into a second group of addresses actually assigned to the accessed means, comprising: Address translation means that performs address translation while retaining at least part of the correspondence between the first group of addresses and the second group of addresses;
If the correspondence between the first group of addresses and the second group of addresses to be converted is not held in the address conversion means, the correspondence is stored in a predetermined area allocated for each access means in the address conversion means. An address translation device comprising: correspondence control means for maintaining a relationship. 2. The address space of the first group of addresses generated by at least one access means is an address space independent of the address space of the first group of addresses generated by other access means. 2. The address translation device according to claim 1. 3. Address translation according to claim 1, further comprising correspondence initial control means for causing the address translation means to hold the correspondence according to at least one access means at the time of predetermined initial setting. Device. 4. The present invention further comprises correspondence data transfer control means for causing the address conversion means to hold the correspondence according to the data transfer when data transfer is started by the access means. Item 1. Address translation device. 5. An address conversion method for converting a first group of addresses generated by a plurality of access means accessing the accessed means into a second group of addresses actually assigned to the accessed means, comprising: The address translation means is caused to perform address translation while retaining at least a part of the correspondence between the first group of addresses and the second group of addresses, and the first group of addresses to be translated and the second group of addresses are An address conversion method characterized in that, when the correspondence relationship with the addresses of a group is not held in the address conversion means, the correspondence relationship is held in a predetermined area allocated for each access means in the address conversion means. . 6. The address translation method according to claim 5, wherein the correspondence relationship corresponding to at least one access means is held in the address translation means at the time of predetermined initial setting. 7. The address translation method according to claim 5, wherein when data transfer is started by the access means, the address translation means holds the correspondence relationship corresponding to the data transfer.