JPH04357714A - Phase detector - Google Patents

Abstract

PURPOSE:To reduce the time till a repulling-in to a stable point by trying repulling-in against the out of phase of detection in a tentative short time according to a SIN curve characteristic. CONSTITUTION:When a signal from a detector 1 is at an L level, a voltage characteristic selection circuit 25 outputs an applied detection signal at it is and when a signal from a detector 1 is at an H level, the circuit 25 outputs a maximum error voltage according to a maximum error voltage characteristic. Then signals 9omega9-1 from a DQ flip-flop 23 are given to a voltage characteristic selection circuit 25, which outputs signals 9omega8-0 in response to the signal from the detector 1. In this case, when an up-down counter detects that a phase deviation exceding +thetaa deg., -thetab deg. for a prescribed number of times takes place, the repulling-in of the PLL according to a maximum error voltage characteristic is carried out. Furthermore, the PLL is repulled-in according to a SIN curve characteristic against the temporary out of phase of the PLL for a short time.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detector for detecting out-of-phase detection.

0002

2. Description of the Related Art A conventional phase detector will be explained in detail below with reference to FIGS. 4 to 8.

FIG. 4 shows a block diagram of a conventional phase detector. FIG. 5 shows a block diagram of the voltage characteristic selection circuit 25. FIG. 6 shows the SIN curve characteristics of the phase detector. FIG. 7 shows the maximum error voltage characteristics of the phase detection characteristics. FIG. 8 shows an example of the operation of the voltage characteristic selection circuit 25. Hereinafter, a signal with 10 bits and the most significant bit (hereinafter referred to as MSB) being 9 to the least significant bit (hereinafter referred to as LSB) being 0 will be expressed as 10 bits.
It is written as ω9~0.

In FIG. 4, the video signal including the burst supplied to the adder 21 and the output of the NOT circuit 24 are added together and supplied to the D terminal of the DQ flip-flop 22. A clock is supplied to the DQ flip-flop 22 and the DQ flip-flop 23 only during the burst period. The DQ flip-flop 22 delays the signal supplied to the D terminal by one clock, and outputs 10ω9 to 0 to the D terminal of the DQ flip-flop 23, and 1ω9 to the voltage characteristic selection circuit 25 via the B point from the Q terminal. do. The DQ flip-flop 23 further converts the signal supplied to the D terminal into one
The clock is delayed and 9ω9-1 is outputted to the voltage characteristic selection circuit 25, and 10ω9-0 is outputted to the NOT circuit 24 from the Q terminal. The NOT circuit 24 inverts the signal supplied from the DQ flip-flop 23 and outputs it to the adder 21.

The voltage characteristic selection circuit 25 is set to the SIN curve characteristic shown in FIG. 6 when 1ω9 supplied from point B is "L", and to the maximum error voltage characteristic shown in FIG. 7 when it is "H". . The voltage characteristic selection circuit 25 receives the 9ω9 signal supplied from the DQ flip-flop 23.
~1, and outputs 9ω8~0 according to the set characteristics.

In FIG. 5, 1ω9 supplied from point B
is supplied to NAND circuits 51 and 52. 1ω9 supplied from point A is sent to the NAND circuit 52, 1ω8 from point D,
The signal is then supplied to the NAND circuit 51 via the NOT circuit 55. The calculation result of the NAND circuit 51 is sent to the NAND circuit 3.
1 to 37 and 48. The calculation result of the NAND circuit 52 is supplied to the NAND circuits 38, 41-47. A
1ω8-1 supplied from the point are supplied to NAND circuits 48-41, respectively, and NAND circuits 38-3, respectively.
1 to 1ω7 to 1ω0 at point D, respectively. Next, the operation of the phase detector configured as described above will be explained.

In the phase detector shown in FIG. 4, a detection signal is generated at point A, and a signal that is shifted by ±90 degrees from the detection signal at point A is generated at point C. This +90 degrees or -90 degrees changes depending on whether the frequency is higher or lower than 4fsc (fsc: color subcarrier frequency, approximately 3.58 MHz) when locked to the lock phase.

Two's complement data is used for points A and C,
As shown in FIG. 8, the voltage characteristic selection circuit 25 is set to the SIN curve characteristic or the maximum error voltage characteristic by the signal from point B, which is the sign bit (MSB) of point C, and the voltage characteristic is set to the SIN curve characteristic or the maximum error voltage characteristic, and the voltage characteristic is supplied from point A according to the set characteristic. The detected signal is output to point D.

When the voltage characteristic selection circuit 25 in FIG. 5 receives an "L" signal from point B, it outputs 9ω9-1 of the detected signal supplied from point A as it is as 9ω8-0 of point D. do. When a signal of "H" is supplied from point B, the maximum error voltage characteristic becomes the maximum error voltage characteristic, and when 1ω9 from point A is "L", 9ω8 to 0 of point D are "LLHHHHHHHH".
”, and when 1ω9 from point A is “H”, 9ω8 to 0 from point D each become “HHLLLLLLL”.

In the above conventional phase detector, the PLL
In order to speed up the pull-in of
If a phase shift occurs at an angle exceeding θb degrees, the maximum error voltage will be output, and the phase error voltage will take the maximum value. For this reason, the loop gain of the PLL is unnecessarily increased, and extra time is required to bring the PLL back to a stable operating point.

[0011]

[Problems to be Solved by the Invention] In this way, in the conventional device, it is not necessary to re-draw the PLL due to the maximum error voltage characteristics such as loss of lock or disturbance in the non-burst period of the burst lock PLL of the video signal. If it is detected that a phase shift exceeding +θa degrees or -θb degrees has occurred, even if the PLL is temporarily disconnected for a short time, the PLL loop gain will be increased unnecessarily until the PLL is pulled back to a stable point. There was a problem in that it required extra time.

The present invention eliminates the drawbacks of the prior art as described above, and when the PLL is temporarily disconnected for a short period of time, the SIN
The purpose of this is to shorten the time required for re-pulling to a stable point by re-pulling the PLL according to the curve characteristics. [Structure of the invention]

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention includes a detection means for detecting a predetermined amount of PLL dislocation and outputting a detection signal, and a detection means for detecting a predetermined amount of PLL dislocation and outputting a detection signal, and a frequency of the detection signal is set to a predetermined value. means for outputting a characteristic selection signal when higher than

When the characteristic selection signal is supplied, SIN
Provided is a phase detector characterized in that it is equipped with a voltage characteristic selection circuit that is set to a curve characteristic and to a maximum error voltage characteristic when no voltage is supplied, and outputs a detected signal supplied according to the set characteristic. do.

[0015]

[Operation] In the device configured as described above, when the up-down counter detects that a phase shift exceeding a predetermined number of +θa degrees and -θb degrees has occurred, the PLL is re-drawn based on the maximum error voltage characteristic. conduct. As a result, the SI is effective against temporary PLL disconnection that does not require re-pulling the PLL due to the maximum error voltage characteristic.
Since the PLL is re-drawn using the N curve characteristic,
To prevent the loop gain of a PLL from becoming unnecessarily large and to eliminate the need for extra time until re-drawing to a stable point.

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4. In FIG. 1, the same parts as those in FIG. 4 described in the conventional example are given the same numbers, and the explanation will be omitted, and only the different parts will be explained. FIG. 1 shows an embodiment of the present invention, in which a detector 1 is inserted between point B in FIG. 4 and the voltage characteristic selection circuit 25. In FIG. FIG. 2 is a diagram showing this detector 1, and will be described in detail with reference to FIGS. 1 and 2.

The signal supplied from point B is supplied to a NOT circuit 2 and an up/down counter 3. NOT circuit 2 inverts the signal and outputs it to OR circuit 6 and NAND circuit 7.
Output to. The up/down counter 3 counts up when the signal supplied from point B is "H", counts down when it is "L", and outputs the counted 3-bit digital signals to the NAND circuit 4 and NOR circuit 5, respectively. . Further, the up/down counter 3 holds the counted number when the signal supplied from the NAND circuit 8 is "H", and performs a counting operation when the signal is "L".

[0018] The NAND circuit 4 performs an operation, and the operation result is O.
It is supplied to the R circuit 6 and the NAND circuit 11. NOR
Circuit 5 performs calculations, and the calculation results are sent to NAND circuits 7 and N
The signal supplied to the OT circuit 9 and inverted by the NOT circuit 9 is supplied to the NAND circuit 10. OR circuit 6 and N
The calculation result of the AND circuit 7 is supplied to the NOR circuit 8, and the calculated result is supplied to the up/down counter 3. The output of the NAND circuit 10 is supplied to the NAND circuit 11, and the output signal of the NAND circuit 11 is supplied to the NAND circuit 10.
and is output to the voltage characteristic selection circuit 25. The operation of the detector configured in this way will be explained using FIG. 2.

In FIG. 2, the up/down counter 3 counts up when the signal supplied from point B is "H" and counts down when the signal is "L". When the counted value is 7, do not count up from that value,
When the counted value is 0, it does not count down from that value. When the counted value reaches 7, it outputs an "H" signal until it reaches 0, and when it reaches 0, it outputs an "L" signal until it reaches 7 to the voltage characteristic selection circuit 25. The operation of a phase detector including this detector 1 will be explained.

The voltage characteristic selection circuit 25 outputs the supplied detection signal as it is when the signal from the detector 1 is "L", and when the signal is "H" it becomes the maximum error voltage characteristic and outputs the maximum error voltage. The voltage characteristic selection circuit 25 outputs the 9ω9-1 signal supplied from the DQ flip-flop 23 as a 9ω8-0 signal in accordance with the signal from the detector 1. FIG. 3 is a diagram showing an example of the operation of this embodiment. In FIG. 3, when an "H" signal is supplied from the point B supplied to the detector 1, the counter counts up, and when a "L" signal is supplied, the counter counts down.

First, when the value of the up/down counter 3 is 0, the detector 1 outputs an "L" signal to the voltage characteristic selection circuit 25, and the voltage characteristic circuit 25 outputs the supplied detected signal as it is. Next, when more "H" signals are generated than "L" signals from point B and the value of the up/down counter 3 reaches 7, the detector 1 outputs an "H" signal to the voltage characteristic selection circuit 25. The voltage characteristic circuit 25 has the maximum error voltage characteristic and outputs the maximum error voltage regardless of the supplied detection signal. Then, when "L" signals are generated more often than "H" signals from point B and the value of the up/down counter 3 becomes 0, the detector 1 outputs an "L" signal to the voltage characteristic selection circuit 25, and the voltage The characteristic circuit 25 outputs the supplied detection signal as it is.

In this embodiment, when the signal from point B is generated continuously and the detector 1 performs a continuous counting operation,
Since the output signal of the detector 1 does not change while counting, it is also possible to adjust by delaying 9ω9 to 1 from point A using a predetermined time delay device.

[0023]

[Effect of the invention] According to this invention, temporary short-time PL
In response to a deviation of L, the PLL is re-pulled according to the SIN curve characteristic instead of re-pulling the PLL according to the maximum error voltage characteristic, so that the time required for re-pulling to a stable point can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a phase detector according to the present invention.

FIG. 2 is a block diagram of a detector of a phase detector according to the present invention.

FIG. 3 is a diagram showing the operation of the detector according to the present invention.

FIG. 4 is a block diagram of a conventional phase detector.

FIG. 5 is a diagram showing a block diagram of a conventional voltage characteristic selection circuit 25.

FIG. 6 is a diagram showing a SIN curve characteristic of a conventional phase detection characteristic.

FIG. 7 is a diagram showing maximum error voltage characteristics of conventional phase detection characteristics.

FIG. 8 is a diagram showing an example of the operation of a conventional voltage characteristic selection circuit 25.

[Explanation of symbols]

1 Detector 25 Voltage characteristic selection circuit

Claims (1)

[Claims] 1. Detecting means for detecting a predetermined amount of PLL deviation and outputting a detection signal; means for outputting a characteristic selection signal when the frequency of the detection signal is higher than a predetermined value; It is characterized by comprising a voltage characteristic selection circuit which is set to the SIN curve characteristic when supplied, and to the maximum error voltage characteristic when not supplied, and outputs a detected signal supplied according to the set characteristic. Phase detector.