JPH04356813A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To avoid the saturation of a bipolar transistor by connecting an FET, which can impart a prescribed bias to a gate, between the collector electrode of the bipolar transistor and the base electrode. CONSTITUTION:An FET 42 connected between the collector electrode of a bipolar transistor 50 and the base electrode so as to apply the prescribed bias to the gate forms a current path so that the collector potential of the transistor 50 can not be lower than the base potential. Thus, the saturation of the transistor 50 can be avoided without fail. Further, it is preferable for the FET 42 to connect the gate electrode to a constant voltage source, for the FET to be an n-channel type transistor and for the bipolar transistor to be an npn type transistor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device used for arithmetic processing in digital computers and the like.

0002

2. Description of the Related Art One of the decisive factors for increasing the speed of arithmetic processing in digital computers and the like is increasing the speed of carry propagation circuits. Conventionally, in this type of circuit, a carry propagation circuit using a MOS switch as shown in FIG. 2 has been frequently used.

In the figure, 1 is a MOS switch that propagates a carry generated in a lower bit to an upper bit, 2 is a MOS switch for generating carry, and 3 is a MOS switch for suppressing carry. The logical formula for carry generation based on this principle is:

0004

[Math 1]

[0005] That is,

[0006]

[Math 2]

When [0007],

[0008]

[Math 3]

The carry from the lower bit is propagated to the upper bit.

[0010] Also,

[0011]

[Math 4]

0012

[0013]

[Math 5]

##EQU1## A carry "1" is output regardless of the carry of the lower bit. similarly

[0015]

[Math 6]

When 0016

[0017]

[Math 7]

##EQU1## A carry "0" is output regardless of the carry of the lower bit.

[0019] A conventional example applying this principle is disclosed in Japanese Patent Application Laid-open No. 1983-
No. 10032 and Japanese Unexamined Patent Publication No. 59-75343.

Furthermore, when using bipolar transistors in conventional digital circuit technology, there is a need to avoid saturation of the bipolar transistors for high-speed switching processes. Conventionally, so-called Schottky transistors have been used to reduce the saturation state.

[0021]

The conventional method using the Schottky transistor has the disadvantage that it increases the manufacturing process of a semiconductor integrated circuit device and hinders the improvement of the degree of integration.

The object of the present invention is to eliminate such drawbacks and
Another object of the present invention is to provide a semiconductor integrated circuit device in which saturation of bipolar transistors can be reliably avoided.

[0023]

[Means for Solving the Problems] The above object is to provide a semiconductor integrated circuit comprising a bipolar transistor whose base is connected to the output of a logic circuit, whose emitter is connected to a reference potential, and whose collector is connected to an output terminal. This is achieved in the circuit device by connecting a field effect transistor whose gate is given a predetermined bias between the collector electrode and base electrode of the transistor.

[0024]

[Operation] By connecting a field effect transistor whose gate is given a predetermined bias between the collector electrode and base electrode of the bipolar transistor, the collector potential of the bipolar transistor becomes lower than the base potential due to this field effect transistor. A current path is formed to avoid saturation of the bipolar transistor.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a carry propagation circuit according to the present invention. In the figure, 11 to 14 are NMOS, the drain and source of 11 and 12 are node N1, and 12 and 13 are NMOS.
The drain and source of NMO are connected to node N2, and the drains and sources of 13 and 14 are commonly connected to node N3.
The source of S11 is commonly connected to the drain of NMOS20 at node N0. Further, the drain of NMOS 14 is connected to the base of NPN transistor 50 at node N4. The gates of NMOS11-14 are connected to the exclusive OR output of a corresponding set of input signals A and B.

[0026] NMOS2 is connected between the node N0 and the reference potential.
0 and 30 are connected in series, and there is N between the node N1 and the reference potential.
MOS21 and 31 are connected in series, NMOS22 and 32 are connected in series between node N2 and reference potential, NMOS23 and 33 are connected in series between node N3 and reference potential, and NMOS24 and 34 are connected in series between node N4 and reference potential. There is a connection. The carry input signal CIN is connected to the gate of the NMOS 20, and the AND output of the corresponding pair of input signals A and B is connected to the gates of each of the NMOS 21 to 24. In addition, a clock signal is applied to the gates of NMOS30 to 34.

[0027]

[Math. 8]

are commonly connected. The collector of the NPN transistor 50 is connected to one end of the resistor 43, the base to the node N4, and the emitter to a reference potential. resistance 43
The other end is commonly connected to the drains of NMOS 41, 42 and PMOS 40. The sources of NMOS41 and 42 are NP
Connected to the base of the N transistor 50, the NMOS 41
The gate of the clock

[0029]

[Math. 9]

[0030] The gate of NMOS 42 is connected to power supply VCC. The source of PMOS 40 is connected to power supply VCC. In addition, the gate of PMOS40 is a mode signal

0
031]

[Math. 10]

It is connected to [0032]. With the above configuration, the 4-bit carry output COUT is an NPN transistor 50
from the collector. Next, the operation of this circuit will be explained using two typical cases.

(1)

[0034]

[Math. 11]

[0035] At this time, NMOS11 to NMOS14, NMOS
21 to 24 are all off. Therefore, at this time, regardless of the input carry CIN, there is no current bus from node N4 to the reference potential. For this reason, PMO
NPN transistor 50 through S40 and NMOS42
A base current flows through the NPN transistor 50, and the NPN transistor 50 is turned on. Therefore, at this time, the carry output COUT is “
0".

(2)

[0037]

[Math. 12]

At this time, all NMOSs 11 to 14 are on, and all NMOSs 21 to 24 are off. In this state, if the carry input CIN is "0", there is no current bus from the node N4 to the reference potential, as in the case described above, so the NPN transistor 50 is on, and the carry output COUT is "0". On the other hand, CIN is “1”
”, then nodes N4, N3, N2, N1, N
Since a current bus is formed through 0 to the reference potential, N
The base current to PN transistor 50 is bypassed to the reference potential and NPN transistor 50 is turned off. As a result, a load (not shown) is charged through the PMOS 40 and the resistor 43, and the carry output COUT becomes "1".

Note that the NMOS 41 is a clock signal

00
40]

[Math. 13]

When COUT is "1", the resistor 43 is an additional means for increasing the base current to the NPN transistor 50 to speed up turn-on, and the resistor 43 is a level shifting means for adjusting the level of the carry output COUT. Also, P
The gate of MOS40 is the mode signal

[0042]

[Math. 14]

[0043] During normal operation, it is connected to

004
4]

[Math. 15]

[0045] is turned on at “0” level, but when not operating

[0046]

[Math. 16]

[0047] is turned off at the "1" level, cutting off power to the entire circuit.

[0048] What should be noted is the above (1) and (2).
The node N0 through which the carry signal propagates during the operation process explained in
The voltage at ~N4 is the voltage at the base of the NPN transistor 50.
The emitter-to-emitter junction voltage (approximately 0.9V) is suppressed, and the circuit operates at a low amplitude of less than 1/5 of that of conventional carry propagation circuits. Therefore, the charging and discharging time of the parasitic capacitance existing in the carry propagation path is shortened, and high-speed carry propagation can be achieved. Also, as a means of level reproduction, M
Since a bipolar transistor having a larger transfer conductance than the OS is combined, a low amplitude signal at node N4 can be effectively extracted as a large amplitude logic level signal.

Furthermore, since the field effect transistor 42 whose gate is given a predetermined bias is connected between the collector electrode and the base electrode of the bipolar transistor 50, the current is controlled so that the collector potential of the bipolar transistor does not become lower than the base potential. A path is formed to avoid saturation of the bipolar transistor.

[0050]

According to the present invention, saturation of bipolar transistors can be reliably avoided and high-speed switching can be achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a diagram of a carry propagation circuit using a conventional MOS switch.

[Explanation of symbols]

11-14, 20-24, 30-34...NMOS transistor, 41-42...NMOS transistor, 40...P
MOS transistor, 50...NPN transistor.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device comprising a bipolar transistor having a base connected to an output of a logic circuit, an emitter of the bipolar transistor connected to a reference potential, and a collector connected to an output terminal, wherein the collector of the transistor is connected to an output terminal. A semiconductor integrated circuit device characterized in that a field effect transistor whose gate is given a predetermined bias is connected between an electrode and a base electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein the field effect transistor has a gate electrode connected to a constant voltage source. 3. The semiconductor integrated circuit device according to claim 1, wherein the field effect transistor is an n-channel transistor, and the bipolar transistor is an npn transistor. . 4. The semiconductor integrated circuit device according to claim 1, wherein the field effect transistor has a current path formed such that a collector potential is maintained at a higher potential than a base potential. Semiconductor integrated circuit device.