JPH04355271A - Digital signal processor - Google Patents

Abstract

PURPOSE:To reduce the number of crystal oscillators for generating a reference clock frequency as much as possible in a digital signal processor obtaining a digital signal by sampling an input signal at a prescribed sampling frequency, converting the digital signal into a recording signal while using a channel clock having a prescribed frequency as a reference and outputting it to a magnetic head. CONSTITUTION:By generating the channel clock based on reference clocks 21 and 22 for generating a sampling frequency, the channel clock frequency can be generated without providing the crystal oscillator dedicated to the channel clock. That is, by changing over a switching circuit 32 corresponding to an input audio signal S1, three kinds of sampling clocks FS can be generated and converted into an audio signal 11 in a frequency division circuit 23.

Description

[Detailed description of the invention]

0001

[Table of Contents] The present invention will be explained in the following order. Industrial applications Conventional technology Problems that the invention aims to solve Means to solve problems (Figure 1) Effect (Figure 1) Examples (Figures 1 to 3) Effect of the invention

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device, and is suitable for application to, for example, a magnetic recording and reproducing device for recording and reproducing digital audio signals.

0003

2. Description of the Related Art Conventionally, among magnetic recording and reproducing devices, there is a digital audio tape recorder (hereinafter referred to as DAT) which can record and reproduce digital audio signals using a rotating drum.

[0004] In such a DAT, an audio signal consisting of an analog signal can be converted into a digital signal and recorded and reproduced, so deterioration in sound quality can be effectively avoided.
Audio signals can be recorded with high density.

[0005]

[Problem to be solved by the invention] By the way, this type of DA
In T, digital I/O is used in the conversion system that converts analog audio signals to digital audio signals.
O, 48 [kHz], 32 [kHz] as a sampling frequency system for movable digital filters, etc.
, 44.1 [kHz].

[0006] Here, 48 [kHz] and 32 [kHz]
] In the sampling frequency system, the master clock frequency is 24.576 [MHz], which is the least common multiple of 256 times the frequency of each frequency and twice or more of each frequency.

[0007] Therefore, 48 [kHz] and 32 [kHz]
] In the sampling frequency system of 24.576 [MHz
] The master clock frequency is shared.

In addition, in the sampling frequency system of 44.1 [kHz], the master clock frequency is 22.5792 [MHz], which is twice the frequency that is 256 times that frequency.

Furthermore, the channel clock frequency used when converting the audio data converted into a digital signal into a recording signal and recording it on the magnetic tape via the first and second magnetic heads provided on the rotating drum. As a system, if the diameter of the rotating drum is 30 [mm], 9.40
8 [MHz], and a frequency that is an integral multiple of the channel clock frequency is required as the master clock frequency.

[0010] Therefore, in the DAT, 24.57
Master clock frequency of 6 [MHz], 22.57
Master clock frequency of 92 [MHz] and 9.
Three crystal oscillators were required, each generating a master clock frequency of 408 MHz.

By the way, in this type of DAT, since it is thought that the usability can be further improved by making it smaller, it is necessary to simplify the structure as much as possible.

The present invention has been made in consideration of the above points, and proposes a digital signal processing device that can further simplify the configuration by minimizing the number of crystal oscillators for generating the master clock frequency. This is what I am trying to do.

[0013]

[Means for Solving the Problems] In order to solve the problems, in the present invention, an input signal S1 is sampled at a predetermined sampling frequency fs to obtain a digital signal D1, and a channel clock FCH having a predetermined frequency fc is obtained. A digital signal processing device 1 that converts a digital signal D1 into a recording signal SR using a reference and outputs it to a magnetic head 19.
0, the channel clock FCH is generated based on the reference clocks FS1 and FS2 for generating the sampling frequency fs.

[0014]

[Operation] By selecting the diameter D of the rotary drum 19 in accordance with the channel clock frequency fc that can be obtained from the reference clocks FS1 and FS2 for generating the sampling frequency, the sampling frequency f
A channel clock FCH can be generated based on the reference clocks FS1 and FS2 for generating s,
As a result, the channel clock frequency fc can be generated without providing a crystal oscillator exclusively for the channel clock. Therefore, since the crystal oscillator is not provided, the configuration of the digital signal processing device 10 can be simplified.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 10 generally indicates a DAT, in which an input audio signal S1 consisting of an analog signal is converted into digital audio data DA1 in an audio signal conversion circuit 11 and sent to an error detection and correction circuit 13.

The error detection and correction circuit 13 sequentially loads the digital audio signals stored in the memory 14 at a predetermined timing and generates a parity code consisting of an inner code and an outer code for error detection and correction in units of blocks. The parity code is stored in the memory 14.

As a result, the digital audio signal DA1 input via the audio signal conversion circuit 11 has the following characteristics:
Generate a parity code in the interleave period and store it in memory 1.
4.

On the other hand, during reproduction, the error detection and correction circuit 1
3 sequentially loads the reproduced data stored in the memory 14 via the modulation circuit 15, performs error detection and error correction on the reproduced data, and stores the resultant data in the memory 14.

[0020] Accordingly, the digital audio signals recorded while being separated by the interleaving period are stored in the memory 14 after error correction processing is performed.

The modulation circuit 15 sequentially reads out the digital audio signal DA2 stored in the memory 14 together with the parity code in a predetermined order and modulates it by 8-10.

Further, the modulation circuit 15 converts the modulation signal into serial data, adds a pilot signal for ATF tracking control, a synchronization signal, etc. to generate a recording signal SR, and performs recording/reproduction amplification of the recording signal SR. By outputting to the magnetic heads 20A and 20B via the circuit 17,
Digital audio signals can be sequentially recorded on the magnetic tape 18.

Furthermore, during reproduction, the modulation circuit 15 receives the reproduction signal SP.
After 10-8 demodulation, the resulting reproduced data D
A5 are sequentially stored in a predetermined area of the memory 14.

After the reproduced data DA5 thus demodulated is subjected to error correction in the error detection and correction circuit 13 (DA6),
The audio signal is analog-converted in the audio signal conversion circuit 11 and thus recorded on the magnetic tape 18, and is output as a reproduced audio signal S2.

In the audio signal conversion circuit 11, the input audio signal S1 is sampled using a sampling clock FS obtained by frequency-dividing the master clock FS1 or FS2 output from the reference signal generation circuit 21 or 22. ing.

The frequency f of this sampling clock FS
s is 48 [kHz], 32 [kHz] and 4
4.1 [kHz] are required, and master clocks FS1 and FS are required to generate the frequency fs.
As the second frequency, the types shown in FIG. 2 can be considered.

[0027] As a result, 48 [kHz] and 32 [k
The master clock frequency for generating Hz] is 2
It is possible to share a frequency that is an integral multiple of 4.576 [MHz].

[0028] Also, the master clock frequency for generating 44.1 [kHz] is 11.2896 [MHz].
] It is possible to use a frequency that is an integral multiple of 2 or more.

Therefore, the frequency dividing circuit 23 switches the switching circuit 32 to the input terminal a or b side in accordance with the input audio signal S1, so that the frequency dividing circuit 23 changes the frequency from the master clock FS1 or FS2 to 48 [kHz]. , 32
[kHz] or 44.1 [kHz] sampling clock FS is generated, and this is sent to the audio signal conversion circuit 1.
1.

On the other hand, the modulation circuit 15 uses the master clock F output from the reference signal generation circuit 21 or 22.
S1 (24.576 [MHz]) or FS2 (22.5
792 [MHz]) switching circuit 31 and frequency dividing circuit 28
The recording signal SR is output or the reproduction signal SP is input at a transmission speed corresponding to the diameter D of the rotary drum 19 with reference to the channel clock FCH which is frequency-divided through the rotary drum 19.

That is, in the recording format of the DAT, the first and second magnetic heads 20A and 20B
The rotating drum 19 carrying the magnetic head rotates at 2000 [rpm], so that the recording tracks by the first and second magnetic heads become 200/3 tracks per second.

Furthermore, since the rotational speed is constant at 2000 [rpm], if the frequency of the channel clock FCH is fc [MHz], the diameter D of the rotating drum is
[mm] is the following formula,

[Math 1] Represented by

Therefore, since the diameter D of the rotating drum 19 and the channel clock frequency fc are proportional, the master clock FS1 (24.576 [MHz]) or FS2 (
By selecting the diameter D of the rotary drum 19 that corresponds to the channel clock frequency fc that can be obtained from 22.5792 [MHz]), the crystal oscillator for the channel clock FCH can be changed to the crystal oscillator 25 of the sampling frequency system. 2
6 can be substituted.

That is, 48 [kHz] and 32 [k
The frequency fM [MHz] of the master clock FS1 of the sampling frequency system consisting of

[Formula 2] The channel clock frequency fc [MHz] that can be generated from this frequency fM is expressed by the following formula, where m and n are natural numbers, respectively.

[Math 3] becomes.

Therefore, the diameter D of the rotating drum 19 in this case
1 [mm] is the following formula,

[Math 4] becomes.

Similarly, the diameter D2 [mm] of the rotating drum 19 obtained based on the master clock FS2 of the sampling frequency system of 44.1 [kHz] is calculated by dividing m by 2.
The following formula, where n is a natural number,

[Math 5] becomes.

Therefore, the master clock frequency can be generated using the crystal fundamental wave by equations (4) and (5): 24.576
[MHz] and 22.5792 [MHz], and if the diameter D [mm] of the rotating drum 19 is selected in the range of 15 [mm] or more, the values shown in FIG. 4 will be obtained.

For example, the master clock frequency is 24.57
The diameter D of the rotary drum 19 corresponding to the channel clock frequency 4.9152 [MHz] obtained by dividing 6 [MHz] by 1/5 is 15.7 [mm].

In this way, the diameter of the rotary drum 19 corresponding to the channel clock frequency fc that can be generated based on the master clocks FS1 and FS2 is selected, and the CPU 29 selects the frequency division ratio corresponding to the rotary drum diameter D. The channel clock FCH can be obtained by specifying it by the control signal CON from the channel clock FCH.

Therefore, the channel clock frequency fc can be obtained without providing a dedicated crystal oscillator.

According to the above configuration, the master clocks FS1 and FS2 for generating the sampling frequency fs
By selecting the diameter D of the rotary drum 19 in accordance with the channel clock frequency fc that can be obtained from FCH can be generated, thereby making it possible to generate the channel clock frequency fc without providing a crystal oscillator dedicated to the channel clock.

[0042] Thus, it is only necessary to provide a crystal oscillator for generating the sampling frequency fs, and the DAT
10 can be further simplified.

In the above-described embodiment, a case was described in which the diameter D of the rotating drum 19 was selected as shown in FIG. 3, but the present invention is not limited to this.
) Various types can be used as long as they satisfy the formula.

Furthermore, in the above embodiment, a case was described in which two crystal oscillation elements were used to generate the master clock frequency, but the present invention is not limited to this, and various numbers of crystal oscillation elements may be used as necessary. applicable.

Further, in the above embodiment, the case where the rotation speed of the rotary drum 9 was set to 2000 [rpm] was described, but the present invention is not limited to this and can be applied to various rotation speeds. In this case, the channel clock frequency fc may be selected depending on the rotational speed.

Furthermore, in the above-described embodiments, the case where audio signals are recorded and reproduced has been described, but the present invention is not limited to this, and can be applied to an external storage device of an arithmetic processing unit, etc., to record and reproduce various data. It's okay.

Furthermore, the present invention can be widely applied not only to magnetic recording and reproducing apparatuses but also to recording-only digital audio tape recorders and digital signal processing apparatuses that record or reproduce various data other than audio signals.

[0048]

As described above, according to the present invention, based on the reference clock for generating the sampling frequency,
By generating a channel clock, it is possible to realize a digital signal processing device that can generate a channel clock frequency without providing a crystal oscillation element exclusively for the channel clock.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a digital signal processing device according to the present invention.

FIG. 2 is a chart showing the relationship between sampling frequency and master clock.

FIG. 3 is a chart showing the relationship between the rotating drum diameter and the channel clock.

[Explanation of symbols]

10...DAT, 11...Audio signal conversion circuit, 1
5... Modulation circuit, 18... Magnetic tape, 19... Rotating drum, 20A, 20B... Magnetic head, 25, 26...
Crystal oscillator, FS1, FS2...Master clock, 2
3, 28... Frequency dividing circuit.

Claims (1)

[Claims] 1. A digital signal obtained by sampling an input signal at a predetermined sampling frequency, converting the digital signal into a recording signal based on a channel clock having a predetermined frequency, and outputting the digital signal to a magnetic head. A digital signal processing device characterized in that the processing device generates the channel clock based on a reference clock for generating the sampling frequency.