JPH04354389A - Ferroelectric substance memory cell - Google Patents

Abstract

PURPOSE: To provide a ferroelectric memory cell having structure capable of extremely reducing an area per cell by using a ferroelectric substance and optimum to large capacity and high integration. CONSTITUTION: In the ferroelectric memory cell, a buffer film 32 is formed on an insulating substrate 31 and a cell plate electrode 33, a ferroelectric film 34 and a capacitor electrode 35 are successively formed on the film 32. A transistor(TR) is formed directly on the surface of the electrode 35, gaps among layers are filled with an inter-layer insulating film 41, a contact hole 42 is opened so as to extrude the drain electrode 40 of the TR, and a bit line electrode 43 is formed. Namely the element separation area is constituted of the insulator, a conventional hole for connecting the capacitor electrode 35 to the source electrode 33 is made unnecessary, the TR is formed in the lamination direction and the cell area per bit in the ferroelectric memory cell is extremely reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell, and more particularly to a ferroelectric memory cell suitable for high integration of memory cells using ferroelectric materials.

0002

2. Description of the Related Art Generally, for example, DRAM (Dynami
One memory cell of a volatile memory cell such as a random access memory (Random Access Memory) is each composed of one transistor and one capacitor.

FIG. 11 shows the structure of a DRAM cell composed of one transistor and one capacitor.

In the DRAM shown in FIG. 11, one end of the current path of transistor 1 is connected to bit line BL, and the other end of the current path is connected to one end of capacitor 2. A control electrode of the transistor 1 is connected to a word line WL.

Next, the operation of this DRAM will be explained. First, in a write operation, a potential is applied to the word line WL to turn on the transistor 1, a potential corresponding to the I/O is transferred from the bit line BL to the node N, and information is stored in the capacitor 2 as a charge.

[0006] Furthermore, the write operation is performed on the bit line BL.
After precharging, a potential is applied to the word line WL, transistor 1 is turned on, and the charge is transferred to the bit line BL.
parasitic capacitance CB and memory cell capacitance CS
This is done by sensing the change in bit line potential with a sense amplifier (not shown).

[0007] In a DRAM that reads out such charge, the charge level is determined by the ratio of the bit line capacitance to the capacitor capacitance, and in this case, the charge is small and therefore susceptible to noise. .

Furthermore, as DRAMs become more dense and large in capacity, the area of capacitors in memory cells must be reduced due to chip area limitations, and the capacitance of capacitors that does not cause noise margins and soft errors must be reduced. The lower limit of is determined.

Next, increasing the capacitance of a capacitor will be described.

That is, as a first means of securing the capacitance of a capacitor, the capacitor oxide film is made thinner. If a commonly used silicon oxide thin film is to be used in, for example, 16 megabit or 64 megabit integrated circuit devices, a new thin film technology for forming a thin film of approximately 80 angstroms or less is required.

As a second means, the area of the capacitor can be increased by using, for example, a trench structure for forming the capacitor. However, the trench structure requires complicated processing in the manufacturing process.

As a third means, Ramtron has developed a DRAM capacitor as disclosed in Japanese Patent Publication No. 1-278063 using a ferroelectric film made of a material with a higher dielectric constant than the silicon oxide film. Proposed.

The structure of such a conventional memory cell is shown in FIG.
Shown in 2.

In this structure, first, a P-type semiconductor substrate 1
1 includes a source 12 and a drain 13 consisting of an n+ diffusion region.
is formed. After forming an interlayer insulating layer 14 on the P-type semiconductor substrate 11, contact holes 15 are formed to connect the source 12 and drain 13 to the outside.
, 16 are opened, a capacitor electrode 17 and a bit line electrode 18 made of a conductive material are formed, and then a ferroelectric film 19 and a capacitor electrode 20 are formed on the capacitor electrode 17.
form. Further, a gate electrode 9 is formed between the drain 13 and the source 12.

A top view of an example of a pattern of a memory cell array using such conventional memory cells is shown in FIG. 13 and FIGS. 14(a) and 14(b) and will be described. Further, FIG. 14(a) is a cross-sectional view taken along a-a′ shown in FIG.
FIG. 14(b) is a sectional view taken along line bb' shown in FIG. 13.

In this structure, an SDG region 21 consisting of a diffusion region is formed on a semiconductor substrate, and a gate electrode 22 for control is formed. Then, a predetermined SDG area 21
A capacitor electrode 23, a ferroelectric film 24, and a cell plate electrode 25 are formed thereon. Furthermore, a wiring electrode 26 is formed on the other SDG region 21. A bit line 27 is formed within the interlayer insulating film.

Here, the part 2 surrounded by the dashed line in FIG.
8 indicates an area for one bit.

[0018]

However, the cell array using the memory cells of the conventional structure described above has the following problems.

First, to configure one bit, one cell plate contact hole, one bit line, and a
Two cell plate lines are required. Second, every two bits have one shared drain electrode. Third
The source electrode of the capacitor and the bit line must be spaced apart from each other by a predetermined distance in order to electrically isolate them. Fourthly, a cell in a region corresponding to one bit and an adjacent transistor region must be separated from each other by a predetermined distance in order to electrically isolate them. Fifth, since wiring is frequently used, the spacing between wirings and wiring processing techniques to ensure insulation become a problem.

As described above, in the conventional memory cell array structure, the area of the cell is determined by element isolation and processing technology, and in order to increase capacity and increase integration, further element isolation technology and processing precision are required. We have to try to improve, which is difficult.

[0021] Accordingly, an object of the present invention is to provide a ferroelectric memory that uses ferroelectric material to minimize the area per cell and has a structure that is optimal for large capacity and high integration. .

[0022]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a capacitor section using a ferroelectric material formed on an insulating substrate for storing information, and a capacitor section using a ferroelectric material that stores information for the capacitor section. In a ferroelectric memory cell configured with a transistor section for writing and reading, the capacitor section has a cell plate electrode of the capacitor section formed on a buffer film formed on the insulating substrate;
The transistor section includes a ferroelectric film formed on the cell plate electrode and a capacitor electrode, and one end of the current path of the transistor section is formed directly on the capacitor electrode, and the other end of the current path is formed directly on the capacitor electrode. A ferroelectric memory cell can be provided whose end is configured to connect to a bit line electrode via at least one contact hole filled with a conductor.

Further, when the ferroelectric memory cells are arranged in an array, the control gate electrode and the conductive layer of the transistor are parallel to each other and connected to a plurality of ferroelectric memory cells. Cell arrays can be provided.

Furthermore, it is possible to provide a ferroelectric memory cell array in which the control gate electrodes and conductive layers of the transistors are arranged in an array so as to be parallel to and orthogonal to the other ends of the current paths of the transistors.

[0025]

[Operation] According to the ferroelectric memory configured as above,
There is no need for a contact connection between the transistor source and capacitor electrode, each electrode part of the transistor is not exposed to the substrate surface, and since the capacitor electrode and bit line electrode near the source are formed separately, there is only one type of upper electrode. This can be realized with a number of electrodes, and the number of wiring lines for driving the memory cells can be reduced.

[0026]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

That is, as a first embodiment, FIG. 1(a),
2(b) and 2 show the cell structure of the ferroelectric memory according to the present invention.

First, FIG. 1(a) is a plan view of a ferroelectric memory cell viewed from above, and FIG. 1(b) is a top view of the ferroelectric memory cell.
It is a cross-sectional view in the A′ direction, and FIG. 2 is a cross-sectional view taken along the line B-B′ in FIG.
FIG.

In this ferroelectric memory cell, a buffer film 32 is formed on an insulating substrate 31 made of sapphire or the like, and a cell plate electrode 33 made of platinum or the like is further formed. Then, on the cell plate electrode 33, for example, PZT
A ferroelectric film 34 is formed, and a capacitor electrode 35 made of, for example, aluminum is formed on the ferroelectric film 34 .

Next, an n+ diffusion region that will become the source 36 of the transistor is formed on the capacitor electrode 35, and a p+ diffusion region 37 is formed directly above it. A gate electrode 38 and a conductor layer 39 made of polysilicon or the like are formed facing each other with the p+ diffusion region 37 in between, and a drain electrode 40 is further formed on the p+ diffusion region 37.
is formed.

Further, an interlayer insulating film 41 is filled to surround such a memory cell, and a contact hole 42 is opened so that the drain electrode 40 is exposed from the surface of the interlayer insulating film 41. A bit line electrode (wiring) 43 is formed by filling the contact hole 42 with a conductor so as to be connected to the drain electrode 40.

In a ferroelectric memory cell having such a structure, the orientation of the ferroelectric film 34 sandwiched between the capacitor electrode 35 and the cell plate electrode 33 is influenced by the crystal orientation of the cell plate electrode 33. However, during formation, a buffer film 32 is formed on the insulating substrate 31 so that the crystal orientation can be easily controlled.

In this cell structure, by forming the source electrode 33 of the transistor directly on the capacitor electrode 35, there is no need for a contact hole for connecting the capacitor electrode 35 and the source electrode 33, which was conventionally provided. The cell area can be reduced (Figure 1 (
a), A-A′ direction).

Furthermore, by forming the transistor in the vertical direction, the length in the width (A-A') direction can be shortened. Furthermore, in the cell array of the present invention, since the element isolation region is made of an insulator, there is no need to consider the punch-through breakdown voltage between each element.

On the other hand, in such a structure, the channel
Although the influence of the threshold value fluctuation of the transistor due to the carriers coming out from the portion is likely to occur, this is prevented by allowing the carriers to escape into the conductor by the conductor 40.

Further, since the bit line electrode 43 is connected to the drain electrode 40 through the contact hole 42, the bit line electrode is on the top layer, and the number of wiring lines per bit on the same layer can be reduced. Furthermore, since there is only one contact hole connection, the cell area per bit can be reduced.

Next, FIG. 3 and FIGS. 4(a) and 4(b) show the second cell array constructed using the cells of the present invention described above.
This is an example. Figure 3 is a plan view of the cell array, Figure 4(a)
4 is a cross-sectional view of the cell array in FIG. 3 taken along the line C-C'. Figure 4(b)
) is a cross-sectional view of the cell array in FIG. 3 taken along line DD'. Here, the members constituting the cell array of the first embodiment are shown in FIG.
and the members constituting the cell in FIG. Further, in the cell array of the second embodiment, as shown in the figure, the cell plate electrodes are commonly connected in the vertical direction, and the ferroelectric material is separated for each cell.

Each cell is provided with a control gate 45 and a conductive gate 46 which are commonly connected.

Next, as a third embodiment, FIGS. 5(a) and 5(b)
) and FIG. 6 are diagrams showing a cell array constructed using the cells of the present invention. FIG. 5(a) is a plan view of the cell array;
FIG. 5(b) is a cross-sectional view of the cell array in the EE' direction, and FIG. 6 is a cross-sectional view of the cell array of FIG. 5(a) in the F-F' direction. Here, the members constituting the cell array of the second embodiment are given the same reference numerals as in the second embodiment, and a description thereof will be omitted. In this example, cell plates 33 are commonly connected to any size of cell array, and ferroelectric materials 34 are separated for each cell.

Next, as a fourth embodiment, FIGS. 7 and 8 (a
) and (b) show cell arrays constructed using cells of the present invention. That is, FIG. 7 is a plan view of the cell array, and FIG.
8(a) is a cross-sectional view of the cell array in FIG. 7 in the GG' direction, and FIG. 8(b) is a cross-sectional view of the cell array in FIG. 7 in the H-H' direction.

In this fourth embodiment, the cell plate 33 is similar to the configuration example shown in FIG. 3, and the cell plates of the cells provided on both sides of the cell plate 33 with the wiring interposed therebetween are commonly connected in the thickness direction. . Here, the members constituting the cell array of the fourth embodiment are given the same reference numerals as in the second embodiment, and the description thereof will be omitted.

In this fourth embodiment, all the ferroelectric materials 34 are connected in common and are not separated by patterns.

Next, as a fifth embodiment, FIGS. 9 and 10 (
a) and (b) are cell arrays constructed using cells of the present invention. That is, FIG. 9 is a plan view of the cell array, FIG. 10(a) is a cross-sectional view of the cell array in FIG. 9 in the II' direction, and FIG. 10(b) is a cross-sectional view of the cell array in FIG. 9 in the J-J' direction. It is a diagram. Here, the members constituting the cell array of the fifth embodiment are given the same reference numerals as in the second embodiment, and the description thereof will be omitted.

In this fifth embodiment, the cell plate 33,
This is an example in which all or any size of the ferroelectric films 34 are commonly connected.

From the above detailed description, the cell of the present invention has the following features:
First, by adopting a vertical structure in which elements are formed in the vertical direction, contacts between the source and capacitor electrodes are not required, and the number of contacts per cell is reduced to one.

[0046] Since it is formed on an insulating substrate, SDG
There is no need to consider breakdown voltage between regions, and high precision element isolation technology is unnecessary.

Furthermore, since the capacitor electrode and the bit line electrode on the transistor side are formed separately, only one type of upper layer electrode is required, and the number of wiring lines can be reduced.

[0048]

As described above, the present invention can provide a ferroelectric memory that uses ferroelectric material to minimize the area per cell and has a structure that is optimal for increasing capacity and increasing integration.

[Brief explanation of the drawing]

1] FIG. 1(a) is a top plan view of a ferroelectric memory cell according to a first embodiment of the present invention, and FIG. 1(b) is a line segment A-A in FIG. 1(a). It is a sectional view between '.

FIG. 2 is a cross-sectional view of the ferroelectric memory cell shown in FIG. 1(a) along line BB'.

FIG. 3 is a plan view of a ferroelectric memory cell array according to a second embodiment of the present invention.

4] FIG. 4(a) is a cross-sectional view of the ferroelectric memory cell array in FIG. 3 in the CC′ direction, and FIG.
-D' direction sectional view.

FIG. 5(a) is a plan view of a ferroelectric memory cell array according to a third embodiment of the present invention, and FIG. 5(b) is a plan view of a ferroelectric memory cell array according to a third embodiment of the present invention;
FIG.

FIG. 6 is a cross-sectional view of the ferroelectric memory cell array of FIG. 5(a) in the FF' direction.

FIG. 7 is a plan view of a ferroelectric memory cell according to a fourth embodiment of the present invention.

8] FIG. 8(a) is a cross-sectional view of the ferroelectric memory cell array in FIG. 7 in the GG′ direction, and FIG. 8(b) is a
-H' direction sectional view.

FIG. 9 is a plan view of a ferroelectric memory cell according to a fifth embodiment of the present invention.

10(a) is a cross-sectional view of the ferroelectric memory cell array of FIG. 9 in the II' direction, and FIG. 10(b) is a cross-sectional view of the ferroelectric memory cell array of FIG. 9 in the J-J' direction.

FIG. 11 is a circuit diagram showing the configuration of a conventional DRAM cell.

FIG. 12 is a structural diagram showing the structure of a conventional memory cell.

FIG. 13 is a plan view of a memory cell array using conventional memory cells.

14(a) is a cross-sectional view of the conventional ferroelectric memory cell array of FIG. 13 in the a-a'direction; FIG.
b) is a sectional view taken along the line bb' in FIG. 13;

[Explanation of symbols]

31... Insulator substrate, 32... Buffer film, 33... Cell plate electrode, 34... Ferroelectric film, 35... Capacitor electrode, 36... Source electrode, 37... P+ diffusion region, 38... Gate electrode, 39... Conductor layer, 40...Drain electrode, 41...
Interlayer insulating film, 42... contact hole, 43... bit line electrode, 45... control gate, 46... conductive gate.

Claims (4)

[Claims] 1. A ferroelectric material comprising a capacitor section formed using a ferroelectric material on an insulating substrate and storing information, and a transistor section for writing and reading information to and from the capacitor section. In the memory cell, the capacitor section includes a cell plate electrode of the capacitor section formed on a buffer film formed on the insulating substrate, a ferroelectric film formed on the cell plate electrode, a capacitor electrode, and a cell plate electrode of the capacitor section. In the transistor section, one end of the current path of the transistor section is formed directly on the capacitor electrode, and the other end of the current path is formed through at least one contact hole filled with a conductor. A ferroelectric memory cell configured to be connected to a bit line electrode. 2. The ferroelectric device according to claim 1, wherein a control gate electrode of the transistor is formed in one of the channel regions sandwiched between the two current paths, and a conductor layer is formed in the other region. body memory cells. 3. The ferroelectric memory cells are arranged in an array, and the control gate electrodes and conductive layers of the transistors are parallel to each other and connected to the plurality of ferroelectric memory cells. 2. The ferroelectric memory cell according to item 2. 4. A control gate electrode and a conductor layer of the transistor, and a conductor layer at the other end of the current path of the transistor.
4. The ferroelectric memory cell according to claim 3, wherein the ferroelectric memory cell is arranged in an array so as to be perpendicular to the bit lines connected through two contact holes.