JPH04354164A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a field effect transistor which is suitable for high-speed operation or room-temperature operation by modulating the speed of carriers. CONSTITUTION:An n-type AlGaAs layer 3 is formed on a GaAs substrate 1 so that a heterojunction interface can be obtained and an insulating area 2 is formed so as to divide the first carrier running layer into sections at a position near the heterojunction interface 1a side of the substrate 1. In addition, a gate electrode 4 is formed for selecting the carrier running layer. The second carrier running layer is formed with a gate bias at a part after crossing the insulating area 2. Therefore, such a semiconductor state as an HEMT is formed, because the running of electrons is not disturbed by the insulating area. When the first carrier running layer is selected with the gate bias, an insulated state is set, because the running of electrons is disturbed by the insulating area 2.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention relates to a field effect transistor in which a carrier transport layer is selected, and particularly to a field effect transistor in which high-speed operation is performed by selecting carrier transport layers having different carrier mobilities, such as a velocity modulation field effect transistor. Regarding transistors.

0002

[Prior Art] In general, a field effect transistor has gm (mutual conductance) by changing the gate bias and changing the carrier concentration between the source and drain.
I am getting . In this type of transistor, the gate is turned on by electrons (or holes) traveling between both ends of the channel between the source and drain, and for high-speed operation, electrons must travel between the ends. Although it is necessary to shorten the travel time, there is a limit to high-speed operation due to the limitations of microfabrication.

[0003] Therefore, field-effect transistors, which have a concept different from conventional field-effect transistors and whose operating speed does not depend on the traveling speed of electrons, etc., have been considered, and one such field-effect transistor is a velocity modulation transistor (VMT; veloc
ity-modulation transistor
). In other words, in general, in a transistor,
The current I is the channel width w, the sheet carrier concentration nS,
It is expressed by multiplying the mobility μ by the unit charge e, but in conventional field effect transistors, the mobility μ itself does not change. However, in velocity modulation type transistors such as mass modulation type transistors, the mobility μ changes according to changes in effective mass. A mechanism for operating the is disclosed.

0004

However, in the mass modulation type field effect transistor described in the above-mentioned publication, it is necessary to form a vertical superlattice structure using a tilted substrate in the channel region, and the manufacturing process is difficult. It's not easy. Also,
Some of the speed modulating transistors have H
There are also devices that can operate at high speeds comparable to EMTs, but are not suitable for room temperature operation.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a field effect transistor that operates reliably even at room temperature, achieves high speed operation and high gm, and is advantageous in manufacturing. shall be.

[0006]

[Means for Solving the Problems] In order to achieve the above object, a field effect transistor of the present invention has a first carrier transit layer and a second carrier transit layer, and a gate bias is applied to the first carrier transit layer. Or a field effect transistor in which a second carrier transport layer is selected, characterized in that an insulating region is present in the first carrier transport layer.

[0007] Here, one or more insulating regions can be provided in the first carrier transit layer, and function as a potential barrier that divides the carrier transit layer or protrudes into the carrier transit layer. This insulating region may have a structure in which an insulator such as a silicon oxide film or a nitride film is buried, or may be formed by a void. In the case where the insulating region is formed so as to divide the carrier traveling layer into a plurality of parts in the traveling direction, a semiconductor state in which a current flows through the channel and an insulating state in which no current flows in the channel are selected by the gate bias. Each carrier traveling layer can be formed at a heterojunction interface between layers having different band gaps.

In one example of the field effect transistor of the present invention, in addition to the structure in which the first or second carrier transit layer is selected by a gate bias, an insulating region is present in the first carrier transit layer. However, the second carrier traveling layer has a structure in which at least a portion thereof performs quantum confinement in a direction perpendicular to the carrier traveling direction.

In another example of the present invention, in addition to the structure in which the first or second carrier transit layer is selected by a gate bias, an insulating region is present in the first carrier transit layer. However, the second carrier traveling layer has a structure in which a tunnel barrier exists along the carrier traveling direction and a superlattice mini-band is formed.

0010

[Operation] An insulating region is formed in the first carrier traveling layer between the first carrier traveling layer and the second carrier traveling layer in which the traveling of carriers is selected by a gate bias. Therefore, in the first carrier traveling layer, carrier traveling is obstructed by the insulating region and the mobility is substantially zero, and in the second
Current flows when switching to the carrier transport layer side. Selection of the traveling layer by the gate bias does not require electrons to be dropped into the source and drain as in conventional field effect transistors, so it responds quickly and, as a result, performs high-speed switching.

[0011] In a field effect transistor in which the second carrier transport layer has a structure in which quantum confinement is carried out in at least a portion of the second carrier transport layer in a direction perpendicular to the transport direction, the direction of movement of carriers is limited, so that, for example, the transport layer is By making it undoped, the influence of Coulomb scattering caused by impurities can be significantly reduced. Therefore, high carrier mobility can be obtained.

In addition, when the second carrier traveling layer has a structure in which a tunnel barrier exists along the carrier traveling direction and a superlattice miniband is formed, it is possible to form a so-called quantum wire structure, and optical When the superlattice mini-bandwidth is small compared to the phonon energy and the mini-gap width is wide, scattering by optical phonons, which is dominant near room temperature, is suppressed. Therefore, ballistic carrier conduction is realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

[First Example] In this example, AlGaAs
This is an example of a field effect transistor using /GaAs. Figure 1 shows the cross-sectional structure near the channel. A plurality of insulating regions 2 are arranged in blocks on an undoped GaAs substrate 1.
is formed. This insulating region 2 has a depth d from the heterojunction surface 1a of the GaAs substrate 1.
1. It is embedded at approximately a constant interval L on the plane.
They are arranged with 1 space between them. The insulating region 2 is made of an insulating material such as a silicon oxide film. Although not shown in the drawing, there is a normal H
Similar to EMT, a semi-insulating GaAs substrate or the like can be placed via a buffer layer.

Each heterojunction surface 1a of the GaAs substrate 1
An n-AlGaAs layer 3 as an electron supply layer is formed thereon. GaAs substrate 1 and n-AlGaAs
In the layer 3, the n-AlGaAs layer 3 has a wider bandgap, and as a result, the GaAs substrate 1 and the n-AlGaAs
A two-dimensional electron gas (2DEG) layer is formed on the GaAs substrate 1 side of the heterojunction surface 1a of the layer 3. Therefore, this embodiment has a configuration similar to that of a HEMT device at this heterojunction surface 1a portion.

The upper surface of the n-AlGaAs layer 3 is at the same height as the insulating region 2, and a gate electrode 4 is formed on that surface. This gate electrode 4 is made of, for example, Al. By changing the gate bias supplied to the gate electrode 4, the region of the two-dimensional electron gas is changed, and a transit layer between the first electron transit layer and the second electron transit layer is selected.

FIG. 2 is a schematic plan view of the field effect transistor of this embodiment. The lower part of the substantially rectangular gate electrode 4 serves as a channel region, and a plurality of insulating regions 2 are provided to divide the channel region. Each insulating region 2 has a long side spanning the gate width, as shown by the hatched region, and divides the channel region into a plurality of regions in the gate length direction, which is the traveling direction of carriers (electrons). An n-AlGaAs layer 3 is formed in each region between the pair of insulating regions 2, and a two-dimensional carrier transport layer is formed on the heterojunction surface between the n-AlGaAs layer 3 and the GaAs substrate 1 below. An electron gas layer is formed.

The source region 5 and drain region 6 are formed at both ends in the carrier traveling direction. An ohmic metal (not shown) is deposited on the source region 5 and the drain region 6, and alloyed thereon. The current between these source region 5 and drain region 6 changes depending on the voltage supplied to gate electrode 4.

Next, (a) and (b) of FIGS. 3, 4, and 5
), the operation of the field effect transistor of this example will be explained.

First, FIG. 3 is a diagram showing the state of the electron transit layer, and corresponds to a state where the gate bias is zero (Vg=0) and the first carrier transit layer is selected. In FIG. 3, a dotted line C1 indicates a region of two-dimensional electron gas, and electrons are accumulated in a region of this dotted line C1 on the heterojunction surface 1a side. In this state, the dotted line C1 indicates each n-Al
Although it is formed on the heterojunction surface of the GaAs layer 3, the source and drain are not continuous due to the insulating region 2, but are separated in the carrier traveling direction by the insulating region 2. This is because the first carrier transit layer formed near the heterojunction surface 1a functions as a large potential barrier and prevents the passage of electrons, resulting in an insulating state as a whole.

FIG. 5(a) is a potential diagram near the heterojunction surface 1a in an insulating state, and the curve P3 is n-A.
This is a band potential curve corresponding to the lGaAs layer 3, and the curve P1 is a hand potential curve corresponding to the GaAs substrate 1. A triangular potential well is formed at the heterojunction surface 1a, and a two-dimensional electron gas (2DEG) is formed within the triangular potential well. When this two-dimensional electron gas advances to the insulating region 2, it is blocked by the infinite potential P2 and cannot pass through the insulating region 2, and as a result, the field effect transistor exhibits an insulating state. become.

Next, FIG. 4 is a diagram showing the state of the electron transport layer, and when the gate bias is negative (Vg<0), the second
FIG. 3 is a diagram corresponding to a state in which a carrier traveling layer of is selected. In FIG. 4, the dotted line C2 indicates the two-dimensional electron gas region, and the dotted line C2 indicates the two-dimensional electron gas region.
It becomes two lines. In this state, each n-AlGaAs layer 3
Not only the lower part of the insulating region 2 but also the lower part of the insulating region 2 functions as a part of the carrier transport layer, and since the carrier transport layer is continuous between the source and drain, a drain current flows. That is, depending on the gate bias, GaA
A carrier traveling layer is formed at a deep position in the s-substrate 1, and as a result, operation by two-dimensional electron gas is performed. By forming a channel also under the insulating region 2 in this way,
The element becomes a semiconductor (HEMT) state.

FIG. 5(b) is a potential diagram near the heterojunction surface 1a in a semiconductor state, where the curve p3 is n-
This is a band potential curve corresponding to the AlGaAs layer 3, and the curve p1 is a hand potential curve corresponding to the GaAs substrate 1. Since the gate bias Vg is negative (<0), two-dimensional electron gas (2DEG)
The distribution extends deep into the substrate 1. As a result, the two-dimensional electron gas (2DE
G) protrudes, and its protruding portion ep a connects with other divided portions, resulting in conduction between the source and drain. At this time, the transistor is turned on and drain current flows.

[0024] A field effect transistor with this structure can rapidly switch between an insulating state when the gate bias is zero and a semiconductor (HEMT) state when the gate bias is negative, making it possible to achieve high gm and high-speed operation. is realized. Furthermore, the field effect transistor of this embodiment is convenient in terms of manufacture because it obtains a running layer with substantially zero mobility from the insulating region without using a tilted substrate or the like.

[Second Embodiment] This embodiment is an example of a field effect transistor having a quantum wire (coupled quantum box) structure, and has a channel structure shown in FIG.

FIG. 6 is a diagram showing a cross-sectional structure near the channel. The field effect transistor of this example uses an undoped GaAs substrate 21, and a plurality of insulating regions 22 are formed on its surface so as to divide the channel in the X direction in the figure, which is the carrier traveling direction. . Each insulating region 22 has a substantially rectangular cross section, and when the structure is a one-dimensional coupled quantum box array structure, each insulating region 22 extends across the channel width in a direction perpendicular to the drawing, and its structure is a one-dimensional coupled quantum box array structure. When the structure is a two-dimensional coupled quantum box array structure, each insulating region 22 is formed in a plane parallel to the main surface of the substrate in the X direction and in a direction perpendicular thereto so as to surround a plurality of quantum boxes arranged in a matrix. They are extended and arranged in a so-called grid pattern.

In the portion between each insulating region 22, as in the first embodiment, G is provided at a position higher than the bottom surface of the insulating region 22.
An interface of the aAs substrate 21 is provided, and n-AlGaAs is provided at the interface so that the interface becomes a heterojunction surface 21a.
Layer 23 is laminated. This n-AlGaAs layer 23 has H
It functions as an electron supply layer of the EMT structure, and the heterojunction surface 2
A channel layer is formed on the GaAs substrate 21 side of 1a.

Now, focusing on the size of the n-AlGaAs layer 23 and the insulating region 22, the size of the n-AlGaAs layer 23 in the electron travel direction in the cross section is L3.
The size of the insulating region 22 in the electron travel direction is L2
It is said that Here, the distance obtained by adding the sizes L3 and L2 is approximately the quantum mechanical wavelength (de Broglie wavelength) of the electron.
It is assumed to be as short as λe, and an electron confinement effect appears. For example, the size L3 +L2 is about 100 Å, and L3 and L2 are about 50 Å. When this embodiment has a coupled quantum box array structure arranged in a two-dimensional matrix, the insulating region 22 and the n-AlGaAs layer 2 have the same size in the direction perpendicular to FIG.
3 is repeated, and an electron confinement effect can be obtained also in the direction perpendicular to the cross section of the figure.

In the transistor of this embodiment having such a coupled quantum box structure, the surface of the insulating region 22 and the n-AlGaAs
The surfaces of the layer 23 are substantially the same plane, and a gate electrode layer 24 made of an aluminum-based metal film or the like is formed on the surface. This gate electrode layer 24 is formed to cover the entire channel region, and the on/off of the gate is controlled by a gate bias supplied to the gate electrode layer 24.

Underneath the insulating regions 22, undoped AlG is provided to function as a tunnel barrier.
An aAs layer 25 is formed. This undoped AlGa
The size of the As layer 25 is approximately the same as the size L2 of the insulating region 22, and the quantum boxes at both ends are quantum mechanically coupled via the undoped AlGaAs layer 25.

In the field effect transistor of this embodiment having such a structure, a channel is formed only in the vicinity of the heterojunction surface 21a when the gate bias is zero, as in the first embodiment. Since the channel is divided by the insulating region 22, it is in a gate-off state, that is, an insulating state. In addition, when the gate bias is negative, the channel region of the heterojunction surface 21a expands to the deep part of the substrate, forming an undoped Al layer that is the second carrier transit layer.
This spreads to the surface including the GaAs layer 25, and electrons travel while tunneling through the undoped AlGaAs layer 25. In particular, in this case, undoped A
A superlattice mini-band is formed by the tunnel barrier of the lGaAs layer 25, and the width of the mini-band is made smaller than the optical phonon energy (minimum value), and at the same time, the mini-gap is made larger than the optical phonon energy (maximum value). By doing so, scattering by optical phonons is significantly suppressed. Generally, optical phonons are an important factor that determines mobility at room temperature, etc., and by suppressing scattering by optical phonons, extremely high electron mobility can be achieved at around room temperature due to ballistic conduction phenomena. Also in the field effect transistor of this embodiment, high-speed switching is performed in response to changes in gate bias, and high-speed operation is achieved, as in the first embodiment.

[Third Example] This example is based on a structure that combines the tendency of the difference in mobility between the first carrier traveling layer and the second carrier traveling layer and the tendency of the carrier concentration of each traveling layer. This is an example of a field effect transistor, and is an example in which the positional relationship between the gate and the channel is reversed from the first and second embodiments.

First, FIG. 7 shows the cross-sectional structure of the field effect transistor of this embodiment. For example, on a semi-insulating GaAs substrate 31, a plurality of insulating regions 32 are formed spaced apart from each other in the X direction in the figure, which is the traveling direction of electrons. These insulating regions 32 are formed to cross the channel in a direction perpendicular to the X direction, and each has a substantially rectangular cross section. An n-AlGaAs layer 33 is formed between these insulating regions 32, and this n-AlGaAs layer 33 is
Each of the T devices functions as an electron supply layer. n
- The height of the AlGaAs layer 33 is not the same as that of the insulating region 32, but the insulating region 32 is formed at a higher height on the substrate. Note that the insulating region 32 and the n-AlGaAs layer 33
may be formed on the substrate via a buffer layer or the like. Further, the size of the insulating region 32 and the n-AlGaAs layer 33 may be the quantum mechanical size of an electron, and the quantum blocks of each n-AlGaAs layer 33 are arranged in a two-dimensional matrix to form a coupled quantum box. It is also possible to have a structure in which the insulating region surrounds the insulating region.

The n-AlGaAs layer 33 and the insulating region 3
2 have different heights, but their uneven surfaces are buried in the undoped GaAs layer 34 from the surface. This undoped GaAs layer 34 has a narrower band gap than the n-AlGaAs layer 33, and the GaAs layer 34 has a narrower band gap than the n-AlGaAs layer 33.
The interface between the n-AlGaAs layer 33 and the n-AlGaAs layer 33 becomes a heterojunction surface 35, and as shown by the dotted line in the figure, an electron gas layer is formed on the undoped GaAs layer 34 side of the heterojunction surface 35 at zero bias. This undoped Ga
The upper surface of the As layer 34 is a substantially flat surface, and an undoped AlGaAs layer 36 is laminated on that surface.

The undoped AlGaAs layer 36 is made of Ga
The band gap is made wider than that of the As layer 34, and the interface between the undoped AlGaAs layer 36 and the GaAs layer 34 also serves as a heterojunction surface 37. Therefore, as described later, depending on the gate bias, the undoped AlGaAs layer 36
An electron gas layer is also formed on the side heterojunction surface 37, resulting in a gate-on state.

A gate electrode layer 38 is formed on this undoped AlGaAs layer 36. This gate electrode layer 3
8 is an undoped AlGaAs layer 3 as described later.
6 to control the potential of the GaAs layer 34. Gate electrode layer 38 is formed to cover the channel region.

A source region 39 and a drain region 40 are formed at both ends of the GaAs layer 34. When the transistor is in the on state, the source region 39 and the drain region 40
A current will flow between them. Note that in the figure, dotted lines schematically indicate channels when the transistor is off, indicating a state in which the channels are dispersed by the insulating regions 32.

The field effect transistor of this embodiment having the structure generally described above performs a switching operation by switching the carrier transit layer by gate bias.

First, FIG. 8 is a potential energy diagram showing an insulating state, and shows the potential of a cross section of a portion where the n-AlGaAs layer 33 is formed. In Figure 8,
Curve r1 is the potential corresponding to the undoped AlGaAs layer 36, and curve r2 is the potential corresponding to the undoped AlGaAs layer 36.
This is the potential corresponding to the As layer 34. AlGaA
There is a heterojunction surface 37 between the s layer 36 and the GaAs layer 34.
There is a step in the band corresponding to . Also, the curve r3 is n
- potential corresponding to the AlGaAs layer 33,
There is a band step corresponding to the heterojunction surface 35 between the curve r3 and the curve r2. Dotted line r4 is the insulation region 32
This line corresponds to the upper end of the dotted line r4, and considering that electrons move to the insulating region 32, the insulating region 32 functions as an extremely large potential barrier at a position deep from the surface below the dotted line r4. Figure 8 shows zero bias (Vg=
In this case, the electron gas is in the first carrier traveling layer near the heterojunction surface 35. However, as shown by the dotted line r4 in the figure, in the heterojunction surface 35, each insulating region 32 functions as a potential barrier in the carrier travel direction, and the electron travel is hindered. Therefore, when the gate bias is set to zero and the first carrier transit layer is selected, no current flows between the source and drain, resulting in an insulating state.

Next, FIG. 9 is a diagram showing the semiconductor state. In the diagram, curve R1 is the potential corresponding to the undoped AlGaAs layer 36, and curve R2 is the potential corresponding to the undoped GaAs layer 34. be. Further, a curve R3 is a potential corresponding to the n-AlGaAs layer 33, and a dotted line R4 is a line corresponding to the upper end of the insulating region 32. In FIG. 9, the gate bias is set to be positive, and the curve R1, which is the potential corresponding to the undoped AlGaAs layer 36, is drawn to a high energy position in accordance with the gate bias. As a result, the electron gas existing on the heterojunction surface 35 side in the undoped GaAs layer 34 is moved to the heterojunction surface 37 side due to the gate bias, and electrons are present in the second carrier transit layer. At this interface on the heterojunction 37 side, a channel is formed at a position closer to the gate side than the upper end of the insulating region 32 indicated by the dotted line R4, and
Electrons travel unhindered by the potential barrier 2. That is, the gate is turned on and a drain current flows.

In the field effect transistor of this embodiment having such a structure, the electron transit layer on the heterojunction surface 37 side is rapidly moved from the insulating state in which the electron transit is blocked by the insulating region 32 to the electron transit layer on the heterojunction surface 37 side according to the gate bias. This enables high-speed switching, which is not limited by the time taken for carriers to cross between the source and drain as in conventional FETs. In particular, in the field effect transistor of this embodiment, in a state where electrons travel and the gate is turned on, the electron density n of the heterojunction surface 37 is
shows a tendency depending on the gate bias; for example, the higher the gate voltage, the higher the electron density n at the heterojunction surface 37. Therefore, when the electron mobility increases due to the selection of the traveling layer, the electron density n also increases in the same way, and a higher gm (mutual conductance) can be obtained compared to a field effect transistor that simply modulates the speed. It turns out. Further, by using a superlattice structure as in the second embodiment, high electron mobility can be obtained even at room temperature, which is advantageous for high-speed operation.

[Fourth Embodiment] The field effect transistor of this embodiment is a modification of the third embodiment and has the structure shown in FIG. 10. Now, the manufacturing method will also be explained with reference to FIGS. 11 to 14.

First, as shown in FIG. 10, in the field effect transistor of this embodiment, an undoped GaAs layer 41 is formed as a channel layer.
An undoped AlGaAs layer 42 for obtaining a heterojunction surface 48 is formed on the gate side of the As41 layer. An n-AlGaAs layer 43 as an electron supply layer is formed on the side opposite to the gate electrode of the GaAs layer 41 as a channel layer, and this n-AlGaAs layer 43 and the GaAs layer 4
The interface between 1 and 1 is also a heterojunction surface 45. Furthermore n-
Ga from the AlGaAs layer 43 beyond the heterojunction surface 45
The heterojunction surface 4 spans the portion of the As layer 41 on the interface 45 side.
A plurality of grooves 44 are formed extending parallel to the X direction in the figure, which is substantially perpendicular to the grooves 5 . These grooves 44 serve as insulating regions, and the tips of the grooves 44 are formed so as to cross the GaAs layer 41 in the channel width direction, which is the Z direction in the figure. Since the groove 44 is formed so as to divide the channel length direction, which is the Y direction in the figure, when the heterojunction surface 45 side of the GaAs layer 41 becomes an electron transport layer, the source region 47 and the drain region (not shown) are separated. There is no conduction between them, and they are in an insulated state.

The gate electrode 46 is made of undoped AlGaA.
The s-layer 42 is formed on the opposite side of the GaAs layer 41. The gate electrode 46 is for controlling the movement of electrons by gate bias. Similar to the third embodiment, when the gate bias is zero, the heterojunction surface 45 side of the GaAs layer 41 serves as a carrier transit layer, but since the groove 44 functions as an insulating region, no drain current flows. Also, when the gate bias is forward bias, G
Heterojunction surface 4 of the aAs layer 41 on the AlGaAs layer 42 side
A channel is formed in 8, making it possible to increase electron density and at the same time achieve high-speed electron travel. Furthermore, when switching the gate bias, high-speed switching similar to other speed modulation field effect transistors is performed.

In the field effect transistor having this structure, the size of the groove or the heterojunction surface 45 in the Y direction in the figure can be set to about the quantum mechanical wavelength of electrons, and It is also possible to have a quantum wire structure or a coupled quantum box structure in which the heterojunction surfaces are arranged in a two-dimensional matrix and the heterojunction surface 48 side has a superlattice structure that forms a mini band. In addition, groove 4
It is also possible to embed an insulating film or the like in the portion 4, and the gate electrode 46 is formed of a metal such as aluminum.

Next, with reference to FIGS. 11 to 14, a method for manufacturing the field effect transistor of this embodiment will also be described.

First, as shown in FIG. 11, semi-insulating Ga
An n-AlGaAs layer 52 is laminated on the main surface of the As substrate 51, and an inclined surface 52a is formed in the n-AlGaAs layer 52 by patterning in the forward mesa direction by wet etching.

Next, as shown in FIG. 12, an undoped GaAs layer 53 is grown on the entire surface including the slope 52a by MOCVD or the like, and then an undoped Al layer 53 is grown on the entire surface including the slope 52a.
A GaAs layer 54 is grown. The undoped GaAs layer 53 is used as a channel layer, and the AlGaAs layer 54 is made of GaAs.
A heterojunction is made to the s-layer 53.

Next, RIE (reactive ion etching) is performed obliquely from the direction of the arrow in FIG. 13, which is the in-plane direction of the inclined surface 52a. By this oblique RIE, the GaAs layer 53 on the GaAs substrate 51 and the n-AlGaAs layer 52 is
and the AlGaAs layer 54 are removed, and the GaAs layer 53 and the AlGaAs layer 54 on the inclined surface 52a are removed.

In this way, GaAs is formed only on the inclined surface 52a.
After leaving layer 53 and AlGaAs layer 54, FIG.
As shown in FIG. 2, a plurality of grooves 55 are formed by patterning. This groove 55 is formed so as to vertically divide the inclined surface 52a within the inclined surface, and at the same time, the groove 55 also extends to a part of the GaAs layer 53. Therefore, the GaAs layer 53 and n-
The heterojunction surface between the AlGaAs layers 52 is divided in the Y direction in the figure, which is the traveling direction of carriers, and becomes insulated when a gate bias is applied to form a channel on the heterojunction surface side.

Thereafter, a source electrode, a drain electrode, a gate electrode, etc. are formed to complete a field effect transistor as shown in FIG. Note that the groove 55 may be an insulating region made of air, or may be filled with an insulator.

[0052]

Effects of the Invention As described above, in the field effect transistor of the present invention, the first carrier transit layer in which the insulating region is formed and the second carrier transit layer are selected by a gate bias. As a result, the electrical properties transition between an insulating state and a semiconductor state. Since this transition is performed particularly quickly, high-speed operation and high gm are realized.

Furthermore, in a field effect transistor in which quantum confinement is achieved in the second carrier transport layer, the direction of movement of carriers is limited, and by making the transport layer undoped, for example, the influence of Coulomb scattering due to impurities can be significantly reduced. Can be reduced. Therefore, high carrier mobility can be obtained.

Furthermore, in a field effect transistor in which a superlattice miniband is formed in the second carrier transport layer, a so-called quantum wire or coupled quantum box structure can be used, and the superlattice miniband is smaller than the energy of optical phonons. Ballistic carrier conduction is achieved when the band width is small and the minigap width is wide.

[0055]

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a cross-sectional structure near a channel of an example of a field-effect transistor of the present invention.

FIG. 2 is a plan view partially omitted in the channel direction of the example.

FIG. 3 is a cross-sectional view schematically showing the expansion of the channel region in the insulating state of the example.

FIG. 4 is a cross-sectional view schematically showing the expansion of the channel region in the semiconductor state of the example.

FIG. 5 is a potential energy diagram of the above example,
(a) is a diagram showing the potential when the gate bias is zero, that is, the potential in the insulating state, and (b) is a diagram showing the potential when the gate bias is negative, that is, the potential in the semiconductor state.

FIG. 6 is a cross-sectional view of another example of the field effect transistor of the present invention, which is a field effect transistor having a quantum wire structure.

FIG. 7 is a cross-sectional view of still another example of the field-effect transistor of the present invention, which is a transistor having a gate electrode on the channel layer side rather than on the electron supply layer side.

8 is a potential energy diagram showing the potential of the field effect transistor of FIG. 7 in an insulated state; FIG.

9 is a potential energy diagram showing the potential of the field effect transistor of FIG. 7 in a semiconductor state; FIG.

FIG. 10 is a partially cutaway perspective view showing still another example of the field effect transistor of the present invention.

11 is a process sectional view for explaining the manufacturing process of the field effect transistor shown in FIG. 10, up to the step of forming an inclined surface; FIG.

12 is a process cross-sectional view for explaining the manufacturing process of the field effect transistor of FIG. 10, in which AlGaA
FIG. 3 is a process cross-sectional view up to the growth process of the s-layer.

13 is a process cross-sectional view for explaining the manufacturing process of the field effect transistor of FIG. 10, in which oblique RIE
It is a process sectional view up to the process.

14 is a process cross-sectional view for explaining the manufacturing process of the field effect transistor of FIG. 10, up to the step of forming a groove; FIG.

[Explanation of symbols]

1...GaAs substrate 1a...Heterojunction surface 2...Insulation area 3...n-AlGaAs layer 4...Gate electrode 5...Source area 6...Drain region 21...GaAs substrate 22...Insulation area 23...n-AlGaAs layer 24...Gate electrode layer 25...AlGaAs layer 31...GaAs substrate 32...Insulation area 33...n-AlGaAs layer 34...GaAs layer 35...Heterojunction surface 36...AlGaAs layer 37...Heterojunction surface 38...Gate electrode layer 39...Source area 40...Drain region 41...GaAs layer 42...AlGaAs layer 43...n-AlGaAs layer 44...Insulation area 45...Heterojunction surface 46...Gate electrode 47...Source area 48...Heterojunction surface

Claims (3)

[Claims] 1. A field effect transistor in which a first carrier transit layer or a second carrier transit layer is selected for carrier transit by a gate bias,
A field effect transistor characterized in that an insulating region is present in the first carrier transport layer. 2. The field-effect transistor according to claim 1, wherein at least a portion of the second carrier traveling layer has a structure that performs quantum confinement in a direction perpendicular to the carrier traveling direction. 3. The field effect transistor according to claim 1, wherein the second carrier traveling layer has a tunnel barrier along the carrier traveling direction to form a superlattice mini-band.