JPH04353925A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To shorten the processing time of a division program for an arithmetic unit executing division by means of combining addition and subtraction. CONSTITUTION:A latch pulse generation part 32 supplies a latch pulse RLP to a register 17 based on the decoding result of an instruction decoder 31 and a carry flag outputted from a computing element 19. The register 17 latches an operated result in synchronizing with the latch pulse RLP. When subtraction is executed in the computing element 19, a subtraction result is negative, and the carry flag is '1', for example, the latch pulse RLP is not outputted from the latch pulse generation part 32 to the register 17 and the operated at that time result is not latched by the register 17. When the subtraction result becomes negative at the time of executing division by combining addition and subtraction, a processing for adding a divisor is not required and the number of the steps of the program can be reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device that performs division by combining addition and subtraction instructions.

0002

[Prior Art] Early programmable controllers (hereinafter referred to as PCs) only performed sequence control (bit-by-bit logic control), which was the function of relay boards up until then. Some have been put into practical use that have numerical arithmetic control functions (word-by-word logic control, ie, quantity control), data processing functions, etc. Numerical calculation functions are divided into logical operations such as AND and OR, and arithmetic operations such as arithmetic operations and square roots.

First, the structure of a conventional instruction code and an arithmetic circuit that decodes the instruction code and performs an operation will be explained with reference to FIG. The instruction code consists of an instruction classification section 11 for distinguishing it from other instructions, and register specification sections R1 and R2 for specifying registers to be used in the instruction, and other sections are not used.

The instruction classification section 11 is decoded by an instruction decoder 12, and the register specification section R1 is decoded by an R1 decoder 13.
The register designation portions R2 are respectively decoded by the R2 decoder 14.

[0005] The latch pulse generating section 15 outputs a latch pulse RLP to a corresponding register among the plurality of registers 17 based on the decoding result at the instruction decoder 12 and the decoding result at the R1 decoder.

[0006] The register file 16 includes the plurality of registers 17 described above and 2 registers for selecting one of the outputs of the registers 17.
selectors 18a, 18b and the selectors 18a
, 18b as inputs.

The decoding result of the R1 decoder is input to the selection terminal of the selector 18a, and the decoding result of the R2 decoder is input to the selection terminal of the other selector 18b. The register 17 is selected and its contents are output to the arithmetic unit 19.

[0008] The arithmetic unit 19 is a combination of general-purpose 4-bit ALUs and the like for the necessary number of bits, and the control terminal of this arithmetic unit 19 indicates the type of operation that is the decoding result of the instruction decoder 12. Information is input, subtraction or addition is performed according to the information, and the result of the operation is taken into the corresponding register 17. This computing unit 19
, when the result of subtraction is smaller than the argument,
A carry flag CF which becomes "1" and "0" in other cases is output to the flag register 20.

The flag register 20 is a register that stores various flags, and is a carry flag CF output from the arithmetic unit 19 in synchronization with the rise of the flag register latch pulse FLP generated by the latch pulse generator 15. Latch etc.

The specific configuration of the latch pulse generator 15 will now be described with reference to FIG. 8. Decoder 21
is based on the instruction decoding result in the instruction decoder 12,
If the instruction to be executed is an instruction that changes the contents of the flag register 20, the output signal a is set to "1"; if the instruction is an instruction that changes any of the plurality of registers 17, the output signal b is set to "1"; In this case, both signals are set to "0". Note that when the instruction decode result is a subtraction, both the signal a and the signal b become "1".

One input terminal of the NAND gate 22 has
The output signal a of the decoder 21 is input, and the signal obtained by inverting the clock signal CK by the inverter 23 is input to the other input terminal. Therefore, when the signal a is "1", a latch pulse FLP synchronized with the clock signal CK is output to the flag register 20.

The decoding result of the R1 decoder 13, the output signal b of the decoder 21, and the clock signal inverted by the inverter 23 are input to the plurality of NAND gates 24, and when the signal b is "1", , R1 from the NAND gate 24 whose decoding result is "1" outputs a latch pulse RLP synchronized with the clock signal to the corresponding register 17.

Next, FIG. 9 is an operation time chart of a conventional arithmetic circuit.
A time chart is shown when performing the calculation. First, the arithmetic unit 19 subtracts [R1-R2] and stores the subtraction result in the register indicated by R1 in synchronization with the rise of the register latch pulse RLP. At the same time, CF is latched into the flag register 20 in synchronization with the rising edge of the flag register latch pulse FLP.

Next, a flowchart of a conventional division program in which division of unsigned binary integers is realized by software will be explained with reference to FIG. First, the partial remainder register is cleared to zero (FIG. 10, S1). Next, the contents of the dividend register and partial remainder register are shifted one bit to the left (S2). Note that when shifted one bit to the left, the most significant bit of the dividend register is set to the least significant bit of the partial remainder register.

Next, the divisor is subtracted from the partial remainder register (S3). Then, it is determined whether the subtraction result is zero, positive, or negative (S4). If the subtraction result is zero or positive, the partial remainder is equal to or larger than the divisor;
In this case, the process advances to step S5 and the least significant bit of the dividend register is set to "1". Here, "1" set in the least significant bit of the dividend register indicates the quotient of division.

On the other hand, if the subtraction result is negative, this means that the partial remainder is smaller than the divisor, and in this case, in order to return the value of the partial remainder register to the value before subtraction, the partial remainder register is Add the divisor to .

Thereafter, it is determined whether the calculations for the number of bits of the dividend have been completed (S7). If the operation for the number of bits has not been completed, the process returns to step S2, the contents of the dividend register and the partial remainder register are shifted to the left by one bit, and the same operation is performed for the next bit.

When the calculation for the number of bits of the dividend is completed,
The quotient is found in the dividend register and the remainder is found in the partial remainder register (S8). Next, an example of a specific program based on the above flowchart is shown in FIG. The program in Listing 1 of FIG. 11 is a division routine for a 16×16 bit unsigned binary number.

Assume now that the dividend register is AX, the divisor register is BX, and the remainder register is DX, and the quotient of the division is sequentially stored in the right bit of the dividend register AX, which becomes vacant by left shifting.

As shown in FIG. 11, first, "OR BX
, BX" and "JZ UNSDIV9" to check that the divisor register BX is not "0" and execute "XOR
DX, DX" to clear the remainder register DX.

Next, "SHL AX, 1" is executed to rotate the contents of the dividend register AX to the left by 1 bit. Also, execute “RCL DX, 1” to set the remainder register D.
Rotate the contents of X one bit to the left through the carry. Furthermore, "SUB DX, BX" is executed to subtract the value of the divisor register BX from the value of the remainder register DX.

As a result of the subtraction, if the partial remainder is equal to or larger than the divisor and the carry flag is "0", the process advances to the address specified by the operand "unsdiv2" of the JNC instruction and is stored in the accumulator AL, that is, the dividend register A.
Increment the value of X.

On the other hand, if the partial remainder is smaller than the divisor and the carry flag is "1", the next instruction "AD" after the JNC instruction is
DX, BX" to add the divisor to the partial remainder DX. Thereafter, the process returns to unsdiv1 and the above-described process is repeated.

Note that when the carry flag is "1", the reason why the divisor BX is added to the partial remainder DX is that when subtraction is performed between the remainder register DX and the divisor register BX,
This is to return the value of the register DX to the value before the subtraction, since the result of the subtraction is automatically stored in the remainder register DX.

[0025]

[Problems to be Solved by the Invention] As mentioned above, conventionally, in order to realize a division instruction by combining addition and subtraction instructions, it is necessary to determine whether the subtraction result is positive or negative, and when the subtraction result is negative,
Processing of adding the divisor to the remainder, etc. (Figure 10, ■ and Figure 11,
(2) was necessary. Furthermore, these processes are placed in a loop of the program and are repeatedly executed for the number of bits of the division, which increases the instruction processing time and makes it impossible to speed up the division program.

[0026] In addition, when division is realized by hardware, by using the division instruction DIV, the division program becomes simple and the processing becomes high-speed, as shown in List 2 of Fig. 11, but the hardware configuration becomes complicated. The problem was that it became large-scale. These problems are not limited to division, but also apply to calculations such as square roots.

The present invention relates to an arithmetic device that performs division by combining addition and subtraction, and an object of the present invention is to shorten the processing time of a division program.

[0028]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In an arithmetic device that performs division by combining addition and subtraction instructions, an instruction decoding means 1 decodes an instruction code, and an arithmetic means 2 executes the operation decoded by the instruction decoding means 1.

The register 3 is a register for latching the calculation result of the calculation means 2, and the latch pulse generation means 4
generates a latch pulse that controls whether or not the register 3 latches the subtraction result based on a carry flag that is set or reset as a result of the subtraction in the calculation means 2.

[0030]

[Operation] In the arithmetic unit, when subtraction is performed between registers, the result of the subtraction is automatically stored in the same register. Therefore, in the conventional binary integer division program described above, when the result of subtraction is negative, it is necessary to add the divisor to return the value of the dividend register to the value before subtraction.

In contrast, in the present invention, when the subtraction result is negative and the carry flag is set, no latch pulse is output from the latch pulse generating means 4, and the subtraction result is not latched into the register 3.

Therefore, even if the result of subtraction is negative, there is no need to add the same value after subtraction to return the value of register 3 to the value before subtraction, and the number of steps in the division program can be reduced to speed up processing. It can be done.

[0033]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a configuration diagram of the arithmetic circuit of the programmable controller of the embodiment. In this figure, circuit blocks that are the same as those of the conventional arithmetic circuit shown in FIG. 7 are given the same reference numerals, and their explanation will be omitted. In this embodiment, in addition to the normal subtraction instruction (SUB), a SUBNC instruction is defined in which the subtraction result is not latched in the register 17 when the carry flag (CF) is set as a result of the subtraction.

The instruction decoder 31 in FIG. 2 decodes the instruction classification section 11 of the instruction code, outputs the decoding result to the latch pulse generation section 32, and also outputs the decoding result to the latch pulse generation section 32.
Information indicating the type of operation of the BNC instruction is output to the OR gate 33.

A signal that becomes "1" when the SUB instruction or SUBNC instruction is decoded, for example, is input to the OR gate 33, and the result of the logical sum of the two is input to the signal S.
It is output as S to the arithmetic unit 19. Further, this signal SS is output to the latch pulse generation section 32.

The latch pulse generation unit 32 generates a latch pulse F for the flag register 20 based on the decoding result of the instruction decoder 31 and the decoding result of the R1 decoder 13.
LP and latch pulses R corresponding to multiple registers 17
This is a circuit that generates LP.

The latch pulse generation section 32 specifically has a configuration as shown in FIG. In the case of an instruction to change, the output signal a is set to "1", and in the case of an instruction to change any of the plurality of registers 17, the output signal b is set to "1".
In other cases, the output signals a and b are set to "0". Note that when the instruction decoded by the instruction decoder 31 is a SUB instruction or a SUBNC instruction, the output signals a,
Both b become "1".

The output signal a of the decoder 34 is input to one input terminal of a NAND gate 35, and a signal obtained by inverting the clock signal CK by an inverter 36 is input to the other input terminal. Therefore, when the output signal a of the decoder 33 is "1", a signal synchronized with the clock signal CK is outputted from the latch pulse generator 32 as the latch pulse FLP for the flag register 20.

The output signal SS of the OR gate 33 (FIG. 2) and the carry flag CF which becomes "1" or "0" as a result of the calculation are input to the NAND gate 37. The output of this NAND gate 37 is input to one input terminal of an AND gate 38, and the output signal b of the decoder 34 is input to the other input terminal of the AND gate 38. The output of this AND gate 38 is a plurality of 3-input NAND gates 39
The decoding result of R1 and the inverted signal of the clock signal CK are input to the other input terminals of the three-input NAND gate 39.

Therefore, when the SS signal is "1" and the carry flag CF is "0", the output signal c of the NAND gate 37 becomes "1", and at this time the output signal b of the decoder 34
If is "1", a latch pulse RLP synchronized with the clock signal CK is supplied to the register 17 from the NAND gate 39 selected by the R1 decoding result.

On the other hand, the SS signal is "1" and the carry flag C
When F is "1", the output signal c of the NAND gate 37
becomes “0”, and the output of the AND gate 38, that is, 3
One of the input signals of the input NAND gate 39 becomes "0". As a result, the output signal RLP of the 3-input NAND gate 39
is always “1”, and the register 17 receives the latch pulse RL.
P will not be supplied.

The operation of the arithmetic circuit when the SUBNC instruction is executed will now be described with reference to the operation time chart of FIG. As a result of the SUBNC operation, if the argument is larger than the argument and the carry flag CF becomes "0",
As described above, the latch pulse FLP for the flag register 20 and the latch pulse RLP for the register 17 are outputted from the latch pulse generator 32 at timings synchronized with the clock signal. Then, as shown in FIG. 4(A), the calculation result R is synchronized with the rising edge of the latch pulse RLP.
The carry flag CF is latched in the register 17 indicated by 1, and the carry flag CF is latched in the flag register 20 in synchronization with the rising edge of the latch pulse FLP.

On the other hand, if the argument is smaller than the argument and the carry flag CF becomes "1", the latch pulse FLP for the flag register 20 is generated from the latch pulse generator 32.
is output, but the latch pulse RLP for the register 17 is not output. Therefore, as shown in FIG. 4B, the carry flag CF is latched in the flag register 20 in synchronization with the rise of the latch pulse FLP, but the operation result is not latched in the register 17.

Next, a flowchart for performing division of unsigned binary integers using the above arithmetic circuit will be described with reference to FIG. First, clear the partial remainder register (
Figure 5, S11). The data in the remainder register and partial remainder register are shifted one bit to the left (S12). Next, the partial remainder and the divisor are compared, and if the divisor does not exceed the partial remainder, the value of the divisor register is subtracted from the partial remainder register (S13).

Then, it is determined whether the divisor has been subtracted (S14). If the divisor can be subtracted, set the least significant bit of the dividend register to 1 as the quotient (S
15) It is determined whether the calculations for the number of bits of the dividend have been completed (S16). On the other hand, if subtraction is not possible,
Proceeding directly to step S16, it is determined whether or not the operations for the number of bits have been completed. If it is determined in step S15 that the calculations for the number of bits have not been completed, the process returns to step S12 and repeats the above-described process.

When the operations for the number of bits are completed, the quotient is found in the dividend register and the remainder is found in the partial remainder register (S17). Next, an example of a division program based on the above flowchart will be explained with reference to FIG. The program in FIG. 6 is a division routine for an unsigned binary integer of 16 bits/16 bits. Hereinafter, the differences from the conventional division routine shown in FIG. 11 will be explained.

"SHL AX,1", "RCL D
X, 1" and set the data in the dividend register AX to 1.
The bits are shifted to the left, and the data in the partial remainder register DX is shifted to the left by 1 bit through a carry.

Next, "SUBNC DX, BX" is executed to subtract the divisor BX from the partial remainder register DX. If the partial remainder is smaller than the divisor, the carry flag becomes "1" by subtraction. As a result, the operand "un" of the next conditional jump instruction "JC unsdiv3"
Proceed to the address specified by ``sdiv3''.

In this case, since it is a SUBNC instruction, the signal SS becomes "1", and the subtraction result is negative and the carry flag becomes "1", so the latch pulse generator 32 generates the latch pulse RLP for the register. No output. Therefore, the result of subtraction at this time is not latched in the partial remainder register DX, and the value before subtraction remains as it is in the partial remainder register D.
Saved in X.

On the other hand, if the partial remainder is equal to or larger than the divisor, the subtraction result will be zero or positive and the carry flag will be "0".
”, the above conditional jump instruction is not executed, and the next “INC AL” instruction is executed. This instruction sets the least significant bit of the dividend register AX to "1", which becomes the quotient of the division.

In this case, since it is a SUBNC instruction, the signal SS is "1", but since the carry flag is "0", the latch pulse generator 32 outputs the latch pulse RLP for the register. As a result, the subtraction result at this time is latched into the partial remainder register DX.

As described above, in the above embodiment, when the subtraction result is negative, the latch pulse RLP for latching the subtraction result in the register 17 is not generated, so that unlike the conventional case, the subtraction result is negative. In this case, there is no need to add a divisor to the subtraction result. For example, in the division routine of the embodiment shown in FIG. 6, the ADD instruction and JMP instruction of the conventional division routine of FIG. 11 are unnecessary. These instructions are included in the loop instruction and are repeated for the number of bits in the division, so by eliminating the ADD and JMP instructions, the overall instruction processing time is reduced (ADD instruction execution time + JMP instruction execution time) x number of bits. can be reduced.

The present invention is not limited to the arithmetic circuits and programs described in the embodiments, but can be applied to arithmetic circuits and programs of other configurations. Furthermore, the present invention is applicable not only to programmable controllers but also to other arithmetic devices that calculate division, square roots, etc. by addition and subtraction.

[0054]

[Effects of the Invention] According to the present invention, when the subtraction result obtained by subtracting the divisor from the partial remainder is negative, there is no need to add the divisor to the subtraction result, so the number of instructions of the division program can be reduced. This can reduce the overall processing time.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a configuration diagram of an arithmetic circuit according to an embodiment.

FIG. 3 is a configuration diagram of a latch pulse generation section of the embodiment.

FIG. 4 is an operation time chart of the embodiment when a SUBNC instruction is executed.

FIG. 5 is a flowchart of a division program according to the embodiment.

FIG. 6 is a diagram showing an example of a division program according to the embodiment.

FIG. 7 is a configuration diagram of a conventional arithmetic circuit.

FIG. 8 is a configuration diagram of a conventional latch pulse generation section.

FIG. 9 is an operation time chart of a conventional example when executing a SUB instruction.

FIG. 10 is a flowchart of a conventional division program.

FIG. 11 is a diagram showing an example of a conventional division program.

[Explanation of symbols]

1. Instruction decoding means 2. Calculation means 3 Register 4 Latch pulse generation means

Claims (1)

[Claims] Claim 1: In an arithmetic unit that performs division by combining addition and subtraction instructions, an instruction decoding means (1) for decoding an instruction code is provided.
), a calculation means (2) for executing the calculation decoded by the instruction decoding means (1), a register (3) for latching the calculation result of the calculation means (2), and the calculation means (2). The register (3) is set or reset based on the carry flag set or reset by subtraction in the register (3).
An arithmetic device comprising: latch pulse generating means (4) for generating a latch pulse for controlling writing to.