JPH0435208U - - Google Patents
Info
- Publication number
- JPH0435208U JPH0435208U JP7692890U JP7692890U JPH0435208U JP H0435208 U JPH0435208 U JP H0435208U JP 7692890 U JP7692890 U JP 7692890U JP 7692890 U JP7692890 U JP 7692890U JP H0435208 U JPH0435208 U JP H0435208U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- recording
- amplifier
- reproduction signal
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の１実施例を示すブロツク図、
第２図は従来の磁気デイスク装置の記録・再生系
を示すブロツク図である。
図において、１……ヘツドデイスクアツセンブ
リ、２……磁気ヘツド、３……ヘツドＩＣ、５…
…増幅器、８……再生信号処理回路、９……コン
トローラ、１０……自動利得制御回路。なお、図
中、同一符号は同一または相当部分を示す。
FIG. 1 is a block diagram showing one embodiment of the present invention.
FIG. 2 is a block diagram showing a recording/reproducing system of a conventional magnetic disk device. In the figure, 1...head disk assembly, 2...magnetic head, 3...head IC, 5...
...Amplifier, 8...Reproduction signal processing circuit, 9...Controller, 10...Automatic gain control circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
電流を決定する定電流回路および再生信号を増幅
する増幅器を内蔵した集積回路とを密封構造とし
たヘツドデイスクアツセンブリ、記録電流制御回
路、再生信号処理回路を備える記録・再生系を有
する磁気デイスク装置において、上記集積回路に
、上記増幅器の利得を制御する自動利得制御回路
を設けたことを特徴とする磁気デイスク装置。 A head disk assembly with a sealed structure including a magnetic head, a constant current circuit that determines the recording current supplied to the magnetic head, and an integrated circuit that includes an amplifier that amplifies the reproduction signal, a recording current control circuit, and reproduction signal processing. 1. A magnetic disk device having a recording/reproducing system including a circuit, wherein the integrated circuit is provided with an automatic gain control circuit for controlling the gain of the amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7692890U JPH0435208U (en) | 1990-07-17 | 1990-07-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7692890U JPH0435208U (en) | 1990-07-17 | 1990-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0435208U true JPH0435208U (en) | 1992-03-24 |
Family
ID=31618840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7692890U Pending JPH0435208U (en) | 1990-07-17 | 1990-07-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0435208U (en) |
-
1990
- 1990-07-17 JP JP7692890U patent/JPH0435208U/ja active Pending
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