JPH04346529A - Digital radio communication system - Google Patents

Abstract

PURPOSE:To prevent the pseudo synchronization of an error correction circuit which is caused by the pseudo synchronization of a demodulator. CONSTITUTION:A transmitter 1 inputs a code train 4 out of both code trains 4 and 5 of two series outputted from a convolutional coder 3 and a train 9 which secured the sum of the train 5 into a modulator 10. The modulator 10 modulates both trains 4 and 9. Meanwhile a receiver 20 inputs a data train 23 out of both received transmission data trains 23 and 24 of two series demodulated by a demodulator 22 and a train 28 secured the difference of the train 24 into an error correcting decoder 29. Then the decoder 29 decodes both trains 23 and 28. In such a configuration, the pseudo synchronization of an error correction circuit can be prevented despite the pseudo synchronization caused in a carrier wave reproduction circuit of the demodulator.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital radio communication system, and more particularly to a digital radio communication system to which error correction using convolutional codes used in satellite communication is applied.

0002

2. Description of the Related Art In recent years, small-capacity communication systems have become active in satellite communication systems, mainly VSAT systems, IBS/IDR, and the like. These systems introduce powerful error correction schemes using convolutional coding. In addition, for frequency tracking on the communication side of frequency fluctuations that occur in the satellite system, in order to miniaturize the equipment and reduce equipment costs, pilot receivers, etc. are omitted, and the demodulator itself is required to capture and track the frequency fluctuations that occur in the satellite system. . Conventionally, when the demodulator itself captures and tracks the frequency fluctuations of the satellite system, the frequency of the local oscillator inside the demodulator is swept, the demodulated signal is observed, and the point at which it is determined that the demodulation is being performed correctly is determined by The frequency error was corrected by stopping the sweep at . A state in which demodulation is performed correctly is called a state in which demodulator synchronization is established.

FIG. 2 is a block diagram showing the above-mentioned demodulator control method. In FIG. 2, 201 is a received modulated wave containing a frequency error, 202 is a variable local oscillator whose frequency can be controlled externally, and 203 is a received modulated wave 201.
204 is a modulated wave converted to an intermediate frequency with frequency error corrected, 205 is a demodulation unit that demodulates data, 206 is demodulated data, and 207 is a determination for determining whether synchronization of the demodulator is established. part, 208 is the determination part 2
This is a sweep control unit that controls the oscillation frequency of the variable local oscillator 202 based on the determination result from 07.

To briefly explain this operation, a received modulated wave 201 is modulated to an intermediate frequency by a variable local oscillator 202. The demodulation section 205 generates the modulated wave 20 of the intermediate frequency.
4 and performs demodulation operation. At this time, the determining unit 207 determines whether the data 206 from the demodulating unit 205 is correct demodulated data, that is, whether the synchronization of the demodulator 205 has been established.
When the synchronization of the demodulator 205 is not established, the frequency of the variable local oscillator 202 is swept, and when the synchronization is established, the sweep is stopped and demodulation is continued.

Among the operations described above, it is extremely difficult to establish synchronization of the demodulator 205 by the demodulator 205 alone. In such cases, the usual method is to refer to the document “LSI implementation of variable coding rate error correction device for satellite communication” (Otani et al.: IEICE Technical Report IT87-1).
As shown in 9), an excellent method is to use the synchronization state of the subsequent error correction circuit to determine whether synchronization has been established.

FIG. 3 shows a conventional example in which the method described in the above-mentioned document is used for the configuration of the determining section 207 that determines the establishment of synchronization of the demodulator in FIG. In FIG. 3, 301 is demodulated data;
302 is an error correction decoder, 303 is decoded data, 304
is a reencoder that reconvolutionally encodes the decoded data,
305 is a delay circuit that delays the demodulated data 301 by the decoding delay of the error correction decoder 302; 306 is the re-encoded data; 307 is the demodulated delay data; 308 is the one that compares the re-encoded data 306 and the demodulated delay data 307. 309 is an EOR circuit, 309 is an estimation error, 310 is a BER measurement circuit that integrates the estimation error within a certain period of time and calculates a bit error rate, 311 is BER information, and 312 is a circuit that determines whether or not the BER information is larger than a certain threshold. This is a synchronization determination circuit that determines that if the value is large, it is asynchronous, and if it is small, it is synchronized.

[0007] Demodulated data 301 is decoded into decoded data 303, which is an information source, by an error correction decoder 302, such as a Viterbi decoder or a sequential decoder. This decoded data 301 has been corrected for errors on the transmission path, so
When this is encoded by the re-encoder 304, it becomes transmission data in which almost all errors on the transmission path have been removed. The demodulated delay data 307 delayed by the delay required for decoding by the error correction decoder 302 contains errors on the transmission path, and is compared with the re-encoded data 306 by the EOR circuit 308 to correct the errors on the transmission path. The error can be estimated. This estimation error 309 is counted to measure the bit error rate, and by comparing it with a certain threshold, it is determined whether the error correction circuit is synchronized or not. This synchronous and asynchronous information is used as it is as synchronous and asynchronous information of the demodulator in FIG.

[0008]

The above-mentioned system using synchronization of the error correction decoding circuit has the problem of pseudo-synchronization of the error correction circuit caused by pseudo-synchronization of the carrier recovery circuit of the demodulator. This is because the demodulated data reproduced when the carrier regeneration circuit is pseudo-synchronized becomes an incorrect code word, and the error correction decoder decodes it as incorrect transmission data, so it behaves as if synchronization of the error correction circuit has been established. state. This will be explained in detail below.

As an example, a convolutional code with a constraint length of 7 and a coding rate of 1/2 will be explained. The transmitted code words Cn,p, Cn,q in time slot n are expressed by the following equations 1 and 2, where information data is Dn.

0010

[Math 1]

[0011]

[Math 2]

Generally, in a demodulator that uses coherent detection for carrier recovery, the received carrier fc and the recovered carrier frc
When the frequency error Δf between the symbol rate fs and the symbol rate fs is an integer fraction of the symbol rate fs, that is, when it is expressed by the following equation 3, the carrier recovery circuit enters a pseudo-synchronized state.

[0013]

[Math 3]

The demodulated data reproduced in this state undergoes polarity reversal every n symbols, and the phase shifts by π. originally,
In a communication system such as a PSK system that transmits information through phase changes, the demodulator itself cannot determine whether the π shift in phase is due to Δf.

Now, the code words Cn, shown by Equations 1 and 2,
In QPSK where p, Cn, q are input, Δf=
Demodulated data generated by pseudo-synchronization of the fs/2 carrier recovery circuit is expressed by the following equations 4 and 5.

[0016]

[Math 4]

[0017]

[Math 5]

The demodulated data strings of Equations 4 and 5 are expressed by Equations 6 and 7 below.

[0019]

[Math 6]

[0020]

[Math 7]

When the following number 8 is introduced, these numbers 6 and 7 can be expressed as the following numbers 9 and 10.

[0022]

[Math. 8]

[0023]

[Math. 9]

[0024]

[Math. 10]

By the way, if we use the following relationship of Equation 11 and Equation 12, we can obtain Equation 13 by substituting Equation 1 into Equation 9.

[0026]

[Math. 11]

[0027]

[Math. 12]

[0028]

[Math. 13]

Similarly, by substituting the number 2 into the number 10, the following number 14 is obtained.

[0030]

[Math. 14]

From equations 13 and 14, Zn,p,Z
n, q are code words whose information data is Dn'. Therefore, at this time, the error correction decoder performs normal decoding and determines that the error correction circuit is synchronized, resulting in pseudo synchronization.

In the case of BPSK, inside the modulator on the transmitting side, two input data strings are subjected to parallel/serial conversion to become one data string as shown in the following equation 15.

[0033]

[Math. 15]

On the receiving side, conversely, the fifteen data strings are serial/parallel converted inside the demodulator and returned to two data strings. Therefore, what has been described above can be applied as is.

As can be seen by analogy from the above example, Q
Pseudo-synchronization of the error correction circuit occurs for Δf shown by equation 16 in the case of PSK and Δf shown by equation 17 in the case of BPSK.

[0036]

[Math. 16]

[0037]

[Math. 17]

In such a case, in FIG.
07 issues a command to the sweep control unit 208 to stop the sweep, so the decoded data becomes forever incorrect data. That is, even though Dn is sent, it is decoded as Dn'.

An object of the present invention is to provide a digital wireless communication system that can prevent pseudo-synchronization of an error correction circuit caused by pseudo-synchronization of a demodulator.

[0040]

[Means for Solving the Problems] According to the present invention, a transmitter includes a convolutional encoder that inputs transmission information data, convolutionally encodes it, and outputs two series of convolutional codes; A summation circuit inputs the first series of the two series of convolutional codes and sums the series, and the second of the two series of convolutional codes is input to the first channel as transmission transmission data. a modulator which inputs the sequence and inputs the output sequence of the summing circuit into a second channel and applies digital modulation thereto;
A demodulator that inputs the modulated wave modulated by the modulator, demodulates it, and outputs two series of received and transmitted data, and corresponds to a second channel of the transmitter of the two series of received and transmitted data. A difference circuit which inputs data to calculate the difference between the data strings, and inputs data corresponding to the first channel of the transmitter of the two series of received and transmitted data and the output of the difference circuit to detect an error. A digital wireless communication system is obtained, characterized in that it includes an error correction decoder that performs correction and outputs received information data.

[0041]

Embodiments Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1(a), 1 indicates a transmitter, 2 is a transmitting information data, 3 is a convolutional encoder, 4 and 5 are two series of convolutional codes, and 6 is a summation code. 7 is a first EOR circuit, 8 is a first one-symbol delay device, 9 is an output of a summation circuit, 10 is a modulator, and 11 is a modulated wave output.

In FIG. 1(b), 20 indicates a receiver, in which 21 is a modulated wave input, 22 is a demodulator, and 2 is a receiver.
3 and 24 are the outputs of the demodulator which are two series of received transmission data, 25 is the difference circuit, 26 is the second EOR circuit, 27 is the second 1-symbol delay device, 28 is the output of the difference circuit, and 29 is the error A correction decoder 30 is received information data.

[0045] The present invention solves the problem that conventionally occurred by transmitting two code sequences as they are caused by convolutional coding, by transmitting one of the two code sequences as is and summing the remaining one sequence. This can be solved by adding separate processing and transmitting.

[0046] This will be explained below using FIG. Transmission information data 2 to be transmitted is convolutionally encoded by a convolutional encoder 3, and two series of convolutional codes 4 and 5 are generated.
become. These correspond to those shown by Equation 1 and Equation 2 in the above-mentioned example. Suppose that the convolutional code 4 is Cn of number 1
,p, and the convolutional code 5 is the number Cn,q. 2
In the modulator 10 having two input channels, these two series of convolutional codes 4 and 5 are not input as they are, but the convolutional code 4 of Cn,p is inputted as is on one channel, and the convolutional code 4 of Cn,p is inputted as is on the other channel. The summation output 9, Yn, which has been subjected to summation processing by the summation circuit 6, is input to Cn,q. The sum output 9 is expressed by the following equation 18.

[0047]

[Math. 18]

The summation circuit 6 realizes Equation 18, and sends the output Yn-1 of the previous symbol to the one-symbol delay circuit 8.
The outputs of the convolutional encoder Cn,q and E
The OR circuit 7 takes the sum and outputs Yn. Here, the 1-symbol delay device 8 can be easily realized with a D flip-flop.

The modulated wave digitally modulated by the modulator 10 is input to the demodulator 22 through a transmission path, and two demodulated series of received transmission data 23 and 24 are output from the demodulator. If synchronization of the demodulator is established and demodulation is performed correctly, Cn,p appears in the received transmission data 23, and Yn shown by Equation 18 appears in the received transmission data 24. Now, when the sequence Yn of the received transmission data 24 is input to the difference circuit 25 and subjected to difference processing, the convolutional code Cn,q is obtained according to the following equation 19.

[0050]

[Math. 19]

The difference circuit 25 realizes Equation 19, and delays the input Yn-1 one symbol before by the one-symbol delayer 27, takes the difference between the received transmission data Yn and the EOR circuit 26, and calculates the difference between the received transmission data Yn and the EOR circuit 26. This outputs the following. The error correction decoder 29 receives Cn, which is the received transmission data 23.
, p and Cn,q which is the output 28 of the difference circuit 25 are input, and the received information data 30 which is the correct decoder output is obtained.

Next, consider a case where the carrier regeneration circuit of the demodulator causes pseudo synchronization and correct demodulation is not performed. As a first example, consider the case of QPSK transmission with Δf=fs/2 as described above. Demodulated data at this time,
That is, the two series of received and transmitted data 23 and 24 are as shown by the following equations 20 and 21, respectively, as described above.

[0053]

[Math. 20]

[0054]

[Math. 21]

[0055] Here, received transmission data 2 shown by equation 21
Let's focus on 4. When the data series shown in Equation 21 is input to the difference circuit 25, its output 28 becomes the value shown in Equation 22 below.

[0056]

[Math. 22]

[0057] Here, using the following relationship 23,
The number 22 becomes the next number 24.

[0058]

[Math. 23]

[0059]

[Math. 24]

[0060] Here, if we substitute the above-mentioned number 19 into number 24, we get
It becomes a series of number 25.

[0061]

[Math. 25]

Now, the sequence shown by Equation 20 and the sequence shown by Equation 25 are input to the error correction decoder 29, but in these two data sequences, the original data corresponds to Equation 20 and Equation 25, respectively. Since Dn' and Dn are the same as described above, the code word is not correct and normal decoding cannot be performed. Therefore,
Even if the carrier regeneration circuit of the demodulator is pseudo-synchronized, pseudo-synchronization of the error correction circuit does not occur.

As a second example, a case of transmission using BPSK will be shown. In the transmitter 1, as mentioned above, Cn,p, which is the output 4 of the convolutional encoder 3, and Yn, which is the output 9 of the summing circuit 6, are subjected to parallel/serial conversion inside the modulator and are expressed as the following equation 26. It is modulated and transmitted as a sequence like this.

[0064]

[Math. 26]

Pseudo-synchronization of the carrier wave recovery circuit of the demodulator is Δf
Consider a case where this occurs when = fs /8 and correct demodulation is not performed. The demodulation sequence of the demodulator is the following equation 27.

[0066]

[Math. 27]

The demodulation sequence of this demodulator is subjected to serial/parallel conversion, and two received transmission data sequences shown by the following equations 28 and 29 are output.

[0068]

[Math. 28]

[0069]

[Math. 29]

The series shown by this number 29 is the difference circuit 25
When input to , the output 28 becomes the value shown by the following equation 30.

[0071]

[Math. 30]

[0072] Furthermore, by using the relationship shown in the above equation 23 and the following equation 31, equation 30 becomes the following equation 32.

[0073]

[Math. 31]

[0074]

[Math. 32]

Substituting the number 19 into the number 32 results in the following number 33.

[0076]

[Math. 33]

The sequence shown in Equation 28 and the sequence shown in Equation 33 are input to the error correction circuit 29, but since these cannot be correct code words, normal decoding cannot be performed, and the error correction circuit No pseudo-synchronization occurs.

[0078]

As described above, the digital wireless communication system of the present invention can prevent pseudo-synchronization of the error correction circuit even when the carrier regeneration circuit of the demodulator causes pseudo-synchronization.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a conventional demodulator control scheme.

FIG. 3 is a block diagram showing a circuit for determining the establishment of synchronization of a conventional error correction circuit.

[Explanation of symbols]

1 Transmitter 2 Transmission information data 3 Convolutional encoder 4,5 Convolutional code 6 Integration circuit 7 First EOR circuit 8 First 1-symbol delay device 9 Integration circuit output 10 Modulator 11 Modulated wave output 20 Receiver 21 Modulated wave input 22 Demodulator 23, 24 Received transmission data 25 Differential circuit 26 Second EOR circuit 27 Second 1-symbol delay device 28 Differential circuit output 29 Error correction decoder 30 Reception information data

Claims (1)

[Claims] Claim 1: A transmitter includes a convolutional encoder that inputs transmission information data, convolutionally encodes the data, and outputs two series of convolutional codes, and a first one of the two series of convolutional codes. A summation circuit inputs the series of convolutional codes and sums the series, and inputs the second series of the two series of convolutional codes to the first channel as transmission transmission data, and also inputs the second series of the two convolutional codes to the second channel as transmission data. has a modulator that inputs the output series of the summation circuit and applies digital modulation thereto, and the receiver inputs the modulated wave modulated by the modulator, demodulates it, and modulates it. a demodulator that outputs the series of received transmission data; a difference circuit that inputs data corresponding to a second channel of the transmitter of the two series of received transmission data and calculates a difference between the data series; an error correction decoder that receives data corresponding to the first channel of the transmitter out of the series of received transmission data and the output of the differential circuit, performs error correction, and outputs received information data; A digital wireless communication system characterized by